KR100548570B1 - Metal wiring formation method of semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device, comprising the steps of: providing a semiconductor substrate having a cell region and a ferry region defined therein; a gate structure in which a floating gate / dielectric film / control gate is stacked on the substrate; Forming respective sources / drains on the substrates on both sides of the gate structure, and forming a dual damascene trench structure on a portion corresponding to the gates and drains of the source, drain and ferry regions of the first oxide layer and the cell region on the entire surface of the resultant. Forming a second oxide film in sequence, forming a first diffusion barrier film filling the trench of the second oxide film, forming a first metal film on the entire surface of the substrate including the first diffusion barrier film, and first metal Forming a photoresist pattern on the film, the photoresist pattern exposing portions corresponding to the gate and the drain of the source, the drain, and the ferry region; Etching the first metal layer and the first diffusion barrier layer using a photoresist pattern as a mask to form a metal hard mask, removing the photoresist pattern, and etching the layers by using a metal hard mask as an etching barrier. Forming a contact hole for exposing the gate and the drain of the source, the drain, and the ferry region, respectively, exposing the floating gate of the gate by the contact hole, and forming a plug to fill the contact hole. .

Description

Method for forming metal line of semiconductor device

1A to 1G are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

Figure 2 is an enlarged view showing only metal wiring according to the present invention.

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming metal wiring of a semiconductor device having a damascene structure.

In the damascene structure of a semiconductor device, a wet cleaning process is used to secure a contact resistance with a substrate, wherein an etching ratio difference between a silicon nitride film used as an etch stop film and an oxide film formed above and below the silicon nitride film occurs. do. At this time, if the oxide film is severely collapsed or the metal film embedding process is not performed properly in the subsequent process, an electrical short with the neighboring pattern is generated. In addition, the trench of the oxide film in which the metal film for metal wiring is embedded is wet in both directions. Etching results in increased crosstalk. Therefore, in the exposure and etching process for forming a fine trench of 100 nm or less, it is important to secure an oxide bar CD (Critical Dimension) to improve the crosstalk generated in the metal film. Since the CD of the trench or contact of the oxide layer to be buried becomes smaller, it is difficult to determine the photoresist that serves as an etch barrier. In other words, in order to etch the high trench fine trench or contact, a photoresist having a step ratio of 3: 1 to 5: 1 is used, which causes a photoresist collapse or DOF (Depth Of Focus) margin problem.

On the other hand, when a single damascene method or an etch back method of a tungsten metal film is applied to form a metal wiring, in the case of a micro contact, the contact area with the upper metal wiring is narrow and the electrical resistance is relatively low. It becomes bigger.

The present invention is to solve the above problems, by forming a metal wiring contact hole by applying a metal hard mask instead of a photoresist film as an etch stop film, a semiconductor device that can improve the DOF margin due to crosstalk and topology It is to provide a method of forming metal wiring.

In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention comprises the steps of providing a semiconductor substrate having a cell region and a ferry region defined, and the floating gate / dielectric film / control gate stacked on the semiconductor substrate Forming a gate structure and forming a source / drain on both sides of the gate structure of the semiconductor substrate, and corresponding portions of the first oxide layer and the source and drain regions of the cell region and the gate and drain regions of the cell region on the entire surface of the resultant substrate. Sequentially forming a second oxide film having a dual damascene trench structure, forming a first diffusion barrier layer filling the trench formed in the second oxide layer, and the second diffusion layer including the first diffusion barrier layer. Forming a first metal film on an entire surface of an oxide film, and forming the source / cell of the cell region on the first metal film. Forming a photoresist pattern exposing a portion corresponding to a gate and a drain of the lane and the ferry region, and etching the first metal layer and the first diffusion barrier layer using the photoresist pattern as a mask to form a metal hard mask And removing the photoresist pattern, and forming a contact hole exposing the source / drain of the cell region and the gate and drain of the ferry region, respectively, by etching the layers with the metal hard mask as an etch barrier. However, the method may include exposing the floating gate of the gate to be exposed by the contact hole, and forming a plug to fill the contact hole.

After the forming of the first oxide film, the step of sequentially forming an etch stop film and a second oxide film on the first oxide film, and adding the step of etching the second oxide film until the etch stop film is exposed. desirable.

The etch stop film is formed of any one of a silicon oxide film and a silicon nitride film, wherein the silicon oxide film is preferably formed of any one of a SiN film and a SiON film.

It is preferable to form the etch stop film by any one of LPCVD and PECVD in the furnace.

The forming of the plug in the contact hole may include sequentially forming a second diffusion barrier layer and a second metal layer on the entire surface of the substrate including the contact hole, and the second metal layer and the second diffusion layer until the second oxide layer is exposed. It is preferable to further add a step of forming a plug for embedding the contact hole by the CMP to prevent the barrier film.

In the CMP process, it is preferable to remove the second metal film by using a vaporized SiO 2 and a hemispherical Al 2 O 3 having a pH of 2 to 8 and a particle size of 50 to 150 nm.

Preferably, the first diffusion barrier and the second diffusion barrier are formed of any one of a PVD Ti / TiN film, a CVD Ti / TiN film, and a WN film.

The metal hard mask forming process and the contact hole forming process may be performed in-situ in one chamber or in a multiple chamber.

It is preferable to form the second oxide film with a thickness of 2000 to 4000 microns using any one of an oxide film of BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP-USG, HDP-PSG, and APL.

(Example)

Hereinafter, a method of forming metal wirings of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device according to the present invention.

In the method for forming metal wirings of a semiconductor device according to the present invention, as shown in FIG. 1A, first, a semiconductor substrate 1 in which a cell region and a ferry region are defined is provided. Subsequently, a gate structure in which the floating gate 3, the dielectric film 4, and the control gate 5 are sequentially stacked is formed on the substrate 1 through the gate insulating film 2. At this time, the control gate 5 adopts a triple stacked structure of a polycrystalline silicon film / tungsten silicide film / hard silicon nitride film.

Then, insulating spacers 6 are formed on both sides of the gate structure, and ion implantation is performed to form a source / drain (not shown) on both sides of the gate structure, respectively. Thereafter, the first silicon nitride layer 7 is deposited on the entire surface of the resultant substrate and selectively etched to expose the upper portion of the gate structure of the ferry region.

Subsequently, a first oxide layer 9 and a second oxide layer 11 are sequentially formed on the resultant. Then, a second silicon nitride film 13 and a third oxide film 15 are sequentially formed on the second oxide film 11, and then the third oxide film 15, the second silicon nitride film 13, and The second oxide layer 11 is sequentially etched to form a dual damascene trench structure. The dual damascene trench structure may be formed by selectively etching only the third oxide layer 15 using the second silicon nitride layer 13 as an etch stop layer. The second silicon nitride film 13 is formed by depositing a SiN film or a SiON film in any one of a low pressure chemical vapor deposition (LPCVD) and a plasma enhanced chemical vapor deposition (PECVD) in a furnace. .

In addition, the pattern of the third oxide layer 15 has a dual damascene trench structure at portions corresponding to the gates and drains of the source, drain, and ferry regions of the cell region. Here, the third oxide film 15 may include BoroPhosphoric Silicate Glass (BPSG), Phosphoric Silicate Glass (PSG), Fulorine-doped Silicate Glass (FSG), Plasma Enhanced-BoroPhosphoric Silicate Glass (PE-TEOS), and PE-SiH4. It is formed to a thickness of 2000 ~ 4000Å using any one of the oxide film of HDP-USG (High Density Plasma-Undoped Silicage Glass), HDP-PSG and APL (Advanced Planarization Layer).

Meanwhile, reference numeral 13, which is not described, shows the second silicon nitride layer 13 remaining after the etching process.

Subsequently, as shown in FIG. 1B, the pattern of the third oxide layer 15 forms a first diffusion barrier layer 17 to fill the dual damascene trench structure, and then the first diffusion barrier layer 17. The first metal film 19 is formed on the entire surface of the substrate including the (). At this time, the material of the first diffusion barrier 17 is any one of a PVD (Physical Vapor Deposition) Ti / TiN film, CVD Ti / TiN film and WN film, and the first metal As the material of the film 19, any one of a CVD tungsten film, a TiSiX film, a TiN film, a Cu film, and an Al film is used.

Meanwhile, in the present invention, after forming the third oxide film pattern having the dual damascene trench structure, the first metal film forming process is performed without a separate wet cleaning process, but there is no effect on the resistance.

Subsequently, as shown in FIG. 1C, a photoresist film is coated on the entire surface of the substrate including the first metal film 19, and then exposed and developed to provide a metal wiring contact region (not shown), that is, a source, drain and ferry region of the cell region. A photosensitive film pattern 21 is formed to expose a portion corresponding to the gate and the drain. In this case, although not shown in the drawing, a process of interposing the anti-reflection film between the first metal film 19 and the photoresist pattern 21 is omitted.

Subsequently, as shown in FIG. 1D, the first metal layer 19 and the diffusion barrier layer 17 are etched using the photoresist pattern 21 as a mask to form a metal hard mask 19a. Then, the photosensitive film pattern 21 is removed.

Then, as illustrated in FIG. 1E, the films are etched using the metal hard mask 19a as an etch barrier to expose the source, drain and gate of the cell region and the gate and drain of the ferry region, respectively. The hole 22 is formed. In this case, when the contact hole 22 exposing the gate of the ferry region is formed, the control gate and the dielectric layer are etched to pattern the upper surface of the floating gate.

Meanwhile, the metal hard mask 19a forming process and the contact hole forming process corresponding to FIGS. 1D and 1E may be performed in-situ in one chamber or may be multi-chambered. can proceed in -chamber.

Thereafter, as illustrated in FIG. 1F, a cleaning process (not shown), such as a wet cleaning method or a dry cleaning method, is performed on the entire surface of the substrate including the contact hole 22, and then a second surface of the substrate is cleaned. The diffusion barrier 23 and the second metal layer 24 are sequentially formed. At this time, the cleaning process is to reduce the contact resistance with the substrate. In addition, during the cleaning process, since the remaining first diffusion barrier layer 17 acts as a barrier, there is no fear that the oxide component of the third oxide layer 15 may be lost. The second diffusion barrier 23 is formed using the same method and material as the first diffusion barrier 17, and the second metal layer 24 is formed using the same method and material as the first metal layer 19. Can be.

Subsequently, as illustrated in FIG. 1G, the CMP of the second metal layer 24, the second diffusion barrier 22, and the metal hard mask 19a is sequentially turned on until the surface of the third oxide layer 15 is exposed. (Chemical Mechnical Polishing) to form a cylindrical plug-in metal wiring 25 for embedding the cylindrical contact hole (22). Here, the metal hard mask 19a not only serves as an etch barrier in forming the contact hole 22 but also serves to reduce the step in the second metal film CMP process for forming the plug-in metal wiring 25. In the CMP process, the second metal film is removed using humed SiO 2 having a pH of 2 to 8 and a particle size of 50 to 150 nm and Al 2 O 3 having a hemispherical shape.

Figure 2 is an enlarged view showing only metal wiring according to the present invention.

In the present invention, as shown in FIG. 2, the metal wiring 25 has a structure including a plug and a first diffusion barrier film 17 surrounding an upper portion of the plug. Therefore, the metal wiring having the above structure can not only prevent resistance increase and short circuit of the metal wiring, but can also reduce crosstalk.

As described above, the present invention forms a metal hard mask using a first metal film instead of using a conventional photoresist film which lacks a margin as an etch stop film in an etching process for forming a contact hole of a metal size for wiring. By performing the contact hole etching process, the second metal film filling process, and the CMP process to form the metal wiring, the DOF margin due to the crosstalk and the topology can be improved. In addition, the present invention can reduce the crosstalk in the metal film for metal wiring, there is an advantage such as the reliability of the device, the operation speed improvement and the yield improvement.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (13)

Providing a semiconductor substrate in which a cell region and a ferry region are defined; Forming a gate structure in which a floating gate / dielectric film / control gate is stacked on the semiconductor substrate, and forming a source / drain on both sides of the gate structure of the semiconductor substrate; Sequentially forming a first oxide film and a second oxide film having a dual damascene trench structure in a region corresponding to a source, a drain, and a gate and a drain of a cell region on the entire surface of the resultant; Forming a first diffusion barrier layer filling the trench formed in the second oxide layer; Forming a first metal film on the entire surface of the second oxide film including the first diffusion barrier film; Forming a photoresist pattern on the first metal layer to expose portions corresponding to the source / drain of the cell region and gates and drains of the ferry region; Etching the first metal layer and the first diffusion barrier layer using the photoresist pattern as a mask to form a metal hard mask; Removing the photoresist pattern; The metal hard mask is used as an etch barrier and the layers are etched to form contact holes for exposing the source / drain of the cell region and the gate and drain of the ferry region, respectively, wherein the floating gate of the gate is formed by the contact hole. To expose it, And forming a plug to fill the contact hole. According to claim 1, After the first oxide film forming step, Sequentially forming an etch stop film and a second oxide film on the first oxide film; And etching the second oxide film until a point where the etch stop layer is exposed. The method of claim 2, wherein the etch stop film is formed of any one of a silicon oxide film and a silicon nitride film. 4. The method of claim 3, wherein the silicon nitride film is formed of any one of an SiN film and a SiON film. 4. The method of claim 3, wherein the etch stop film is formed in a furnace by any one of LPCVD and PECVD. The method of claim 1, wherein the forming of the plug in the contact hole is performed. Sequentially forming a second diffusion barrier layer and a second metal layer on the entire surface of the substrate including the contact hole; And forming a plug to fill the contact hole by CMPing the second metal film and the second diffusion barrier layer until the second oxide film is exposed. The method of claim 6, wherein the CMP process removes the second metal film using SiO 2 having a pH of 2 to 8 and particle size of 50 to 150 nm, and Al 2 O 3 having a hemispherical shape. 7. The metal line formation of the semiconductor device according to claim 6, wherein the first diffusion barrier and the second diffusion barrier are formed of any one of a PVD Ti / TiN film, a CVD Ti / TiN film, and a WN film. Way. 7. The method of claim 6, wherein the first metal film and the second metal film are formed by depositing any one of tungsten, TiSiX, TiN, Cu, and Al by CVD. The method of claim 1, wherein the metal hard mask forming process and the contact hole forming process are performed in-situ in one chamber. The method of claim 1, wherein the metal hard mask forming process and the contact hole forming process are performed in multiple chambers. The semiconductor device of claim 1, wherein the second oxide layer is formed of one of BPSG, PSG, FSG, PE-TEOS, PE-SiH4, HDP-USG, HDP-PSG, and APL oxide films. How to form metal wiring. 2. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the second oxide film is formed to a thickness of 2000 to 4000 micrometers.

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