KR100541703B1 - Gate Forming Method of Semiconductor Device Using Double Layer Patterning - Google Patents

Abstract

The present invention discloses a method for forming a gate of a semiconductor device using double layer patterning, the method of the present invention comprising the steps of sequentially forming a gate oxide film and a first polysilicon film on a semiconductor substrate; Patterning the first polysilicon layer and the gate oxide layer to form a lower gate having a fine line width; Forming a first nitride film to have a flat surface while completely covering the lower gate on the substrate; Etching a portion of the first nitride film to form a groove exposing the lower gate surface and a portion of the first nitride film adjacent thereto; Depositing a second nitride film on the groove surface and the first nitride film; Etching the entire surface of the second nitride layer to form a spacer on a groove wall; Depositing a second polysilicon film to fill the groove on the substrate resultant; CMPing the second polysilicon film until the first nitride film is exposed to form an upper gate in the groove having an upper width greater than a lower width of the lower gate; And removing the spacer and the first nitride film. According to the present invention, the width of the upper gate may be larger than the lower gate width while the gate is configured as a double layer, thereby realizing a fine channel length and securing a contact margin to the gate in the metallization process.

Description

TECHNICAL FOR FORMING GATE OF SEMICONDUCTOR DEVICE USING DOUBLE LAYER PATTERNING

1A to 1C are cross-sectional views illustrating a conventional MOSFET device forming method.

2A through 2G are cross-sectional views illustrating processes for forming a gate using double layer patterning according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20: semiconductor substrate 21: gate oxide film

22: first polysilicon film 22a: lower gate

23: first resist pattern 24: low concentration impurity region

25: first nitride film 26: second resist pattern

27: groove 28: second nitride film

28a: nitride film spacer 29: second polysilicon film

29a: upper gate 30: gate

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a gate forming method using double layer patterning to secure a contact margin while having a fine channel length.

As the integration of semiconductor devices proceeds, the line width of the gate is reduced, and accordingly, various technologies for realizing low resistance in the fine line width have been researched and developed.

Here, polysilicon is mainly used as the gate material, and such polysilicon is not only easy to handle, but also has a desired conductivity type according to the type and doping concentration of the dopant, and at the same time, it can have an appropriate level of specific resistance. As various uses.

Hereinafter, a conventional MOSFET device manufacturing method will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, in a state in which P-type and N-type wells (not shown) are formed through well-ion implantation in the semiconductor substrate 10, the gate oxide film 11 is formed on the substrate 10. And the polysilicon film 12 are formed in this order. Then, a resist pattern 13 is formed on the polysilicon film 12 to define a gate formation region. Here, the thickness of the resist pattern 13 is determined in consideration of the etching selectivity of the resist to polysilicon in the subsequent dry etching.

Next, as shown in FIG. 1B, the polysilicon film and the gate oxide film are dry-etched using the resist pattern as an etch barrier, thereby forming a gate 12a and then removing the resist pattern. .

Here, the line width of the gate 12a depends on the width of the resist pattern formed in the previous process and its thickness, in particular, the width, wherein the width of the resist pattern is determined by the resolution limit in the exposure process.

Next, as shown in FIG. 1C, after the low concentration ion implantation of impurities into the substrate product, spacers 13 are formed on both sidewalls of the gate 12a through deposition of an insulating film and a blanket etch thereto. ), And then a high concentration ion implantation of impurities into the substrate resultant to form a source / drain region 14 on the substrate surface on both sides of the gate 12a including the spacer 13 to form a MOSFET device. .

Here, the channel length in the MOSFET device is the sum of the gate width and the width of the spacers formed on both sides of the gate, and the reduction in the channel length can be achieved by reducing the width of the resist pattern, which is an etch barrier during gate formation. have.

However, according to the conventional gate forming method, the line width of the gate can be reduced by improving the resolution in the exposure process, thereby realizing a fine channel length that meets the trend of high integration, but when the gate line width is reduced, As the overlap margin of the contact hole is reduced in the metallization process, electrical short between the gate and the source / drain regions may occur.

As a result, the conventional gate forming method has difficulty in realizing a fine channel length and at the same time securing a contact margin due to the reduction of the line width of the gate.                         

Accordingly, an object of the present invention is to provide a gate forming method for securing a contact margin while having a fine channel length.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a gate oxide film and a first polysilicon film on a semiconductor substrate; Patterning the first polysilicon layer and the gate oxide layer to form a lower gate having a fine line width; Forming a first nitride film to have a flat surface while completely covering the lower gate on the substrate; Etching a portion of the first nitride film to form a groove exposing the lower gate surface and a portion of the first nitride film adjacent thereto; Depositing a second nitride film on the groove surface and the first nitride film; Etching the entire surface of the second nitride layer to form a spacer on a groove wall; Depositing a second polysilicon film to fill the groove on the substrate resultant; CMPing the second polysilicon film until the first nitride film is exposed to form an upper gate in the groove having an upper width greater than a lower width of the lower gate; And removing the spacers and the first nitride layer.

Here, the groove is formed to a size such that the lower gate surface is not covered by the spacer.

According to the present invention, the width of the upper gate may be larger than the lower gate width while the gate is configured as a double layer, thereby realizing a fine channel length and securing a contact margin to the gate in a metal wiring process.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views illustrating processes for forming a gate according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, N-type and P-type wells (not shown) form a gate oxide film 21 on a semiconductor substrate 20 through well-ion implantation, and on the gate oxide film 21. The first polysilicon film 22 is deposited. Here, the first polysilicon film 21 is preferably deposited to a thickness lower than the thickness of the gate to be finally obtained, for example, about half the thickness.

Subsequently, in a state where a resist is applied on the first polysilicon film 22, it is exposed and developed to form a first resist pattern 23 defining a gate formation region. Here, the coating thickness of the resist is determined in consideration of the etching selectivity of the resist to the polysilicon generated during the dry etching using the plasma, and the first resist pattern 23 obtained by exposure and development is implemented. It is formed to have a width corresponding to the desired fine channel length.

Referring to FIG. 2B, the first polysilicon layer and the gate oxide layer are dry-etched using the first resist pattern as an etch barrier, thereby forming the lower gate 22a having a fine line width.

Thereafter, while the first resist pattern used as the etching barrier is removed, low concentration ion implantation is performed on the substrate resultant to form a low concentration impurity region 24 on the substrate surface on both sides of the lower gate 22a. Here, the thickness of the low concentration impurity region 24 is preferably equal to or less than half of the gate thickness finally obtained.

Referring to FIG. 2C, the first nitride film 25 is deposited on the entire region of the substrate 20 to cover the lower gate 22a, and the surface thereof is planarized by chemical mechanical polishing (CMP). Then, after applying a resist on the planarized first nitride film 25, the resist is exposed and developed to form a second resist having an opening pattern of a width of the lower gate 22a, more precisely, larger than the channel length. The pattern 26 is formed.

Referring to FIG. 2D, the first nitride layer 25 is etched using the second resist pattern as an etch barrier, and through this, a groove for exposing the lower gate surface and a portion of the first nitride layer adjacent thereto is exposed. ).

Then, in the state where the second resist pattern is removed, the second nitride film 28 is formed on the surface of the groove 27 and the first nitride film 25 with a uniform thickness while being thinner than the first nitride film 25. Deposit.

Referring to FIG. 2E, the nitride nitride spacer 28a is formed on the wall surface of the groove 27 by bulk etching the second nitride layer. In this case, the nitride layer spacer 28a is formed so that the exposed surface of the lower gate 22a is not covered, and thus, the groove 27 and the second nitride layer are formed on the wall surface of the groove 27. After is formed, it is preferable that the surface of the lower gate 22a is formed to have a size and a thickness not covered by the nitride film spacer 28a.

Subsequently, the second polysilicon film 29 is deposited on the substrate resultant so that the groove 27 in which the nitride film spacer 28a is formed on the wall is completely embedded.

Referring to FIG. 2F, the surface of the second polysilicon film is CMP until the first nitride film 25 is exposed, thereby forming an upper gate 29a in the groove in which the nitride film spacer 28a is formed on the wall. At this time, the upper width of the upper gate 29a is larger than the lower width of the lower gate 22a, that is, the channel length.

Referring to FIG. 2G, a wet etching process is performed on the substrate resultant to remove the first nitride layer and the nitride spacer, thereby forming a double layer gate 30 according to the present invention.

Here, the double layer gate 30 of the present invention is different from each other in the lower width and the upper width, in particular, because the lower width is formed as a fine width can implement a fine channel length, and the upper width is relative to the lower width Due to the large formation, the contact margin may be increased in a subsequent metallization process.

As described above, the present invention forms a double layer gate having a lower width and a lower width and a larger upper width than the lower width through double layer patterning, thereby realizing fine channel lengths. It is possible to improve contact margins, and thus to enable the implementation of high integration and high speed devices, and to improve device characteristics.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (2)

Sequentially forming a gate oxide film and a first polysilicon film on the semiconductor substrate; Patterning the first polysilicon layer and the gate oxide layer to form a lower gate having a fine line width; Forming a first nitride film to have a flat surface while completely covering the lower gate on the substrate; Etching a portion of the first nitride film to form a groove exposing the lower gate surface and a portion of the first nitride film adjacent thereto; Depositing a second nitride film on the groove surface and the first nitride film; Etching the entire surface of the second nitride layer to form a spacer on a groove wall; Depositing a second polysilicon film to fill the groove on the substrate resultant; CMPing the second polysilicon film until the first nitride film is exposed to form an upper gate in the groove having an upper width greater than a lower width of the lower gate; And And removing the spacers and the first nitride film. The method according to claim 1, wherein the groove size and the deposition thickness of the second nitride film are formed to have a size and a thickness such that the lower gate surface is not covered by a spacer.

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