KR100525900B1 - Static random access memory cell and manufacturing method thereof - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a static random access memory cell and a method of manufacturing the same.

2. Technical problem to be solved by the invention

In order to improve the characteristics of the device by suppressing the generation of the P-N diode generated in the node contact formed between the N-type and P-type gate.

3. Summary of the Solution of the Invention

A method of manufacturing a static random access memory cell according to the present invention includes forming a field oxide film on a well formed semiconductor substrate to define an active region, and then forming an access transistor and a driver transistor, and forming an access transistor and a driver transistor on the entire structure on which the driver transistor is formed. Sequentially forming a first insulating layer, a ground potential line, and a second insulating layer, and sequentially etching selected portions of the second and first insulating layers to expose a portion of a gate of the driver transistor and a portion of the active region. Forming a contact hole, forming a metal plug in the node contact hole, and forming a thin film transistor electrically connected to the metal plug.

4. Important uses of the invention

Any semiconductor device that wants to prevent the creation of P-N diodes.

Description

Static random access memory cell and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell and a method of manufacturing the same, and more particularly, to embedding tungsten-plug in a node contact hole where a PN diode is formed, thereby suppressing the formation of the P-diode diode. The present invention relates to a static random access memory cell (SRAM) capable of improving the characteristics of and a method of manufacturing the same.

In general, a unit cell in a static random access memory cell is composed of two driver transistors, two access transistors, and two load elements. Increasingly, high load resistors use thin film transistors (TFTs), especially for 4M SRAMs and above, with stand-by current (ISB) and data retention voltages. In order to maintain voltage (Vccdr) characteristics, a thin film transistor structure is widely employed.

In a conventional static random access memory cell, an NMOS and a PMOS are simultaneously formed in a cell, and a PMOS P-type gate and an N-type gate (driver transistor gate), a ground potential line, and the like are formed in a circuit, and then the drive transistor gate is formed. It is formed on one side and has a structure in which the first contact is formed to expose a portion of the junction of the N-type active region. In this structure, a first contact is formed between the N-type and P-type gates so that the N-type and P-type gates are connected to each other through an interconnection layer, which forms a PN diode, and thus This increases the contact resistance of the first contact (node contact) region. In order to suppress this problem, recently, after defining a node contact, a photoresist used as a node contact mask is removed, and then a node contact plug ion implantation process through a blanket ion implantation is performed.

In the above, in order to suppress problems such as an increase in contact resistance as much as possible, it is not possible to increase the dose at the time of node contact plug ion implantation, which is infinite because the punch characteristics between the node contacts may be degraded. This can cause the dose to not increase. For this reason, parasitic PN diodes deteriorate thin film transistor (TFT) characteristics at low voltage, and have difficulty in securing cell stability and optimum device characteristics. Note acts as a factor

In addition, since the conductors of the node contacts are formed by forming the node contact holes, depositing undoped polysilicon, and then ion implanting, the conductors of the node contacts may be formed to ensure uniform conductivity. Size is required to a considerable extent.

Accordingly, the present invention eliminates the parasitic PN diode formed by embedding a tungsten plug as an interconnection layer in a node contact hole formed between an N-type and a P-type gate, thereby improving the characteristics of the device. The object is to provide a cell and a method of manufacturing the same.

In accordance with another aspect of the present invention, there is provided a static random access memory cell including a driver transistor, an access transistor, and a load element, wherein the node contact electrically interconnects the driver transistor and the load element. It characterized by comprising a metal layer.

A method of manufacturing a static random access memory cell according to the present invention for achieving the above object comprises forming a field oxide film on a well formed semiconductor substrate to define an active region, and then forming an access transistor and a driver transistor; Sequentially forming a first insulating layer, a ground potential line, and a second insulating layer on the entire structure in which the transistor is formed, sequentially etching selected portions of the second and first insulating layers, and a part of the gate of the driver transistor; Forming a node contact hole through which a portion of the active region is exposed, forming a metal plug in the node contact hole, and forming a thin film transistor electrically connected to the metal plug. do.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1E are cross-sectional views sequentially illustrating a method of manufacturing a static random access memory cell according to the present invention.

Referring to FIG. 1A, a field oxide film 32 is formed on a semiconductor substrate 31 having P-wells and N-wells to define an active region, and then a gate oxide film and a gate polysilicon layer are formed. . The gate polysilicon layer and the gate oxide layer are sequentially etched through an etching process using a mask, and an impurity ion implantation process is performed to form a junction, and thus, the gate oxide layer 33 and the gate of the access transistor (not shown) are performed. And the gate 34 of the driver transistor is formed. After forming the first insulating layer 35 to electrically protect and insulate the device, form the polysilicon layer for the ground potential line, and then form the ground potential line 36 through an etching process using a mask, The second insulating layer 37 for electrically protecting and insulating the film is formed.

In the above, the gate 34 and the ground potential line 36 of the driver transistor are formed using a polysilicon layer, but the polysilicon layer and the metal silicide layer are laminated to form a metal polyside layer in order to reduce electrical resistance. The first and second insulating layers 35 and 37 may be planarization layers formed by depositing a thermal oxide film and a BPSG film.

Referring to FIG. 1B, a portion of the gate 34 of the n-type driver transistor and the semiconductor substrate 31 are formed through an etching process using a contact mask on a selected portion of the planarization layer on which the second insulating layer 37 is formed. The node contact hole 38 is formed by sequentially etching the second and first insulating layers 37 and 35 to expose a portion of the second and first insulating layers 37 and 35.

Referring to FIG. 1 (c), after the barrier metal layer and the tungsten layer are sequentially formed to sufficiently fill the node contact hole 38 on the entire structure in which the node contact hole 38 is formed, a blanket etching process is performed. The tungsten layer and the barrier metal layer are sequentially etched, whereby the tungsten plug 39 is formed only in the node contact hole 38.

Referring to FIG. 1 (d), a polysilicon layer for gate of a thin film transistor is formed on the entire structure in which the tungsten plug 39 is formed, and then the thin film connected to the tungsten plug 39 through an etching process using a mask. The gate 40 of the transistor is formed. Here, the gate 40 of the thin film transistor is p-type.

Referring to FIG. 1E, a gate oxide film and a channel polysilicon layer are sequentially formed on the entire structure in which the gate 40 of the thin film transistor is formed, and then the polysilicon layer and gate for the channel are etched using a mask. By etching the oxide film to form the gate oxide film 41 and the channel region 42 of the thin film transistor, a thin film transistor is formed, and the thin film transistor serves as a load element.

Thereafter, a planarization process (depositing a load oxide film and a load BPSG film), a metal wiring forming process, and a back-end process are performed to fabricate a static random access memory cell.

The static random access memory cell formed by the above-described manufacturing method is composed of a driver transistor 34, an access transistor, and a thin film transistor (load element), wherein the node contact electrically interconnects the driver transistor 34 and the load element. That is, tungsten-plug 39 is composed of a metal layer such as barrier metal / tungsten or tungsten.

As described above, the present invention is a structure consisting of an N-type gate and a P-type gate, and an N-type active and node contact, by embedding a tungsten plug instead of a polysilicon layer as an interconnect layer in the node contact hole. Eliminates parasitic PN diodes in the device, improving device characteristics and eliminating node contact plug ion implantation, resulting in a punch-to-node contact (BVDSS between node-to-node or node-to-node bar) It is possible to secure process margins. In addition, since the node contacts are made of metal, they have lower resistance values than conventional contact resistors, thereby securing margins on the side of the device, and using a smaller contact size, thereby securing margins and process margins on design rules. have.

1 (a) to 1 (e) are cross-sectional views sequentially illustrating a method of manufacturing a static random access memory cell according to the present invention.

<Description of Signs of Major Parts of Drawings>

31 semiconductor substrate 32 field oxide film

33: gate oxide film 34: gate of driver transistor

35 first insulating layer 36 ground potential line

37: second insulating layer 38: node contact hole

39: tungsten-plug 40: gate of thin film transistor

41: gate oxide film of thin film transistor

42: channel region of a thin film transistor

Claims (4)

A semiconductor substrate having a driver transistor having an access transistor and a gate of a type conductivity type, An interlayer insulating layer formed on the semiconductor substrate and including a metal layer connected to a gate of the driver transistor; A P-type conductive TFT gate electrode formed on the interlayer insulating film and connected to the gate of the driver transistor through the metal layer; And a gate oxide film and a channel layer stacked on the TFT gate electrode and an interlayer insulating film adjacent thereto. The method of claim 1, And the metal layer is formed of any one of tungsten and barrier / tungsten. Forming a field oxide film on the well formed semiconductor substrate to define an active region, and then forming a driver transistor having an access transistor and an n-type conductivity gate; Sequentially forming a first insulating layer, a ground potential line, and a second insulating layer on the entire structure; Sequentially etching selected portions of the second and first insulating layers to form node contact holes exposing a portion of the gate and the active region of the driver transistor; Forming a metal plug in the node contact hole; Forming a p-type conductive TFT gate electrode electrically connected to the metal plug; And forming a channel layer on the TFT gate electrode and the second interlayer insulating layer adjacent thereto, the channel layer being interposed therebetween. The method of claim 3, wherein And the metal plug is formed of any one of tungsten and barrier metal / tungsten.