KR100525300B1 - 소자분리막 형성 방법 - Google Patents
소자분리막 형성 방법 Download PDFInfo
- Publication number
- KR100525300B1 KR100525300B1 KR10-2003-0095629A KR20030095629A KR100525300B1 KR 100525300 B1 KR100525300 B1 KR 100525300B1 KR 20030095629 A KR20030095629 A KR 20030095629A KR 100525300 B1 KR100525300 B1 KR 100525300B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- etching
- insulating film
- hard mask
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (4)
- 소자분리막 형성 방법에 있어서,하드 마스크 및 절연막이 형성된 기판을 평탄화하는 단계;상기 기판의 가장자리 부분의 절연막을 단일 습식 식각 장치를 이용하여 선택적으로 식각하는 단계; 및상기 기판의 중심부에서 메인 식각을 실시하는 단계를 포함하여 이루어짐을 특징으로 하는 소자분리막 형성 방법.
- 제 1항에 있어서,상기 절연막은 산화막임을 특징으로 하는 소자분리막 형성 방법.
- 제 1항에 있어서,상기 절연막이 형성된 기판은 STI가 형성된 기판임을 특징으로 하는 소자분리막 형성 방법.
- 제 1항에 있어서,상기 절연막을 선택적으로 식각하는 단계는 불산을 이용하여 기판의 가장자리 부위를 과도 식각하는 것을 특징으로 하는 소자분리막 형성 방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0095629A KR100525300B1 (ko) | 2003-12-23 | 2003-12-23 | 소자분리막 형성 방법 |
US11/021,803 US6974756B2 (en) | 2003-12-23 | 2004-12-23 | Methods of forming shallow trench isolation |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0095629A KR100525300B1 (ko) | 2003-12-23 | 2003-12-23 | 소자분리막 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050064273A KR20050064273A (ko) | 2005-06-29 |
KR100525300B1 true KR100525300B1 (ko) | 2005-11-02 |
Family
ID=34675976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2003-0095629A Expired - Fee Related KR100525300B1 (ko) | 2003-12-23 | 2003-12-23 | 소자분리막 형성 방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6974756B2 (ko) |
KR (1) | KR100525300B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8691690B2 (en) | 2010-09-13 | 2014-04-08 | International Business Machines Corporation | Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects |
CN103199052A (zh) * | 2013-04-09 | 2013-07-10 | 上海华力微电子有限公司 | 浅沟槽隔离结构的制作方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR930010987B1 (ko) * | 1990-12-22 | 1993-11-18 | 삼성전자 주식회사 | 반도체 장치의 소자분리방법 |
KR960011861B1 (ko) * | 1993-06-10 | 1996-09-03 | 삼성전자 주식회사 | 반도체장치의 소자 분리 방법 |
US6291315B1 (en) * | 1996-07-11 | 2001-09-18 | Denso Corporation | Method for etching trench in manufacturing semiconductor devices |
US5783097A (en) * | 1997-06-09 | 1998-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Process to avoid dielectric damage at the flat edge of the water |
DE19805525C2 (de) * | 1998-02-11 | 2002-06-13 | Sez Semiconduct Equip Zubehoer | Verfahren zum Naßätzen von Halbleiterscheiben zum Erzeugen eines definierten Randbereichs durch Unterätzen |
US6100162A (en) * | 1999-05-14 | 2000-08-08 | Micron Technology, Inc. | Method of forming a circuitry isolation region within a semiconductive wafer |
US6764920B1 (en) * | 2002-04-19 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices |
US6777336B2 (en) * | 2002-04-29 | 2004-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming a shallow trench isolation structure |
US6858532B2 (en) * | 2002-12-10 | 2005-02-22 | International Business Machines Corporation | Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling |
-
2003
- 2003-12-23 KR KR10-2003-0095629A patent/KR100525300B1/ko not_active Expired - Fee Related
-
2004
- 2004-12-23 US US11/021,803 patent/US6974756B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20050064273A (ko) | 2005-06-29 |
US20050136614A1 (en) | 2005-06-23 |
US6974756B2 (en) | 2005-12-13 |
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