KR100516692B1 - Non-volatile ferroelectric memory device for controlling timing reference and method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device having a timing reference control function and a control method thereof, and more particularly, to amplify a sensing voltage level of cell data at a sensing sensing threshold voltage, and to apply a reference timing strobe based on a time axis. A technique for determining cell data is disclosed. The present invention stores read data applied from the cell array block in the read / write data register array unit through the read data bus unit in the read operation mode, and read data stored in the read / write data register array unit in the write operation mode. The input data applied from the read / write data buffer unit is stored in the cell array block through the write data bus unit, and the sensing voltage of the cell data may be determined based on the time axis to improve the sensing margin.

Description

Non-volatile ferroelectric memory device having a timing reference control function and a control method thereof Non-volatile ferroelectric memory device for controlling timing reference and method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile ferroelectric memory device having a timing reference control function and a control method thereof. In particular, the present invention relates to a method of converting a sensing voltage of cell data with respect to a time axis, and to determine cell data in a reference timing strobe section. Technology.

In general, the nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device due to its characteristic that data is preserved even when the power is turned off. have.

The FRAM is a memory device having a structure substantially similar to that of a DRAM, and uses a ferroelectric material as a capacitor material to utilize high residual polarization characteristic of the ferroelectric material. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

Description of the above-described FRAM has been disclosed in the application number 2002-85533 filed by the same inventor as the present invention. Therefore, a detailed description of the basic configuration of the FRAM and its operation will be omitted.

When sensing cell data in such a conventional nonvolatile ferroelectric memory, the level of the sensing reference voltage should be set to an appropriate level.

However, as the chip operating voltage of FeRAM became low, the level of the reference voltage for sensing the cell gradually decreased. When the sensing voltage level of the cell data is low, the voltage margin with the reference voltage becomes small, which makes it difficult to discriminate data. In addition, there is a problem that the sensing margin is reduced by the voltage level variation of the reference voltage itself.

Therefore, there is a problem that it is difficult to implement a high operating speed in the FeRAM chip of 1T1C (1transistor, 1capacitor) structure.

The present invention was created to solve the above problems, and has the following object.

First, the purpose of the present invention is to improve a structure of a bus for reading and writing data, and to implement a chip having improved data access time by storing data read and written through a register.

Second, the self-sensing voltage of the cell data is amplified in the reference timing section, and the voltage level of the data is determined based on the time axis, so that the margin of the sensing voltage is secured and the operating speed is increased when the low power supply voltage or fast access time chip is implemented. Its purpose is to improve it.

The nonvolatile ferroelectric memory device having the timing reference control function of the present invention for achieving the above object, each of the nonvolatile ferroelectric memory, and the reference timing strobe period when the voltage of the main bit line reaches the sensing detection threshold voltage A plurality of cell array blocks configured to amplify and output a sensing voltage of cell data sensed from the nonvolatile ferroelectric memory based on a specific time point; A read / write data register array for storing read data applied from a plurality of cell array blocks upon activation of the read lock control signal, and for storing read data or input data to be written to the plurality of cell array blocks upon activation of the write lock control signal. Wealth; A read data bus unit commonly connected to the plurality of cell array blocks and outputting read data to the read / write data register array unit; And a write data bus unit commonly connected to the plurality of cell array blocks and outputting read data or input data to the plurality of cell array blocks.

In addition, the present invention includes a nonvolatile ferroelectric memory, each of the cell data sensed from the nonvolatile ferroelectric memory on the basis of a specific time point in a reference timing strobe period in which the voltage of the main bit line reaches a sensing sensing threshold voltage. A plurality of upper cell array blocks and a plurality of lower cell array blocks for amplifying and outputting a sensing voltage; Read data applied from the plurality of upper cell array blocks or the plurality of lower cell array blocks when the read lock control signal is activated, and stored in the plurality of upper cell array blocks or the plurality of lower cell array blocks when the write lock control signal is activated. A read / write data register array section for storing read data or input data to be written; An upper read data bus unit commonly connected to the plurality of upper cell array blocks to output read data to the read / write data register array unit; A lower read data bus unit commonly connected to the plurality of lower cell array blocks to output read data to the read / write data register array unit; And a write data bus unit connected in common with the plurality of upper cell array blocks and the plurality of lower cell array blocks to output read data or input data to the plurality of upper cell array blocks or the plurality of lower cell array blocks. do.

The present invention also provides a plurality of cell array blocks each having a nonvolatile ferroelectric memory; And a read / write data register array section for storing read data applied from the plurality of cell array blocks and storing input data written to the plurality of cell array blocks, wherein the plurality of cell array blocks have voltages of the main bit lines. A sense for converting the self sensing voltage of the cell data sensed from the nonvolatile ferroelectric memory based on a specific time point in the reference timing strobe period reaching the sensing detection threshold voltage and amplifying the self sensing voltage converted at the specific time point. And an amplifier array unit.

The present invention also provides a plurality of cell array blocks each having a nonvolatile ferroelectric memory; And a read / write data register array section for storing read data applied from the plurality of cell array blocks via the read data bus section, and storing input data written to the plurality of cell array blocks via the write data bus section; The read / write data register array unit includes: a read bus pull-up unit which pulls up the read data bus unit in an initial state according to the bus pull-up control signal; A read bus switch unit for selectively outputting read data in accordance with a state of the read lock control signal; A data input switch section for selectively outputting input data applied from the data buffer bus section in accordance with the state of the write lock control signal; A data latch unit for storing read data and input data; A write bus switch unit for outputting read data or input data stored in the data latch unit according to the write enable signal; And a data output switch unit configured to output read data stored in the data latch unit to the data buffer bus unit according to the output enable signal.

The present invention also provides a level sensing unit for amplifying a sensing voltage level of cell data high of a main bit line when the sensing voltage of the main bit line is less than or equal to a predetermined threshold set as a logic threshold voltage when enabling the sensing enable signal. ; A sensing buffer unit configured to buffer an output voltage of the level sensing unit based on a logic threshold voltage; And a sensing output unit configured to determine a voltage level of read data read from the nonvolatile ferroelectric memory according to an output voltage of the sensing buffer unit when the sensing output enable signal is enabled.

In addition, the nonvolatile ferroelectric memory control method having the timing reference control function of the present invention for achieving the above object is provided to the plurality of cell array blocks through a plurality of cell array blocks, a read data bus unit and a write data bus unit. A nonvolatile ferroelectric memory control method having a timing reference control function having a read / write data register array unit for storing read / write data, the method comprising: adjusting a voltage level of cell data applied from a main bit line of a plurality of cell array blocks; Sensing; Amplifying the voltage level of the cell data and outputting an amplified voltage to the read data bus unit when the voltage level of the cell data reaches a sensing sensing threshold voltage or less; And sensing a voltage level of an amplification voltage on a predetermined time axis during the reference timing strobe period, and storing valid cell data values according to the sensed level.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a block diagram of a nonvolatile ferroelectric memory device having a timing reference control function according to a first embodiment of the present invention.

The present invention provides a read / write data buffer unit 100, a data buffer bus unit 200, a read / write data register array unit 300, a read data bus unit 400, and a plurality of cell array blocks ( 500 and the write data bus unit 600.

The read / write data buffer unit 100 is connected to the read / write data register array unit 300 through the data buffer bus unit 200. The plurality of cell array blocks 500 share the read data bus unit 400 and the write data bus unit 600. The read data bus unit 400 and the write data bus unit 600 are connected to the read / write data register array unit 300.

In the present invention having such a configuration, the data read in the cell array block 500 is stored in the read / write data register array unit 300 through the read data bus unit 400 in the read operation mode. The read data stored in the read / write data register array unit 300 is output to the read / write data buffer unit 100 through the data buffer bus unit 200.

On the other hand, in the write operation mode, input data input through the read / write data buffer unit 100 is stored in the read / write data register array unit 300 through the data buffer bus unit 200. Input data or read data stored in the read / write data register array unit 300 is written to the cell array block 500 through the write data bus unit 600.

2 is a block diagram of a nonvolatile ferroelectric memory device having a timing reference control function according to a second embodiment of the present invention.

According to the present invention, the read / write data buffer unit 100, the data buffer bus unit 200, the read / write data register array unit 300, the upper read data bus unit 400, and the lower read data bus unit 700, a plurality of upper cell array blocks 500, a plurality of lower cell array blocks 502, and a write data bus unit 600.

Here, the data bus connected to the upper cell array block 500 of FIG. 2 is the upper read data bus unit 400, and the data bus connected to the lower cell array block 502 is the lower read data bus unit 700.

The read / write data buffer unit 100 is connected to the read / write data register array unit 300 through the data buffer bus unit 200. The plurality of upper cell array blocks 500 share the upper read data bus unit 400 and the write data bus unit 600. The plurality of lower cell array blocks 502 share the write data bus unit 600 and the lower read data bus unit 700. In addition, the upper read data bus unit 400, the lower read data bus unit 700, and the write data bus unit 600 are connected to the read / write data register array unit 300.

According to the exemplary embodiment of the present invention, in the read operation mode, the read data output from the upper cell array block 500 or the lower cell array block 502 is stored in the upper read data bus unit 400 or the lower read data bus unit 700. The read / write data register array unit 300 is stored in the read / write data register array unit 300. The read data stored in the read / write data register array unit 300 is output to the read / write data buffer unit 100 through the data buffer bus unit 200.

In this case, only one of the upper read data bus unit 400 and the lower read data bus unit 700 operates selectively. That is, the operation path of the lower read data bus unit 700 is blocked when the upper read data bus unit 400 is operated, and the operation path of the upper read data bus unit 400 is operated when the lower read data bus unit 700 is operated. Is blocked.

On the other hand, in the write operation mode, input data input through the read / write data buffer unit 100 is stored in the read / write data register array unit 300 through the data buffer bus unit 200. The input data stored in the read / write data register array unit 300 is written to the upper cell array block 500 or the lower cell array block 502 through the write data bus unit 600. In this case, read data stored in the read / write data register array unit 300 may be re-stored in the upper cell array block 500 or the lower cell array block 502.

3 is a detailed block diagram of the upper cell array block 500 and the lower cell array block 502 of the present invention.

Since the configurations of the upper cell array block 500 and the lower cell array block 502 are the same, the configuration of the cell array block 500 shown in FIG. 1 will be described as an embodiment of the present invention.

The cell array block 500 includes a sense amplifier array unit 510, a main bit line (MBL) pull up control unit 520, a plurality of sub cell arrays 530, and a write switch 540. .

Here, the sense amplifier array unit 510 is connected to the read data bus unit 400, and the write switch unit 540 is connected to the write data bus unit 600.

4 is a detailed circuit diagram of the MBL pull-up control unit 520 of FIG. 3.

The MBL pull-up control unit 520 includes a PMOS transistor P1 for pulling up the main bit line MBL upon precharging. The source terminal of the PMOS transistor P1 is connected to the supply voltage VCC (or VPP) applying terminal, the drain terminal is connected to the main bit line MBL, and the main bit line pull-up control signal MBLPUC is applied through the gate terminal.

FIG. 5 is a detailed circuit diagram illustrating the light switch unit 540 of FIG. 3.

The write switch unit 540 includes an NMOS transistor N1 and a PMOS transistor P2. The NMOS transistor N1 is connected between the main bit line MBL and the write data bus unit 600 to receive the write switch control signal WSN through the gate terminal. In addition, the PMOS transistor P2 is connected between the main bit line MBL and the write data bus unit 600 to receive the write switch control signal WSP through the gate terminal.

The light switch unit 540 having such a configuration is used only during the write operation, and maintains the off state during the read operation. In the read operation, the amplified data of the sense amplifier array unit 510 is output to the read data bus unit 400.

FIG. 6 is a detailed circuit diagram of the subcell array 530 of FIG. 3.

Each main bit line MBL of the sub cell array 530 is selectively connected to one sub bit line SBL among the plurality of sub bit lines SBL. That is, when the sub bit line selection signal SBSW1 is activated, the NMOS transistor N6 is turned on to activate one sub bit line SBL. In addition, a plurality of cells C are connected to one sub bit line SBL.

The sub bit line SBL is pulled down to the ground level according to the turn-on of the NMOS transistor N4 when the sub bit line pull-down signal SBPD is activated. The sub bit line pull-up signal SBPU is a signal for controlling the power supplied to the sub bit line SBL. That is, at a low voltage, a voltage higher than the power supply voltage VCC is generated and supplied to the sub bit line SBL.

The sub bit line selection signal SBSW2 controls the connection between the sub bit line pull-up signal SBPU applying terminal and the sub bit line SBL according to the switching of the NMOS transistor N5.

In addition, the NMOS transistor N3 is connected between the NMOS transistor N2 and the main bit line MBL, and the gate terminal is connected to the sub bit line SBL. The NMOS transistor N2 is connected between the ground voltage terminal and the NMOS transistor N3, and the main bit line pull-down signal MBPD is applied through the gate to adjust the sensing voltage of the main bit line MBL.

7 is a detailed block diagram illustrating the sense amplifier array unit 510 of FIG. 3.

The sense amplifier array unit 510 includes a level sensing unit 511, a sensing buffer unit 512, and a sensing output unit 513.

Here, the level sensing unit 511 includes PMOS transistors P3 and P4 and NMOS transistors N7 and N8. The PMOS transistor P3 is connected between the supply voltage VCC supply terminal and the main bit line MBL so that the gate terminal is connected to the node SL. The PMOS transistor P4 is connected between the supply voltage VCC supply terminal and the node SL to apply a ground voltage to the gate terminal.

In addition, the NMOS transistor N7 is connected between the node SL and the NMOS transistor N8 so that the gate terminal is connected to the main bit line MBL. The NMOS transistor N8 is connected between the NMOS transistor N7 and the ground voltage terminal, and a sensing enable signal S_EN is applied to the gate terminal.

The level sensing unit 512 includes inverters IV1 and IV2 for buffering the output signal of the level sensing unit 511. The inverters IN1 and IV2 sense and buffer the output voltage of the node SL based on the logic Vt (threshold voltage) value.

The sensing output unit 513 includes NMOS transistors N9 and N10. The NMOS transistor N9 is connected between the read data bus unit 400 and the NMOS transistor N10 so that a gate terminal thereof is connected to the node SLO. The NMOS transistor N10 is connected between the NMOS transistor N9 and the ground voltage terminal, and the sensing output enable signal SOUT_EN is applied to the gate terminal.

Referring to the operation of the sense amplifier array unit 510 of the present invention having such a configuration as follows.

First, in the normal mode, the NMOS transistor N8 of the level sensing unit 511 maintains the off state. When the sensing enable signal S_EN is enabled in the read operation mode, the NMOS transistor N8 is turned on to apply a ground voltage to the node SL. Here, the gate terminal of the NMOS transistor N7 is connected to the main bit line MBL, and the amount of current flowing through the NMOS transistor N7 is controlled by the voltage of the main bit line MBL.

The amount of current flowing through the PMOS transistor P3 is determined by the voltage of the node SL. Therefore, when the node SL is at the ground level, the PMOS transistor P3 is turned on to supply the power supply voltage VCC to the main bit line MBL. At this time, the PMOS transistor P4 is always turned on and serves as a load by supplying a constant current to the node SL.

If the main bit line MBL is at the power supply voltage VCC level, the voltage of the node SL indicates a low state. On the other hand, when the main bit line MBL is at the ground level, the voltage of the node SL indicates a high state.

In other words, when the main bit line MBL is at a high level, the voltage of the node SL becomes low, resulting in a large current supply capability of the PMOS transistor P3. When the voltage of the main bit line MBL gradually decreases, the voltage of the node SL gradually rises, so that the current supply capability of the PMOS transistor P3 decreases. Therefore, the smaller the voltage of the main bit line MBL becomes, the faster the voltage drop rate of the main bit line MBL becomes.

For this reason, the voltage drop rate of the main bit line MBL is faster in the case of data "high" in the cell data of the memory cell than in the data "low". Therefore, when comparing the voltage rising rate at the node SL, the voltage rising rate at the cell data "high" becomes larger than the voltage rising rate at the cell data "low".

Afterwards, the inverters IV1 and IV2 buffer the output voltage of the node SL based on the logic threshold voltage Vt. As a result, the voltage level difference between the cell data “high” and “low” may be further amplified at the threshold value of the logic threshold voltage Vt to which the reference timing strobe is applied based on the time axis.

In this case, the margin of the sensing voltage level may be adjusted by adjusting the logic threshold voltages Vt of the inverters IV1 and IV2.

The NMOS transistor N10 remains off in normal operation mode. In the Lido operation mode, the sensing output enable signal SOUT_EN is enabled and the NMOS transistor N10 is turned on. Therefore, the voltage level of the read data bus unit 400 is determined according to the voltage level state of the node SLO.

That is, the read data bus unit 400 maintains the precharge state at a high level by the read bus pull-up unit described later, and it is determined whether or not the pull-down is determined by the voltage level of the node SLO. If the voltage level of the node SLO is high, the read data bus unit 400 is pulled down to a low level. On the other hand, when the voltage level of the node SLO is low, the read data bus unit 400 maintains the high level.

8 is an operation timing diagram related to the sense amplifier array unit 510 of the present invention.

First, the T0 section is a section in which the word line WL and the plate line PL are inactive and precharge the main bit line MBL and the read data bus unit 400 to a high level. Here, the sub bit lines SBL and the node SL are precharged to a low level. The sensing enable signal S_EN and the sensing output enable signal SOUT_EN are both disabled.

Thereafter, the word line WL and the plate line PL are activated to a high level in the T1 section. At the same time, data "high" or data "low" of the cell data is applied to the sub bit line SBL and the main bit line MBL.

In addition, the sensing enable signal S_EN and the sensing output enable signal SOUT_EN, which are control signals of the sense amplifier, are activated to a high level. Accordingly, the sense amplifier array unit 510 performs data amplification and sensing operations. At this time, the voltage level of the main bit line MBL is reduced until the sensing sense threshold voltage level is reached.

Next, in the T2 period, the voltage level of the cell data "high" first reaches the sensing sensing threshold voltage. That is, when the cell data is "high", the voltage of the node SL reaches the logic threshold voltage Vt level of the inverter INV1 first. Therefore, the voltage level of the node SLO transitions high to output the low level to the read data bus unit 400 first. Here, when the voltage level of the node SL increases, the voltage level of the PMOS transistor P3 drops rapidly from the point where the driving current of the PMOS transistor P3 decreases.

Further, in the T2 period, the voltage level of the cell data "low" does not reach the level of the sensing detection threshold voltage.

Therefore, the time point at which the cell data "high" and the cell data "low" respectively reach the sensing sensing threshold voltage level has a time difference during the T2 period with respect to the time axis. As a result, the validity of the cell data can be determined by applying the reference timing strobe during the T2 period to distinguish the cell data "high" or the cell data "low". The signal for determining the application timing of the reference timing strobe is the read lock control signal R_LOCK of the read / write data register array unit 300 described later.

That is, when the voltage level of the read data bus unit 400 is low in the T2 section, which is a reference timing strobe section, the cell data indicates “high”. On the contrary, when the voltage level of the read data bus unit 400 is high in the T2 period, the cell data indicates “low”.

Subsequently, when the cell data is "low" in the T3 period, the voltage level of the node SL reaches the voltage level of the logic threshold voltage Vt. In the T3 section, the voltage levels of the node SL and the node SLO are all enabled at a high level regardless of the voltage level of the cell data "high" or the cell data "low". Therefore, all of the voltage levels of the read data bus unit 400 are disabled to the low level.

FIG. 9 shows a detailed configuration of the read / write data register array unit 300 of the present invention shown in FIG.

The read / write data register array unit 300 includes a read bus pull-up unit 310, a read bus switch unit 320, a data latch unit 330, a data input switch unit 340, and a write bus switch unit. And a data output switch unit 360.

Here, the read bus pull-up unit 310 pulls up the read data bus unit 400 in an initial state according to the bus pull-up control signal BUSPU. The read bus switch unit 320 outputs data applied from the read data bus unit 400 to the data latch unit 330 according to the read lock control signal R_LOCK.

The data latch unit 330 stores read data applied from the read bus switch unit 320 and input data applied from the data input switch unit 340. The data input switch unit 340 outputs input data applied from the data buffer bus unit 200 to the data latch unit 330 according to the write lock control signal W_LOCK.

The write bus switch unit 350 outputs data stored in the data latch unit 330 to the write data bus unit 600 according to the write enable signal W_EN. The data output switch unit 360 outputs data stored in the data latch unit 330 to the data buffer bus unit 200 according to the output enable signal OUT_EN.

FIG. 10 is a detailed circuit diagram of the read / write data register array unit 300 of FIG. 9.

First, the read bus pull-up unit 310 includes a PMOS transistor P5 connected between a power supply voltage applying terminal and a read data bus unit 400 to which a bus pull-up control signal BUSPU is applied through a gate terminal.

The reed bus switch unit 320 includes the transfer gates T1 and T2 and the inverter IV3. Inverter IV3 inverts the read lock control signal R_LOCK. The transfer gate T1 selectively outputs read data applied from the read data bus unit 400 according to the read lock control signal R_LOCK applied through the NMOS gate and the inverted read lock control signal R_LOCK applied through the PMOS gate. The transfer gate T2 selectively outputs the output signal of the inverter IV5 according to the read lock control signal R_LOCK applied through the PMOS gate and the inverted read lock control signal R_LOCK applied through the NMOS gate.

The data latch unit 330 includes inverters IV4 and IV5 configured as latch circuits.

The data input switch unit 340 includes inverters IV6 and transfer gates T3 and T4. Inverter IV6 inverts the write lock control signal W_LOCK.

The transfer gate T3 selectively outputs the output signal of the inverter IV4 according to the write lock control signal W_LOCK applied through the PMOS gate and the inverted write lock control signal W_LOCK applied through the NMOS gate. The transfer gate T4 selectively selects the output signal of the data buffer bus unit 200 to the data latch unit 330 according to the write lock control signal W_LOCK applied through the NMOS gate and the inverted write lock control signal W_LOCK applied through the PMOS gate. Will print

The write bus switch unit 350 includes inverters IV7 to IV9 and a transmission gate T5. Inverters IV7 and IV8 delay the output signal of transfer gate T3. Inverter IV9 inverts the write enable signal W_EN. The transfer gate T5 selectively outputs the output signal of the inverter IV8 to the write data bus unit 600 according to the write enable signal W_EN applied through the NMOS gate and the inverted write enable signal W_EN applied through the PMOS gate.

The data output switch unit 360 includes inverters IV10 to IV12 and a transfer gate T6. Inverters IV10 and IV11 delay the output signal of transfer gate T3. Inverter IV12 inverts the output enable signal OUT_EN. The transfer gate T6 selectively outputs the output signal of the inverter IV11 to the data buffer bus unit 200 according to the output enable signal OUT_EN applied through the NMOS gate and the inverted output enable signal OUT_EN applied through the PMOS gate.

11 is an operation timing diagram of the read / write data register array unit 300 of the present invention.

First, when the read lock control signal R_LOCK is enabled in the T1 section, the cell sensing data applied from the read data bus unit 400 is stored in the data latch unit 330. That is, in the period where the read lock control signal R_LOCK is high, read data is continuously stored in the data latch unit 330.

Subsequently, when the read lock control signal R_LOCK transitions low in the T2 period, the read data is no longer input to the data latch unit 330. Therefore, when the read lock control signal R_LOCK is disabled, data previously stored in the data latch unit 330 can be continuously maintained when the reference timing strobe is applied.

Next, in the T3 section, since the voltage level of the data "high" or the data "low" is all low, the read data can no longer be stored in the data latch 330. As a result, the data input at the time of applying the reference timing strobe during the data valid period of T2 is finally stored in the data latch unit 330.

FIG. 12 shows a detailed configuration of the read / write data register array unit 300 of the present invention shown in FIG.

The read / write data register array unit 300 includes an upper lead bus pull-up unit 311, a lower lead bus pull-up unit 312, an upper lead bus switch unit 321, a lower lead bus switch unit 322, And a data latch section 331, a data input switch section 341, a write bus switch section 351, and a data output switch section 361.

Here, the upper read bus pull-up unit 311 pulls up the upper read data bus unit 400 in an initial state according to the bus pull-up control signal BUSPU. The upper read bus switch unit 321 outputs read data applied from the upper read data bus unit 400 to the data latch unit 331 according to the upper read lock control signal R_LOCK_T.

In addition, the lower read bus pull-up unit 312 pulls up the lower read data bus unit 700 in an initial state according to the bus pull-up control signal BUSPU. The lower read bus switch unit 322 outputs read data applied from the lower read data bus unit 700 to the data latch unit 331 according to the lower read lock control signal R_LOCK_B.

The data latch unit 331 stores the read data applied from the upper reed bus switch unit 321 and the lower reed bus switch unit 322 and the input data applied from the data input switch unit 341. The data input switch unit 341 outputs read data applied from the data buffer bus unit 200 to the data latch unit 331 according to the write lock control signal W_LOCK. At this time, the write lock control signal W_LOCK is enabled when data is restored or in the write operation mode.

The write bus switch unit 351 outputs the data stored in the data latch unit 331 to the write data bus unit 600 according to the write enable signal W_EN. The data output switch unit 361 outputs the data stored in the data latch unit 331 to the data buffer bus unit 200 according to the output enable signal OUT_EN.

FIG. 13 is a detailed circuit diagram of the read / write data register array unit 300 of FIG. 12.

First, the upper read bus pull-up unit 311 includes a PMOS transistor P6 connected between a power supply voltage applying terminal and the upper read data bus unit 400 to which a bus pull-up control signal BUSPU is applied through a gate terminal.

The lower read bus pull-up unit 312 includes a PMOS transistor P7 connected between the power supply voltage applying terminal and the lower read data bus unit 700 to which the bus pull-up control signal BUSPU is applied through the gate terminal.

The upper reed bus switch unit 321 includes transfer gates T7 and T8 and an inverter IV13. Inverter IV13 inverts the upper read lock control signal R_LOCK_T. The transfer gate T7 selectively outputs read data applied from the upper read data bus unit 400 according to the upper read lock control signal R_LOCK_T applied through the NMOS gate and the inverted upper read lock control signal R_LOCK_T applied through the PMOS gate. do.

The transfer gate T8 selectively outputs the output signal of the transfer gate T9 according to the upper read lock control signal R_LOCK_T applied through the PMOS gate and the inverted upper read lock control signal R_LOCK_T applied through the NMOS gate.

In addition, the lower reed bus switch unit 322 includes transmission gates T9 and T10 and an inverter IV14. Inverter IV14 inverts the lower read lock control signal R_LOCK_B. The transfer gate T9 selectively outputs read data applied from the lower read data bus unit 700 according to the lower read lock control signal R_LOCK_B applied through the NMOS gate and the inverted lower read lock control signal R_LOCK_B applied through the PMOS gate. do.

The transfer gate T10 selectively outputs the output signal of the inverter IV16 according to the lower read lock control signal R_LOCK_B applied through the PMOS gate and the inverted lower read lock control signal R_LOCK_B applied through the NMOS gate.

The data latch unit 331 includes inverters IV15 and IV16 constituted by latch circuits.

The data input switch section 341 includes inverters IV17 and transfer gates T11 and T12. Inverter IV17 inverts the write lock control signal W_LOCK.

The transfer gate T11 selectively outputs the output signal of the inverter IV15 according to the write lock control signal W_LOCK applied through the PMOS gate and the inverted write lock control signal W_LOCK applied through the NMOS gate. The transfer gate T12 selectively selects an output signal of the data buffer bus unit 200 to the data latch unit 331 according to the write lock control signal W_LOCK applied through the NMOS gate and the inverted write lock control signal W_LOCK applied through the PMOS gate. Will print

The write bus switch unit 351 includes inverters IV18 to IV20 and a transmission gate T13. Inverters IV18 and IV19 delay the output signal of transfer gate T11. Inverter IV20 inverts the write enable signal W_EN. The transfer gate T13 selectively outputs the output signal of the inverter IV19 to the write data bus unit 600 according to the write enable signal W_EN applied through the NMOS gate and the inverted write enable signal W_EN applied through the PMOS gate.

The data output switch unit 361 includes inverters IV21 to IV23 and a transfer gate T14. Inverters IV21 and IV22 delay the output signal of transfer gate T11. Inverter IV23 inverts the output enable signal OUT_EN. The transfer gate T14 selectively outputs the output signal of the inverter IV22 to the data buffer bus unit 200 according to the output enable signal OUT_EN applied through the NMOS gate and the inverted output enable signal OUT_EN applied through the PMOS gate.

14 is an operation timing diagram when the upper read data bus unit 400 is selected in the read / write data register array unit 300 of the present invention.

First, when the upper read lock control signal R_LOCK_T is enabled in the T1 section, the cell sensing data applied from the upper read data bus unit 400 is stored in the data latch unit 331. That is, in the period where the upper read lock control signal R_LOCK_T is high, read data is continuously stored in the data latch unit 331. At this time, the lower read lock control signal R_LOCK_B is kept low.

Thereafter, when the upper read lock control signal R_LOCK_T transitions low in the T2 section, read data is no longer input to the data latch unit 331. Therefore, at the time when the upper read lock control signal R_LOCK_T is disabled, data previously stored in the data latch unit 331 can be continuously maintained when the reference timing strobe is applied.

Next, in the T3 section, since the voltage level of the data "high" or the data "low" is all low, the read data can no longer be stored in the data latch 331. As a result, the data input at the application timing of the reference timing strobe during the data valid period of T2 is finally stored in the data latch unit 331.

15 is an operation timing diagram when the lower read data bus unit 700 is selected in the read / write data register array unit 300 of the present invention.

First, when the lower read lock control signal R_LOCK_B is enabled in the T1 section, the cell sensing data applied from the lower read data bus unit 700 is stored in the data latch unit 331. That is, in the period where the lower read lock control signal R_LOCK_B is high, read data continues to be stored in the data latch unit 331. At this time, the upper read lock control signal R_LOCK_T is kept low.

Subsequently, when the lower read lock control signal R_LOCK_B transitions low in the period T2, read data is no longer input to the data latch unit 331. Therefore, at the time when the lower read lock control signal R_LOCK_B is disabled, data previously stored in the data latch unit 331 can be continuously maintained when the reference timing strobe is applied.

Next, in the T3 section, since the voltage level of the data "high" or the data "low" is all low, the read data can no longer be stored in the data latch 331. As a result, the data input at the application timing of the reference timing strobe during the data valid period of T2 is finally stored in the data latch unit 331.

16 is a timing diagram of an operation in the write mode of the nonvolatile ferroelectric memory control method having the timing reference control function according to the present invention.

First, when the address changes in the t0 section and the write enable signal / WE is disabled low, the write mode is activated. The main bit line pulldown signal MBPD is enabled high when entering the t1 section. The main bit line pull-up control signal MBLPUC and the bus pull-up control signal BUSPU are disabled low, and the main bit line MBL is precharged high.

At this time, before the word line WL and the plate line PL are activated, the voltage level of the main bit line MBL and the read data bus unit 400 is pulled up in the period t0 and t2.

Thereafter, the word line WL is enabled upon entering the t2 section, the sub bit line pull-down signal SBPD is disabled low, and the storage node of the cell is initialized to the ground level. The read lock control signal R_LOCK and the main bit line pull-up control signal MBLPUC are enabled high. At this time, the word line is activated before the plate line PL in the period t2. Accordingly, the sensing margin can be improved by stabilizing the state of the storage node of the cell during the initial operation.

Next, upon entering the t3 section, which is a data sensing section, the plate line PL is enabled at the pumping voltage VPP level, and cell data is applied to the main bit line MBL. In addition, the bus pull-up control signal BUSPUC is enabled high to stop the pull-up operation of the upper read data bus unit 400.

Here, when the read lock control signal R_LOCK is disabled when the t4 period is entered, the amplified data of the sense amplifier array unit 510 is stored in the data latch unit 331 when the reference timing strobe is applied.

Subsequently, upon entering the t5 section, the voltage level of the plate line PL is disabled low, and the sub bit line selection signal SBSW2 is enabled to the pumping voltage VPP level. Then, the sub bit line pull-down signal SBPD is enabled high so that the voltage level of the sub bit line SBL becomes the ground level. In addition, the main bit line pull-down signal MBPD is disabled low, thereby enabling the main bit line MBL high.

Next, upon entering the t6 section, the voltage level of the word line WL is raised to write the cell data "high". Then, the sub bit line pull-up signal SBPU is enabled high, the voltage level of the sub bit line selection signal SBSW2 rises, and the voltage level of the sub bit line SBL rises to the pumping voltage VPP level. Also, the sub bit line pulldown signal SBPD is disabled low.

At this time, when the write lock control signal W_LOCK is enabled high, input data input from the data buffer bus unit 200 is stored in the data latch unit 331. The write bus switch unit 351 outputs the data stored in the data latch unit 311 to the write data bus unit 600 when the write enable signal W_EN is enabled.

In addition, when the write switch control signal WSN is enabled high, the data of the write data bus unit 600 is output to the main bit line MBL.

Subsequently, if the write enable signal / WE and the plate line PL are enabled when entering the t7 section, the cell data “0” is re-stored during the data validity period. In addition, the write lock control signal W_LOCK is disabled so that the input data inputted to the data input switch 341 is stored in the data latch unit 331.

At this time, the voltage level of the main bit line MBL is disabled low. Then, the voltage level of the sub bit line selection signal SBSW1 rises to the pumping voltage VPP level, the sub bit line selection signal SBSW2 is disabled low, and the data of the main bit line MBL is output to the sub bit line SBL.

Here, when the data of the cell is "high", the voltage of the sub bit line SBL becomes high when sensing. Thus, the current of the switching transistor of the cell C becomes large, so that the voltage level of the main bit line MBL induced in the cell data "low" is lowered.

On the contrary, when the data of the cell is " low ", the voltage of the sub bit line SBL at the read becomes low. Therefore, the current of the switching transistor of the cell C becomes small, so that the voltage level of the main bit line MBL induced in the cell data "high" becomes high.

Therefore, while the sub bit line selection signal SBSW1 is enabled to write new data, the data stored in the read / write data register array unit 300 is applied to the sub bit line SBL and the main bit line MBL, respectively. At this time, when the write data is "0", the data low level is stored in the memory cell.

Next, upon entering the t8 section, the word line WL is disabled before the plate line PL.

Subsequently, upon entering the t9 section, the voltage level of the plate line PL, the sub bit line selection signal SBSW1 and the sub bit line pull-up signal SBPU are disabled low. The sub bit line pull-down signal SBPD and the main bit line are enabled high.

At this time, the write switch control signal WSN is disabled to block the connection between the main bit line MBL and the write data bus unit 600. Then, the write enable signal W_EN is disabled low so that data is no longer input to the write data bus unit 600.

17 is a timing diagram of an operation in the read mode of the nonvolatile ferroelectric memory control method having the timing reference control function according to the present invention.

First, in the read mode, the write enable signal / WE maintains the power supply voltage level. The data output valid section is maintained after the t6 section.

At this time, the write lock control signal W_LOCK maintains a low level. Therefore, instead of writing input data input from the outside through the data buffer bus unit 200 to the cell, read data stored in the data latch unit 330 is re-stored in the cell.

In addition, the output enable signal OUT_EN is enabled high in the period t4 so that the read data stored in the data latch unit 330 can be output through the data buffer bus unit 200 by the read lock control signal R_LOCK.

As described above, the present invention provides the following effects.

First, it improves the structure of the bus for reading and writing data, and improves data access time by storing data read and written through registers.

Second, since a separate reference voltage generation circuit is unnecessary by the self-reference sensing circuit, a margin of the sensing voltage can be secured at a low voltage and the operation speed can be improved.

1 is a first embodiment of a nonvolatile ferroelectric memory device having a timing reference control function according to the present invention;

2 is a second embodiment of a nonvolatile ferroelectric memory device having a timing reference control function according to the present invention;

3 is a detailed block diagram of a cell array block of the present invention.

4 is a detailed circuit diagram of the MBL pull-up control unit of FIG.

FIG. 5 is a detailed circuit diagram of the light switch unit of FIG. 3. FIG.

FIG. 6 is a detailed circuit diagram of the subcell array of FIG. 3. FIG.

FIG. 7 is a detailed circuit diagram of the sense amplifier array unit of FIG. 3. FIG.

8 is an operation timing diagram relating to the sense amplifier array unit of FIG. 7;

9 is a detailed block diagram of the read / write data register array unit according to the first embodiment of the present invention;

FIG. 10 is a detailed circuit diagram of the read / write data register array unit of FIG. 9; FIG.

FIG. 11 is an operation timing diagram relating to the read / write data register array unit of FIG. 9; FIG.

12 is a detailed block diagram of the read / write data register array unit according to the second embodiment of the present invention.

FIG. 13 is a detailed circuit diagram of the read / write data register array unit of FIG. 12; FIG.

14 and 15 are operation timing diagrams related to the read / write data register array unit of FIG.

16 is a timing diagram of operation in a write mode of a nonvolatile ferroelectric memory control method having a timing reference control function according to the present invention;

17 is a timing diagram of operation in a read mode of a nonvolatile ferroelectric memory control method having a timing reference control function according to the present invention;

Claims (38)

Each of the nonvolatile ferroelectric memories is provided, and amplifies the sensing voltage of the cell data sensed from the nonvolatile ferroelectric memory based on a specific time point in a reference timing strobe section in which the voltage of the main bit line reaches the sensing detection threshold voltage. A plurality of cell array blocks; A read / write for storing read data applied from the plurality of cell array blocks upon activation of a read lock control signal, and for storing the read data or input data to be written to the plurality of cell array blocks upon activation of a write lock control signal; A data register array unit; A read data bus unit commonly connected to the plurality of cell array blocks to output the read data to the read / write data register array unit; And And a write data bus unit connected in common with the plurality of cell array blocks and outputting the read data or input data to the plurality of cell array blocks. The method of claim 1, wherein each of the plurality of cell array blocks A sense amplifier array unit configured to amplify a voltage level of cell data at the sensing detection threshold voltage set by a logic threshold voltage based on the specific time point; A main bit line pull-up control unit which pulls up the main bit line according to a state of a main bit line pull-up control signal; A plurality of subcell arrays having the nonvolatile ferroelectric memory to store the read data or input data; And And a write switch unit for selectively connecting the main bit line and the write data bus unit according to a state of a write switch control signal. The method of claim 2, wherein the sense amplifier array unit A level sensing unit configured to amplify a sensing voltage level of cell data high of the main bit line when the sensing voltage of the main bit line is less than or equal to the threshold voltage when the sensing enable signal is enabled; A sensing buffer unit configured to buffer an output voltage of the level sensing unit based on the logic threshold voltage; And And a sensing output unit configured to determine a voltage level of the read data bus unit in accordance with an output voltage of the sensing buffer unit when the sensing output enable signal is enabled. The method of claim 3, wherein the level sensing unit A first driving device configured to output a ground voltage to a first node when the sensing enable signal is enabled; A second driving element controlling an amount of current applied to the first node by a voltage of the main bit line; A third driving element selectively supplying a power supply voltage according to the voltage level of the first node to control an amount of current supplied to the main bit line; And And a fourth driving device for supplying a constant current to the first node. The nonvolatile ferroelectric memory device having a timing reference control function. The method of claim 3, wherein the sensing buffer unit And a plurality of inverter chains for buffering the output voltage of the first node based on the logic threshold voltage. The method of claim 3, wherein the sensing output unit A fifth driving device configured to output a ground voltage to the read data bus unit when the sensing output enable signal is enabled; And And a sixth driving element selectively driven according to an output voltage of the sensing buffer unit to determine a voltage level of the read data bus unit. The data read / write data register array unit of claim 1, A read bus pull-up unit configured to pull up the read data bus unit in an initial state according to a bus pull-up control signal; A read bus switch unit for selectively outputting the read data applied from the read data bus unit according to an activation state of the read lock control signal; A data input switch unit for selectively outputting the input data applied from a data buffer bus unit according to an activation state of the write lock control signal; A data latch unit for storing the read data and the input data; A write bus switch unit configured to output the read data or input data stored in the data latch unit to the write data bus unit when a write enable signal is activated; And And a data output switch unit for outputting read data stored in the data latch unit to the data buffer bus unit when an output enable signal is activated. The method of claim 7, wherein the lead bus pull-up unit And a seventh driving device configured to pull up the read data bus unit to a power supply voltage in response to the bus pull-up control signal. The method of claim 7, wherein the reed bus switch unit A first transfer gate selectively outputting the read data when the read lock control signal is activated; And And a second transfer gate configured to selectively output the read data to the data latch section when the read lock control signal is inactivated. The method of claim 7, wherein the data input switch unit A third transmission gate selectively outputting the input data when the write lock control signal is activated; And And a fourth transfer gate configured to selectively output the input data to the data latch section when the write lock control signal is inactivated. The method of claim 7, wherein the data latch unit A nonvolatile ferroelectric memory device having a timing reference control function, wherein the output signals are inputted to respective input signals and have a first inverter and a second inverter connected in parallel. The method of claim 7, wherein the light bus switch unit A first delay unit connected to an inverter chain by delaying an output signal of the data latch unit for a predetermined time; And And a fifth transfer gate configured to selectively output an output signal of the first delay unit to the write data bus unit according to a state of the write enable signal. The method of claim 7, wherein the data output switch unit A second delay unit delaying an output signal of the data latch unit for a predetermined time and connected to an inverter chain; And And a sixth transfer gate configured to output an output signal of the second delay unit to the data buffer bus unit according to the output enable signal. Each of the nonvolatile ferroelectric memories is provided, and amplifies the sensing voltage of the cell data sensed from the nonvolatile ferroelectric memory based on a specific time point in a reference timing strobe section in which the voltage of the main bit line reaches the sensing detection threshold voltage. A plurality of upper cell array blocks and lower cell array blocks; Store read data applied from the plurality of upper cell array blocks or the plurality of lower cell array blocks when the read lock control signal is activated, and when the write lock control signal is activated, the plurality of upper cell array blocks or the plurality of lower cells. A read / write data register array unit for storing the read data or input data written to a cell array block; An upper read data bus unit connected in common with the plurality of upper cell array blocks to output the read data to the read / write data register array unit; A lower read data bus unit connected in common with the plurality of lower cell array blocks to output the read data to the read / write data register array unit; And A write data bus unit commonly connected to the plurality of upper cell array blocks and the plurality of lower cell array blocks and outputting the read data or the input data to the plurality of upper cell array blocks or the plurality of lower cell array blocks; Nonvolatile ferroelectric memory device having a timing reference control function characterized in that it comprises. The method of claim 14, Each of the plurality of upper cell array blocks and the plurality of lower cell array blocks A sense amplifier array unit configured to amplify a voltage level of cell data at the sensing detection threshold voltage set by a logic threshold voltage based on the specific time point; A main bit line pull-up control unit which pulls up the main bit line according to a state of a main bit line pull-up control signal; A plurality of subcell arrays having the nonvolatile ferroelectric memory; And And a write switch unit for selectively connecting the main bit line and the write data bus unit according to a state of a write switch control signal. The method of claim 15, wherein the sense amplifier array unit A level sensing unit configured to amplify a sensing voltage level of cell data high of the main bit line when the sensing voltage of the main bit line is less than or equal to the threshold voltage when the sensing enable signal is enabled; A sensing buffer unit configured to buffer an output voltage of the level sensing unit based on the logic threshold voltage; And And a sensing output unit configured to determine a voltage level of the upper read data bus unit or the lower read data bus unit according to an output voltage of the sensing buffer unit when the sensing output enable signal is enabled. Volatile ferroelectric memory device. The method of claim 16, wherein the level sensing unit A first driving device configured to output a ground voltage to a first node when the sensing enable signal is enabled; A second driving element controlling an amount of current applied to the first node by a voltage of the main bit line; A third driving element selectively supplying a power supply voltage according to the voltage level of the first node to control an amount of current supplied to the main bit line; And And a fourth driving device for supplying a constant current to the first node. The nonvolatile ferroelectric memory device having a timing reference control function. The method of claim 16, wherein the sensing buffer unit And a plurality of inverter chains for buffering the output voltage of the first node based on the logic threshold voltage. The method of claim 16, wherein the sensing output unit A fifth driving device configured to output a ground voltage to the read data bus unit when the sensing output enable signal is enabled; And And a sixth driving element selectively driven according to an output voltage of the sensing buffer unit to determine a voltage level of the upper read data bus unit or the lower read data bus unit. Device. 15. The memory device of claim 14, wherein the read / write data register array unit An upper read bus pull-up unit configured to pull up the upper read data bus unit in an initial state according to a bus pull-up control signal; A lower read bus pull-up unit configured to pull up the lower read data bus unit in an initial state according to the bus pull-up control signal; An upper read bus switch unit configured to selectively output the read data applied from the upper read data bus unit according to an activation state of an upper read lock control signal; A lower read bus switch unit configured to selectively output the read data applied from the lower read data bus unit according to an activation state of a lower read lock control signal; A data input switch unit for selectively outputting the input data applied from a data buffer bus unit according to an activation state of the write lock control signal; A data latch unit for storing the read data and the input data; A write bus switch unit configured to output the read data or input data stored in the data latch unit to the write data bus unit when a write enable signal is activated; And And a data output switch unit for outputting read data stored in the data latch unit to the data buffer bus unit when an output enable signal is activated. 21. The method of claim 20, wherein the upper lead bus pull-up portion And a seventh driving device configured to pull up the upper read data bus unit to a power supply voltage in response to the bus pull-up control signal. 21. The method of claim 20, wherein the lower lead bus pull-up portion And an eighth driving device configured to pull up the lower read data bus unit to a power supply voltage in response to the bus pull-up control signal. The method of claim 20, wherein the upper reed bus switch unit A first transfer gate selectively outputting the read data when the upper read lock control signal is activated; And And a second transfer gate selectively outputting the read data to the data latch unit when the upper read lock control signal is inactivated. The method of claim 20, wherein the lower reed bus switch unit A third transfer gate selectively outputting the read data when the lower read lock control signal is activated; And And a fourth transfer gate for selectively outputting the read data to the data latch unit when the lower read lock control signal is inactivated. The method of claim 20, wherein the data input switch unit A fifth transmission gate selectively outputting the input data when the write lock control signal is activated; And And a sixth transfer gate configured to selectively output the input data to the data latch unit when the write lock control signal is inactivated. 21. The method of claim 20, wherein the data latch unit A nonvolatile ferroelectric memory device having a timing reference control function, wherein the output signals are inputted to respective input signals and have a first inverter and a second inverter connected in parallel. The method of claim 20, wherein the light bus switch unit A first delay unit delaying an output signal of the data latch unit for a predetermined time and connected to an inverter chain; And And a seventh transfer gate configured to selectively output an output signal of the first delay unit to the write data bus unit in accordance with the state of the write enable signal. 21. The apparatus of claim 20, wherein the data output switch unit A second delay unit delaying an output signal of the data latch unit for a predetermined time and connected to an inverter chain; And And an eighth transfer gate configured to output an output signal of the second delay unit to the data buffer bus unit according to the output enable signal. The method of claim 20, The upper lead lock control signal and the lower lead lock control signal are And only one of the read lock control signals corresponding to the operation of the plurality of upper cell array blocks or the plurality of lower cell array blocks is enabled. A plurality of cell array blocks each having a nonvolatile ferroelectric memory; And A read / write data register array unit configured to store read data applied from the plurality of cell array blocks, and to store input data written to the plurality of cell array blocks, The plurality of cell array blocks The self-sensing voltage of the cell data sensed from the nonvolatile ferroelectric memory is converted based on a specific time point in the reference timing strobe period when the voltage of the main bit line reaches the sensing detection threshold voltage, and the self-sensing converted at the specific time point is converted. A nonvolatile ferroelectric memory device having a timing reference control function comprising a sense amplifier array unit for amplifying a voltage. The method of claim 30, A read data bus unit commonly connected to the plurality of cell array blocks to output the read data to the read / write data register array unit; And And a write data bus unit connected in common with the plurality of cell array blocks and outputting the read data or the input data to the plurality of cell array blocks. The method of claim 31, wherein the sense amplifier array unit A level sensing unit configured to amplify a sensing voltage level of cell data high of the main bit line when the sensing voltage of the main bit line is less than or equal to the threshold voltage when the sensing enable signal is enabled; A sensing buffer unit configured to buffer an output voltage of the level sensing unit based on the logic threshold voltage; And And a sensing output unit configured to determine a voltage level of the read data bus unit in accordance with an output voltage of the sensing buffer unit when the sensing output enable signal is enabled. 32. The memory device of claim 31, wherein the read / write data register array unit A read bus pull-up unit configured to pull up the read data bus unit in an initial state according to a bus pull-up control signal; A read bus switch unit for selectively outputting the read data applied from the read data bus unit according to an activation state of a read lock control signal; A data input switch unit for selectively outputting the input data applied from the data buffer bus unit according to the activation state of the write lock control signal; A data latch unit for storing the read data and the input data; A write bus switch unit configured to output the read data or input data stored in the data latch unit to the write data bus unit when a write enable signal is activated; And And a data output switch unit for outputting read data stored in the data latch unit to the data buffer bus unit when an output enable signal is activated. A plurality of cell array blocks each having a nonvolatile ferroelectric memory; And A read / write data register array unit configured to store read data applied from the plurality of cell array blocks through a read data bus unit, and to store input data written to the plurality of cell array blocks through a write data bus unit; The read / write data register array unit A read bus pull-up unit configured to pull up the read data bus unit in an initial state according to a bus pull-up control signal; A read bus switch unit for selectively outputting the read data according to a state of a read lock control signal; A data input switch section for selectively outputting the input data applied from the data buffer bus section according to the state of the write lock control signal; A data latch unit for storing the read data and the input data; A write bus switch unit configured to output the read data or input data stored in the data latch unit to the write data bus unit when a write enable signal is activated; And And a data output switch unit for outputting read data stored in the data latch unit to the data buffer bus unit when an output enable signal is activated. The method of claim 34, wherein each of the plurality of cell array blocks The self-sensing voltage of the cell data sensed from the nonvolatile ferroelectric memory is converted based on a specific time point in the reference timing strobe period when the voltage of the main bit line reaches the sensing detection threshold voltage, and the self-sensing converted at the specific time point is converted. A nonvolatile ferroelectric memory device having a timing reference control function comprising a sense amplifier array unit for amplifying a voltage. A level sensing unit configured to amplify the sensing voltage level of the cell data high of the main bit line when the sensing voltage of the main bit line is less than or equal to a predetermined threshold value set as a logic threshold voltage when the sensing enable signal is enabled; A sensing buffer unit configured to buffer an output voltage of the level sensing unit based on the logic threshold voltage; And And a sensing output unit configured to determine a voltage level of the read data read from the nonvolatile ferroelectric memory according to the output voltage of the sensing buffer unit when the sensing output enable signal is enabled. Memory device. A nonvolatile ferroelectric having a timing reference control function including a plurality of cell array blocks and a read / write data register array section for storing data read / write in the plurality of cell array blocks through a read data bus section and a write data bus section. In the memory control method, Sensing a voltage level of cell data applied from main bit lines of the plurality of cell array blocks; Amplifying the voltage level of the cell data and outputting an amplified voltage to the read data bus unit when the voltage level of the cell data reaches a sensing sensing threshold voltage or less; And And sensing a voltage level of the amplified voltage on a predetermined time axis during a reference timing strobe period, and storing a value of valid cell data according to the sensed level. Control method. The method of claim 37, And a timing reference control function for reaching the sensing detection threshold voltage at a predetermined time before the low data when the cell data is the high data.