KR100515008B1 - Method for fabricating complex semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a composite semiconductor device capable of simultaneously forming first and second contact holes provided in the capacitor region and the analog circuit region, respectively, in the manufacture of a composite semiconductor device having a capacitor and an analog circuit. As,

In the method of manufacturing a composite semiconductor device according to the present invention, in the method of manufacturing a composite semiconductor device including a capacitor and a transistor, an etching suppression film is laminated and selectively patterned on the entire surface of the substrate on which the upper electrode of the capacitor and the gate electrode of the transistor are formed. Forming an etch inhibiting film only on the upper electrode of the capacitor; laminating an interlayer insulating film on the entire surface of the substrate including the etch inhibiting film; and an upper electrode of the capacitor and a gate electrode of the transistor on the substrate; Forming an etch mask for forming a contact hole exposing a source / drain; and using the etch mask to etch the interlayer insulating layer to expose an etch suppression layer formed on the upper electrode of the capacitor. Performing an etching process; and, of the capacitor And etching the etch suppression layer on the upper electrode and the interlayer dielectric layer on the transistor to complete the contact hole to expose the upper electrode and the gate electrode and the source / drain of the transistor. It features.

Description

Method for fabricating composite semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a composite semiconductor device, and more particularly, to manufacturing a composite semiconductor device including a capacitor and an analog circuit, wherein the first and second contact holes are provided in the capacitor region and the analog circuit region, respectively. It relates to a method for manufacturing a composite semiconductor device that can be formed at the same time.

Capacitors used in analog circuits such as CMOS logic include PIP (Poly-Silicon / Insulator / Poly-Silicon) and MIM (Metal / Insulator / Metal). Among these, the PIP capacitors are widely used for noise prevention, frequency modulation, and the like in analog devices. The PIP capacitor is mainly composed of a bottom electrode, a dielectric film, and a top electrode, and metal wires are connected to the top of the bottom electrode and the top electrode.

On the other hand, recently, due to the high integration technology of semiconductor devices, a composite semiconductor device in which a PIP capacitor is integrated with an analog circuit has emerged. The structure of such a composite semiconductor device will be described with reference to the drawings. 1 is a structural cross-sectional view of a composite semiconductor device having a PIP capacitor and an analog circuit according to the prior art.

As shown in FIG. 1, a conventional composite semiconductor device includes a first polysilicon film 103a as a lower electrode, a dielectric film 104, and a second polysilicon film as an upper electrode on a semiconductor substrate 101. A PIP capacitor composed of 105 and an analog circuit composed of a gate electrode 103b and a source / drain junction (not shown) are formed, respectively.

In the PIP capacitor, a first spacer 107 is formed on sidewalls of the second polysilicon film 105 as the upper electrode and the dielectric 104 and a second sidewall is formed on the sidewall of the first polysilicon film 103a as the lower electrode. Spacers 106 are formed. The second spacer 106 is also formed on the sidewall of the gate electrode 103b of the analog circuit.

An etch stop layer 108 is stacked on the PIP capacitor and the entire analog circuit, and a predetermined portion of the etch stop layer 108 is etched to expose the upper electrode 105 of the capacitor. The second contact hole 110b through which the gate electrode 103b or the substrate 101 of the analog circuit is exposed is formed. Although not shown, metal wires are connected to the first and second contact holes 110a and 110b of the capacitor or the analog circuit.

Briefly looking at the manufacturing process of such a conventional composite semiconductor device as follows. 2A to 2E are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the prior art.

First, as shown in FIG. 2A, an insulating film, a first polysilicon film 103a, a dielectric film 104, and a second polysilicon film 105 are sequentially stacked on a semiconductor substrate. In this state, the second polysilicon layer 105 is selectively patterned using a photolithography and an etching process to form the upper electrode 105 of the capacitor, and the lower dielectric layer 104 is also patterned.

Then, as shown in FIG. 2B, the first polysilicon film 103a is patterned to form a lower electrode in the capacitor region and a gate electrode 103b in the analog circuit region. Next, although not shown in the figure, an LDD ion implantation process is performed in the analog circuit region to form a LDD (Light Doped Drain) region.

In this state, as shown in FIG. 2C, the first spacer 107 is formed on the sidewalls of the upper electrode 105 and the dielectric film 104 in the capacitor region. Next, second spacers 106 are formed on sidewalls of the lower electrode of the capacitor region and the gate electrode of the analog circuit region, respectively. Although not shown in the figure, a source / drain ion implantation process is performed in the analog circuit region to form a source / drain junction. Subsequently, a silicide layer may be formed on the upper electrode 105 and the gate electrode 103b by an optional process.

In this state, as shown in FIG. 2D, the etch stop layer 108 and the interlayer insulating layer 109 are sequentially stacked on the entire surface of the substrate including the PIP capacitor upper electrode 105 and the gate electrode 103b. . Subsequently, a photoresist (not shown) is coated on the interlayer insulating layer 109, and a photolithography process is performed to form a first photoresist layer pattern defining a first contact hole region of a capacitor region on the interlayer insulating layer 109. .

Thereafter, the interlayer insulating layer 109 is etched by a dry etching process using the first photoresist layer pattern to form the first contact hole 110a to expose the upper electrode 105 of the capacitor or the silicide layer of the upper electrode.

In the state where the first contact hole is formed, as shown in FIG. 2E, the first photoresist layer pattern is removed, and a photoresist layer (not shown) is applied on the entire surface of the substrate, and then a photographic process is performed to perform analog on the interlayer insulation layer. A second photosensitive film pattern defining a second contact hole region of the circuit region is formed.

Next, the interlayer insulating layer 109 is etched by a dry etching process using the second photoresist pattern to form a second contact hole 110b exposing a gate electrode or a source / drain junction of an analog region.

Subsequently, although not shown in the drawing, when the metal wires are stacked in the first and second contact holes 110a and 110b, the manufacturing process of the composite semiconductor device according to the prior art is completed.

In the conventional method for manufacturing a composite semiconductor device, a first contact hole forming step of exposing an upper electrode of a capacitor region and a second contact hole forming step of exposing a gate electrode or a source / drain junction of an analog circuit area are separately. Was performed.

The reason for this is that the height of the interlayer insulating layer stacked on the upper portion of each region is different according to the vertical height difference between the capacitor region and the analog circuit region. Therefore, when the first and second contact holes are formed simultaneously, The interlayer insulating film of the capacitor region is etched ahead of time by the step of the interlayer insulating film to expose the upper electrode of the capacitor region. In this case, the upper electrode of the exposed capacitor is inevitably damaged by the etching process until the second contact hole of the analog circuit region is completed. For this reason, the first contact hole forming process of the capacitor region and the second contact hole forming process of the analog circuit region are separately performed to protect the upper electrode of the capacitor region in which the interlayer insulating film having a relatively low height is stacked.

However, as the first and second contact hole forming processes are separately performed, the same process is performed since the capacitor and analog circuit regions are separated to perform the contact mask, contact manufacturing, and mask removal processes separately in each region. Since it is carried out at times, there was a problem that the number of manufacturing processes increases.

The present invention has been made to solve the above problems, in the manufacture of a composite semiconductor device having a capacitor and an analog circuit, a composite that can simultaneously form contact holes provided in the capacitor region and the analog circuit region, respectively It is an object to provide a method for manufacturing a semiconductor device.

In the manufacturing method of the composite semiconductor device of the present invention for achieving the above object, in the method of manufacturing a composite semiconductor device having a capacitor and a transistor, the etching suppression on the entire surface of the substrate on which the upper electrode of the capacitor and the gate electrode of the transistor are formed Stacking and selectively patterning a film to form an etch inhibiting film only on the upper electrode of the capacitor; laminating an interlayer insulating film on the entire surface of the substrate including the etch inhibiting film; and on the substrate, the upper electrode of the capacitor And forming an etch mask for forming a contact hole exposing the gate electrode and the source / drain of the transistor; and etching the interlayer insulating layer using the etch mask to form an etch mask formed on the upper electrode of the capacitor. To proceed with the first etching step of exposing the suppression film. And a second etching process of completing contact holes by etching both the etch inhibiting film on the upper electrode and the interlayer insulating film on the transistor to expose the upper electrode of the capacitor and the gate electrode and the source / drain of the transistor. Characterized in that it comprises a step.

Preferably, the etching inhibiting film can be laminated to a thickness of 200 to 400 kPa using a nitride film.

Preferably, the etching selectivity between the etch inhibiting film and the interlayer insulating film is about 1: 5 to about 10.

According to a feature of the present invention, by forming an etch inhibiting film having a relatively low etching rate compared to the interlayer insulating film on the upper electrode of the capacitor region to a predetermined thickness, the interlayer insulating film formed on the capacitor region and the analog circuit region with different steps. During etching, the upper portion of each region may be simultaneously exposed in time to simplify the process of forming a contact hole.

Hereinafter, a method of manufacturing a composite semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. 3A to 3E are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the present invention.

For reference, the present invention has a key feature in the process of forming a contact hole in the manufacturing process of the composite semiconductor device, and thus a detailed description of the manufacturing of the capacitor and the analog circuit, for example, the transistor, will be omitted.

First, as illustrated in FIG. 3A, a semiconductor substrate is defined as a capacitor region and an analog circuit region, and a PIP capacitor and an analog circuit are previously formed on each region through a series of semiconductor unit processes.

The PIP capacitor may include a dielectric film interposed between a second polysilicon film 305 serving as an upper electrode, a first polysilicon film 303a serving as a lower electrode, and the first and second polysilicon films. 304). In addition, a first spacer 307 is formed on the sidewall of the second polysilicon film 305 and the dielectric film, and a second spacer 306 is formed on the sidewall of the first polysilicon film 303a.

In the analog circuit, for example, a transistor includes a gate electrode 303b and a source / drain junction (not shown), and a second spacer 306 is formed on the sidewall of the gate electrode.

In this state, although not shown in the drawing, a silicide layer may be additionally formed on the second polysilicon layer 305 and on the gate electrode through a silicide process. Subsequently, an etch stop layer 308 is stacked on the entire surface of the substrate.

Subsequently, as illustrated in FIG. 3B, an etch inhibiting film 309 is stacked on the entire surface of the substrate including the second polysilicon film 305 and the gate electrode 303b. Nitride films may be used as the etch inhibiting film, and may be formed to a thickness of 200 to 400 kPa using a chemical vapor deposition process. The etching inhibiting layer is made of a material having a lower etching speed than the interlayer insulating layer. For example, when the nitride film is used as the etching inhibiting film, the etching selectivity with respect to the interlayer insulating film of oxide film material may be about 1: 5 to about 10.

Then, a photoresist film is applied on the etch inhibiting film, and then a photoresist pattern is formed having a region corresponding to the upper electrode of the PIP capacitor using a photographic process. Subsequently, the exposed portion of the etch inhibiting layer is etched and removed using the photoresist pattern so that the etch inhibitor 309 remains only on the upper electrode.

Then, as illustrated in FIG. 3C, an interlayer insulating film 310, for example, an oxide film is laminated on the entire surface of the substrate. At this time, due to the step difference between the capacitor region and the analog circuit region, the stack thickness of the interlayer insulating film varies depending on the region.

In this state, the photoresist film is coated on the interlayer insulating film, and then the photoresist pattern 311 is formed to expose the interlayer insulating film in the region where the contact hole is to be formed by using a photolithography process. Subsequently, a contact hole forming process is performed by etching the interlayer insulating layer using the photoresist pattern as an etching mask. In this case, the contact hole forming process may be classified into a first etching process and a second etching process, and the first and second etching processes use a dry etching process such as reactive ion etching. The exposed portions of the contact holes are the upper electrode 305 of the PIP capacitor, the gate electrode 303b of the transistor, and the source / drain junction region.

On the other hand, as described above, due to the step difference between the PIP capacitor region and the analog circuit region, the interlayer insulating films stacked on the respective regions have different heights. Accordingly, the etch suppression layer 309, which is formed on the upper electrode, is first exposed by etching the interlayer insulating layer 310 on the PIP capacitor upper electrode before exposing the gate electrode and the source / drain of the transistor. do. The process of exposing the etch inhibiting film on the PIP capacitor is defined as a first etching process.

In the state where the interlayer insulating layer 310 on the analog circuit region is not completely etched and the etch inhibiting layer on the PIP capacitor upper electrode 305 is exposed, a second etching process is performed as shown in FIG. 3D. In this case, the etching is performed by using an etching selectivity between the etching suppression layer 309 and the interlayer insulating layer 310, and the etching rate of the etching suppression layer is slower than the etching rate of the interlayer insulating layer. This prevents the PIP capacitor top electrode from being exposed until all are etched.

For example, assuming that a nitride film is used as an etch inhibiting film and an oxide film is laminated as an interlayer insulating film, and the etching rates of the nitride film and the oxide film are 9 kV / sec and 90 kV / sec, respectively, the nitride film and the oxide film having the same height are used. The etching rate of the oxide film is 10 times faster when etching. By using such characteristics, the nitride film can be appropriately set in thickness to simultaneously form contact holes on the PIP capacitor and contact holes on the analog circuit in time.

The manufacturing method of the composite semiconductor device according to the present invention has the following effects.

By forming an etch inhibiting film having a relatively low etching rate compared to the interlayer insulating film on the upper electrode of the capacitor region to a predetermined thickness, the upper part of each region during etching of the interlayer insulating film formed on the capacitor region and the analog circuit region with different steps. Are simultaneously exposed in time to simplify the process of forming a contact hole.

1 is a structural cross-sectional view of a typical composite semiconductor device.

2A to 2E are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the prior art.

3A to 3D are cross-sectional views illustrating a method of manufacturing a composite semiconductor device according to the present invention.

Description of the main parts of the drawing

301 semiconductor substrate 302 insulating film

303a: first polysilicon film 303b: gate electrode

304: dielectric film 305: second polysilicon film

306: second spacer 307: first spacer

308: etch stop film 309: etch stop film

310: interlayer insulating film 311: photosensitive film pattern

Claims (4)

In the manufacturing method of a composite semiconductor device comprising a capacitor and a transistor, Stacking and selectively patterning an etch inhibiting film on the entire surface of the substrate where the upper electrode of the capacitor and the gate electrode of the transistor are formed to form an etch inhibiting film only on the upper electrode of the capacitor; Stacking an interlayer insulating film on an entire surface of the substrate including the etch inhibiting film; Forming an etch mask on the substrate to form a contact hole exposing a top electrode of the capacitor and a gate electrode and a source / drain of the transistor; Performing a first etching process of etching the interlayer insulating layer using the etching mask to expose an etch inhibiting layer formed on the upper electrode of the capacitor; Performing a second etching process of completing contact holes by etching both the etch suppression layer on the upper electrode and the interlayer dielectric layer on the transistor to expose the upper electrode of the capacitor and the gate electrode and the source / drain of the transistor; The manufacturing method of the composite semiconductor element characterized by the above-mentioned. The method of manufacturing a composite semiconductor device according to claim 1, wherein the etching inhibiting film is laminated to a thickness of 200 to 400 kW using a nitride film. The method of claim 1, wherein the etching selectivity between the etch inhibiting film and the interlayer insulating film is about 1: 5 to about 10. 9. The method of manufacturing a composite semiconductor device according to any one of claims 1 to 3, wherein the etching inhibiting film is formed of a nitride film.