KR100509605B1 - Driving method of plasma display panel and apparatus thereof - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel for reducing electromagnetic interference (EMI). A method of driving a plasma display panel for reducing electromagnetic interference according to the present invention is directed to a plasma display panel in which discharge cells are formed in regions where address electrode lines cross with respect to X and Y electrode lines that are alternately arranged side by side. A driving method of a plasma display panel which reduces electromagnetic interference by applying control signals having periodicity to each of an X driver, a Y driver, and an address driver for driving X and Y electrode lines and address electrode lines, respectively. The duty of the control signals to have changes over time. According to the driving method of the plasma display panel for reducing the electromagnetic interference according to the present invention, it is possible to easily reduce the electromagnetic interference that can occur when driving the plasma display panel without additional burden on the hardware.

Description

Driving method and apparatus thereof of plasma display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel for reducing electromagnetic interference (EMI), and more particularly, to reducing electromagnetic interference by varying the duty of a high frequency signal having a certain periodicity. The present invention relates to a driving method of a display panel.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one discharge cell of the panel of FIG. 1.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the conventional surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 , ..., A _Gm , A _Bm ), Dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, partition wall 17 ) And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and to prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

As a driving method of the plasma display panel 1 having the structure described above, an address-display separation driving method which is mainly used is disclosed in US Pat.

FIG. 3 illustrates a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

Referring to the drawing, a unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset period (not shown), an address period A1, ..., A8, and a sustain discharge period S1, ..., S8. do.

In each address period A1, ..., A8, a display data signal is applied to the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _{Bm in} FIG. 1) and each Y electrode line Scan pulses corresponding to (Y ₁ , ..., Y _n ) are applied sequentially.

In each sustain discharge period S1, ..., S8, display is performed on all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n . The discharge pulses are alternately applied to cause display discharge in discharge cells in which wall charges are formed in corresponding address periods A1, ..., A6.

Therefore, the luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1, ..., S8 occupied in the unit frame. The lengths of the sustain discharge cycles S1, ..., S8 occupy a unit frame are 255T (T is the unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, when the subfield to be displayed among the eight subfields is appropriately selected, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

According to the above-described address-display separation driving method, since the time domains of the subfields SF1, ..., SF8 are separated from each other in the unit frame, the address period and the address period of each subfield SF1, ..., SF8 are separated. The time domains of the display periods are also separated from each other. Therefore, in the address period, after each XY electrode line pair has been addressed, it has to wait until all other XY electrode line pairs are addressed. As a result, since the time period occupied by the address period becomes longer for each subfield, the display period becomes relatively short. Therefore, the luminance of light emitted from the plasma display panel is relatively low. In order to remedy this problem, a known method is an Address-While-Display driving method as shown in FIG.

FIG. 4 shows a conventional Address-While-Display driving method for the Y electrode lines of the plasma display panel of FIG. 1.

Referring to the drawing, the unit frame is divided into _eight sub-fields SF ₁ ,..., SF ₈ for time division gray scale display. Here, each unit sub-field overlaps each other based on the driven Y electrode lines Y ₁ ,..., Y n to form a unit frame. Therefore, since all sub-fields SF ₁ ,..., SF ₈ are present at all time points, an address time slot is set between each display discharge pulse for performing each address step.

Reset, address and sustain discharge steps are performed in each sub-field, and the time allocated to each sub-field is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) consists of 256 units of time, driving is performed according to the image data of the least significant bit (Least Significant Bit). Times corresponding to 2 ⁿ are set in the sustain discharge period Sn of the n th subfield SFn. That is, since the sum of the unit times allocated to each sub-field is 255 unit time, 255 gray scale display is possible, and when the gray level in which no display discharge is performed in any sub-field is included, 256 gray scale display is possible.

5 illustrates a general driving apparatus of the plasma display panel of FIG. 1.

Referring to the drawings, a typical driving device 2 of the plasma display panel 1 includes an image processor 26, a controller 22, an address driver 23, an X driver 24, and a Y driver 25. do. The image processing unit 26 converts an external analog image signal into a digital signal, for example, an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 22 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 26. The address driver 23 generates the display data signal by processing the address signal S _A among the drive control signals S _A , S _Y , and S _X from the controller 22, and generates the display data signal. Applied to the address electrode lines. The X driver 24 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the controller 22 and applies the X driving control signal S _X to the X electrode lines. The Y driver 25 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the controller 22 and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 6 shows driving signals applied to the panel of FIG. 1 in a unit sub-field by the address-display separation driving method of FIG. 3.

In FIG. 6, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 ..Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 7 shows the wall charge distribution of one discharge cell immediately after a gradual rising voltage is applied to the Y electrode lines Y ₁ , ... Y _n in the reset period PR of FIG. 6. 8 illustrates a wall charge distribution of one discharge cell at the end of the reset period PR of FIG. 6. 7 and 8, the same reference numerals as used in FIG. 2 indicate the objects of the same function.

Referring to FIG. 6, in the reset period PR of the unit sub-field SF, first, a voltage applied to the X electrode lines X ₁ ,..., X _n is _first divided from the ground voltage V _G. 2 voltage (V _S ), for example, continuously rising to 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

Next, the voltage applied to the Y electrode lines Y ₁ ,..., Y _n is third from the second voltage V _S , for example, from 155 volts V to a second voltage than the second voltage V _S. The highest voltage V _SET + V _{S that} is as high as the voltage V _SET is continuously raised to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

Next, in the state where the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S , the Y electrode lines Y ₁ ,..., Y _n The voltage applied to) is continuously lowered from the second voltage V _S to the ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 8). Further, the address electrode lines (A _R1, ..., A _Bm) is so applied with a ground voltage (V _G), the address electrode lines are positive wall charges around the (A _R1, ..., A _Bm) Slightly increased.

Accordingly, in a subsequent addressing period PA, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ biased to the fourth voltage V _SCAN lower than the second voltage V _S. As a scan signal of the ground voltage V _G is sequentially applied to the ..., Y _n ), smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. do. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. Here, the second voltage (V _S) on to the more accurate and efficient address discharge, the X electrode lines (X _1, ... X _n) applied.

In the sustain discharge period PS that follows, the display of the second voltage V _S is maintained on all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . The pulses are alternately applied, causing a discharge for maintaining the display in the discharge cells in which wall charges are formed in the corresponding address period PA.

9 is a block diagram schematically showing the internal structure of a conventional scan drive integrated circuit.

Referring to the drawings, the scan drive integrated circuit 3 includes a shift register 31 and a latch 32. The scan data signal is applied from the control unit 22 to the scan drive integrated circuit 3. The scan data signal includes a clock signal CLK, a data signal Data, an output enable signal STB, a blanking control signal BLK, and a high impedance control signal HIZ.

The data signal Data is input to the shift register 31 from the controller 22, shifts the data signal Data in synchronization with a clock signal CLK, outputs the data signal to the latch 32, and latch 32. ) Temporarily stores the output of the shift register 31 to enable the output according to the output enable signal input from the control unit 22, and outputs to the Y electrode lines through the predetermined logic circuit section (OUT1, ..., OUT64) Enable it.

The Y driver 25 used in the conventional plasma display panel driver as shown in FIG. 5 is typically formed by connecting at least one or more of the scan drive integrated circuits 3 in series.

FIG. 10 is a timing diagram schematically illustrating waveforms of control signals for operating the scan drive integrated circuit of FIG. 9.

Referring to the drawings, the clock signal CLK, the data signal Data, the output enable signal STB, and the blanking control signal BLK are applied to the scan drive integrated circuit 3 from the controller 22 in the addressing period PA. ), And the waveforms of the high impedance control signal HIZ, respectively.

As illustrated, the clock signal CLK, the output enable signal STB, and the blanking control signal BLK are all input to the scan drive integrated circuit with a high frequency control signal having a certain periodicity. In view of electromagnetic waves, these high frequency control signals having a certain periodicity have a problem of acting as a source of electromagnetic interference (EMI) due to electromagnetic radiation. In particular, the degree increases as the frequency is higher.

This problem is caused by a control signal such as a clock signal (CLK) used for synchronizing internally in the digital system not only in the scan drive integrated circuit but also in another circuit part included in the driving device of the plasma display panel including the data drive integrated circuit forming the address driver. The same applies to high frequency signals having a constant periodicity.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of driving a plasma display panel for reducing electromagnetic interference by varying the duty of a high frequency signal having a certain periodicity to reduce electromagnetic interference.

In order to achieve the above object, the driving method of the plasma display panel according to the present invention includes a plasma display panel in which discharge cells are formed in regions where address electrode lines cross with respect to X and Y electrode lines that are alternately arranged side by side. A method of driving a plasma display panel which reduces electromagnetic interference by applying control signals having periodicity to each of the X driver, the Y driver, and the address driver for driving each of the X and Y electrode lines and the address electrode lines. The duty of the control signals having the periodicity varies with time.

In this case, the control signal having the periodicity is preferably a clock signal.

According to the driving method of the plasma display panel for reducing the electromagnetic interference according to the present invention, it is possible to easily reduce the electromagnetic interference that can occur when driving the plasma display panel without additional burden on the hardware.

According to another aspect of the present invention, an apparatus for driving a plasma display panel for reducing electromagnetic interference may process image data input from the outside to generate a scan data signal, a reset / hold data signal, an address data signal, and a common data signal. And a Y driver for applying a scan driving signal according to the scan data signal to Y electrode lines, and a reset / holding signal for applying a reset / maintenance driving signal according to the reset and sustain data signals to the Y electrode lines. A circuit unit, an address driver for applying an address driving signal according to the address data signal to the address electrode lines, and an X driver for applying a common driving signal according to the common data signal to the X electrode lines. An apparatus for driving a plasma display panel to reduce the scan. A control signal having a periodicity is included in each of the data signal, the reset / hold data signal, the address data signal, and the common data signal, and the duty of the control signals having the periodicity varies with time.

In this case, the control signal having the periodicity is preferably a clock signal.

According to the driving apparatus of the plasma display panel for reducing the electromagnetic interference according to the present invention, it is possible to reduce the electromagnetic interference that may occur when driving the plasma display panel.

According to another aspect of the present invention, a scan drive integrated circuit may generate a scan driving signal according to the scan data signal including a control unit having a periodicity and a control unit for processing the image data input from the outside and generating a scan data signal. A driving device for a plasma display panel including a Y driver applied to a plurality of Y electrode lines, wherein at least one or more are connected in series to form the Y driver to reduce electromagnetic interference. The duty of the control signals with V varies over time.

In this case, the control signals having the periodicity are preferably clock signals.

According to the scan drive integrated circuit for reducing the electromagnetic interference according to the present invention, it is possible to reduce the electromagnetic interference that may occur when driving the plasma display panel.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 11 is a view schematically illustrating a driving device of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to the drawings, the driving device 4 of the plasma display panel includes a control unit 41, an address driving unit 42, an X driving unit 43, a reset / holding circuit unit 44, and a Y driving unit 45. It is made.

The controller 41 processes image data input from the outside to generate a scan data signal, a reset / hold data signal, an address data signal, and a common data signal. The address driver 42 applies an address driving signal corresponding to the address data signal to the address electrode lines. The X driver 43 applies a common driving signal according to the common data signal to X electrode lines. The reset / maintenance circuit section 44 applies a reset / maintenance driving signal corresponding to the reset and sustain data signals to the Y electrode lines. The Y driver 45 applies a scan driving signal corresponding to the scan data signal to Y electrode lines.

According to the driving method of the plasma display panel for reducing the electromagnetic interference according to the present invention, the duty band of the high frequency signal having a constant period and a constant duty causing the electromagnetic interference is varied, so that the frequency band of the emitted electromagnetic waves is in the vicinity of the surrounding band This results in a decrease in the peak value of electromagnetic radiation, thereby reducing electromagnetic interference that may occur when the plasma display panel is driven.

In particular, the Y driver may be connected to the at least one scan drive integrated circuit in series to apply power to the Y electrode lines, the same scan drive integrated circuit used in the present invention can be used as shown in FIG. In addition, detailed description beyond what is demonstrated in this invention is abbreviate | omitted.

Control signals having a periodicity are included in each of the scan data signal, the reset / hold data signal, the address data signal, and the common data signal, and the duty of the control signals having the periodicity changes with time.

That is, the duty of the control signals having the periodicity may change with time, or the period and the duty of the control signals with the periodicity may change with time. In this case, the duty refers to the ratio of the pulse width to the pulse period in the pulse wave as shown in FIG. 10.

In particular, each of the scan data signal, the reset / hold data signal, the address data signal, and the common data signal includes a Y driver 45, a reset / sustain circuit 44, an address driver 42, and X. A clock signal for driving in synchronization with each of the drivers 43 is required. The clock signal may be a high frequency pulse having a constant periodicity, similar to the clock signal CLK used in the scan drive integrated circuit shown as an example in FIG. 10. Can be. At this time, a high frequency pulse signal having a constant periodicity may cause electromagnetic interference as is well known.

Accordingly, the driving apparatus 4 of the plasma display panel according to the present invention proposes a method of varying the duty of the high frequency pulse signal having such a constant periodicity to reduce the emission of electromagnetic waves.

Scan data signals, reset / hold data signals, address data signals, and common data signals applied to the Y driver 45, the reset / hold circuit 44, the address driver 42, and the X driver 43, respectively. The method proposed in the present invention may be applied to all high frequency signals having a certain periodicity included in the field.

Particularly, in the method of driving a plasma display panel for reducing electromagnetic interference according to the present invention, at least one or more data drive integrated circuits forming an address driver 42 and a scan drive integrated circuit forming a Y driver 45 are connected in series. Applicable to the signals used in the circuit.

FIG. 13 is a timing diagram schematically illustrating a scan data signal in which a duty of a clock signal varies with time according to another exemplary embodiment of the present invention. FIG. 14 is a timing diagram schematically illustrating a scan data signal in which a cycle and a duty of a clock signal change with time according to another exemplary embodiment of the present invention.

Referring to the drawings, a timing diagram schematically showing waveforms of control signals for operating a scan drive integrated circuit by a method of driving a plasma display panel for reducing electromagnetic interference according to an embodiment of the present invention. The control signal input to the scan drive integrated circuit 3 includes a data signal Data, a clock signal CLK, a blanking control signal BLK, an output enable signal Strobe, STB, and a high signal. A high impedance control signal (HIZ) is provided.

In this case, the scan drive integrated circuit 3 includes a shift register 31 and a latch 32. The clock signal CLK is a signal that provides a synchronization signal for operation in a circuit. The output enable signal STB is a signal that enables the output to be output from a latch that temporarily stores the signal output from the shift register 31. The blanking control signal BLK is a signal for blanking control of the power outputs OUT1,..., OUT64. The high impedance control signal HIZ is a signal for high impedance control of the power outputs OUT1,..., OUT64.

As shown in Fig. 10, the clock signal CLK, the blanking control signal BLK, and the output enable signal Strobe, STB are high frequency signals having a constant periodicity, respectively, according to the method of the present invention. Will be applicable. In the present embodiment, the method according to the present invention is applied only to the clock signal CLK so that it can be distinguished from other signals.

Referring to FIG. 13, a signal is applied such that the duty of the clock signal CLK changes with time. The duty of each pulse (PW1 / T1, PW2 / T2, PW3 / T3, ...) has a different value for each pulse, and the period of each pulse (T1, T2, T3, ....) The clock signal CLK is formed and inputted to the scan drive integrated circuit so that has a same value for each pulse.

delete

Referring to FIG. 14, a signal is applied such that the period and duty of the clock signal CLK change with time. The duty of each pulse (PW1 / T1, PW2 / T2, PW3 / T3, ...) has a different value for each pulse, in addition to the period (T1, T2, T3, ...) of each pulse. ) Forms a clock signal CLK having a different value for each pulse and inputs it to the scan drive integrated circuit.

As shown in Figs. 13 to 14, the duty of the signal is changed over time, thereby removing the periodicity of the high frequency signal, which is known as the main cause of electromagnetic interference (EMI), from the signal. Accordingly, electromagnetic interference can be reduced as compared with the clock signal CLK shown in FIG. 10.

According to the driving method of the plasma display panel for reducing the electromagnetic interference according to the present invention, the duty of the high frequency signal having a certain periodicity that causes the electromagnetic interference is varied, so that the frequency band of the electromagnetic wave is scattered to the surrounding band As a result, the peak value of the electromagnetic radiation is reduced, thereby reducing the electromagnetic interference that may occur when the plasma display panel is driven.

In addition, since only the control signals applied to the driving apparatus of the conventional plasma display panel are adjusted, the electromagnetic interference can be easily reduced without additional burden on hardware.

In addition, since there is no additional burden of hardware, it is possible to reduce the electromagnetic interference without additional cost by using a conventional plasma display panel driving apparatus.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

2 is a view showing an example of one discharge cell of the panel of FIG.

3 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

4 is a timing diagram illustrating a conventional address-display simultaneous driving method for Y electrode lines of the plasma display panel of FIG. 1.

5 is a block diagram illustrating a general driving device of the plasma display panel of FIG. 1.

FIG. 6 is a timing diagram illustrating driving signals applied to a panel of FIG. 1 in a unit sub-field of the address-display separation driving method of FIG. 3.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell immediately after a gradual rising voltage is applied to the Y electrode lines in the reset cycle of FIG. 6.

8 is a cross-sectional view illustrating a wall charge distribution of one discharge cell at the end of the reset cycle of FIG. 2.

9 is a block diagram schematically showing the internal structure of a conventional scan drive integrated circuit.

FIG. 10 is a timing diagram schematically illustrating waveforms of control signals for operating the scan drive integrated circuit of FIG. 9.

FIG. 11 is a view schematically illustrating a driving device of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 13 is a timing diagram schematically illustrating a scan data signal in which a duty of a clock signal varies with time according to another exemplary embodiment of the present invention.

delete

FIG. 14 is a timing diagram schematically illustrating a scan data signal in which a cycle and a duty of a clock signal change with time according to another exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A ₁ , ..., A _m ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... sub-field,

S _Y1 , ..., S _Yn ... Y electrode drive signal, V _G ... ground voltage,

S _X1 , ..., S _Xn ... X electrode drive signal, SF ... unit sub-field,

S _AR1 .. _ABm ... display data signal, 22 ..

23.address drive, 24..X drive,

25 ... Y drive unit, 26 ... image processing unit,

Claims (9)

An X driver for driving each of the X and Y electrode lines and the address electrode lines in a plasma display panel in which discharge cells are formed in regions where address electrode lines intersect with respect to X and Y electrode lines that are alternately arranged side by side. A driving method of a plasma display panel for reducing electromagnetic interference by applying control signals having periodicity to each of the Y driver and the address driver, And the duty of the control signals having the periodicity varies with time. The method of claim 1, And a control signal having the periodicity is a clock signal. A control unit which processes image data input from outside and generates a scan data signal, a reset / hold data signal, an address data signal, and a common data signal, and applies a scan driving signal according to the scan data signal to Y electrode lines A Y driving unit configured to apply a reset / maintenance driving signal corresponding to the reset and sustain data signals to the Y electrode lines, and an address driving signal corresponding to the address data signal is applied to the address electrode lines. In the driving device of the plasma display panel to reduce the electromagnetic interference by providing an address driver to the driver and an X driver for applying a common driving signal according to the common data signal to the X electrode lines, A control signal having periodicity is included in each of the scan data signal, the reset / hold data signal, the address data signal, and the common data signal, and the duty of the control signals having the periodicity varies with time. Drive system. The method of claim 3, And a control signal having the periodicity is a clock signal. A control unit for generating a scan data signal by processing image data input from the outside and a Y driving unit for generating a scan driving signal according to the scan data signal including control signals having a periodicity and applying the scan driving signal to a plurality of Y electrode lines In the driving device of the plasma display panel, at least one or more are connected in series to form the Y drive unit in the scan drive integrated circuit to reduce the electromagnetic interference, And the duty of the control signals having the periodicity varies with time. The method of claim 5, And a control signal having said periodicity is a clock signal. The method of claim 1, And the control signals having the periodicity change with a period of time. The method of claim 3, And the control signals having the periodicity change with a period of time. The method of claim 5, And the control signals having the periodicity vary with period time.