KR100505633B1 - Data reading apparatus and method for cache memory - Google Patents

Abstract

An apparatus and method for reading data from a cache memory are disclosed. In the data reading apparatus of the cache memory according to the present invention, the cache memory has a set address and a tag address determined by an input index, and accesses a predetermined number of set data corresponding to the determined tag address regardless of the determined set address. A predetermined number of registers for storing a predetermined number of set data, a selector for selectively outputting set data stored in the predetermined number of registers in response to a set selection address, and a determined set address and a determined tag address. Compare the program address with the program address, output a set select signal according to the result of the comparison, output the set data selected by the selector, or update the determined tag and set address and access the cache memory again in correspondence with the kinexin tag and set address. Controlled Comparison When the CPU accesses the cache memory, all the set data corresponding to the tag address are accessed and stored in the registers so that the cache memory needs to be accessed again when only the set address is missed. There is an effect that the performance of the CPU can be improved by selectively reading the set data stored in the registers corresponding to the set select address generated in the hit / miss logic.

Description

Data reading apparatus and method for cache memory

The present invention relates to a cache memory, and more particularly, to an apparatus and method for reading data of a cache memory for reading data from a cache memory of an n-way set association method.

In general, a high-speed central processing unit (CPU) transfers frequently used data from external memory, such as DRAM, to cache memory, a relatively small memory inside the CPU, to improve performance. Save it. On the other hand, the cache memory is largely divided into an instruction cache for storing instructions and a data cache for storing operation results.

These cache memories are accessed by the CPU during instruction execution and if the desired data does not exist in the cache memory, the CPU retrieves the necessary data from the external memory after a certain process (a certain miss flow). This improves CPU performance if the desired data is in the cache (when it is hit) without the need to access external memory, but if the desired data is not in the cache (when it is missed), the CPU needs to access the external memory. Is degraded. Therefore, increasing the hit ratio of the cache is very important to improve the performance of the CPU. On the other hand, the performance of the cache has a direct impact on the performance of the CPU, the size, way, speed, etc. that determine the performance of the cache.

Currently, many ways of associating n-way sets with proper compensation for cache performance and speed are used. In the two-way set correlation method, an index field for accessing a predetermined line of a cache and a tag address portion for determining the set and the tag address portion of the line are determined. Whether or not there is data desired by the CPU in the cache memory is compared with the address from the translator that translates the tag address and the address specified by the program.If the two addresses are the same, the cache hit is said, and if the addresses are different, the cache miss Will be judged. The set address is then included in the tag address and used for comparison. Therefore, if the set address is missed, it is determined to be a cache miss, and the cache memory is accessed again after correcting the tag address and the set address of the cache according to a predetermined miss flow in the CPU.

FIG. 1 is a schematic block diagram illustrating an apparatus for reading a cache memory according to the prior art, and includes a cache memory 40 having a first set region 10, a second set region 20, and a tag region 30. , Comparator 60 and hit / miss logic 70.

Referring to FIG. 1, a set of a predetermined line and an address of a tag are determined by an index ID input to the cache memory 40. That is, the cache memory 40 selectively reads the tag address TADD determined by the index ID and the set address SADD among the first and second set data corresponding to the tag address TADD. At this time, the set address SADD predicts that the second set data is currently output if the first set data has been previously selected, and the set address SADD is determined according to the prediction. The tag address TADD determined by the index ID is input to the comparator 60.

Although not shown, the comparator 60 compares the program address PADD generated by an address translator (not shown) that converts an address designated by a process core (not shown), and compares the result to the hit / miss logic 70. Output According to the comparison result from the comparator 60, the hit / miss logic 70 determines that the cache is a hit when the two data match, and sets the process data corresponding to the set address SADD determined by the index ID. A control signal for controlling (not shown) to be read as desired data is output to the output terminal OUT. However, if the two data to be compared are different, it is determined to be missed, and after correcting the tag and set address (TADD and SADD) of the cache according to a predetermined miss flow, the control signal is returned to the output terminal OUT to access the cache memory again. Output

On the other hand, the set address SADD of the cache memory 40 is included in the tag address TADD and compared with the program address PADD in the comparator 60. Therefore, when the tag address TADD is hit but the set address is missed, it is determined to be a cache miss and attempts to access the cache again according to a predetermined flow, which causes a problem that the performance of the CPU is degraded.

An object of the present invention is to provide a data read device of a cache memory that can access data of a desired set address without re-accessing the cache memory when the tag address is hit and the set address is missed.

Another object of the present invention is to provide a data reading method performed by the data reading apparatus of the cache memory.

In order to achieve the above object, a data read device of a cache memory according to the present invention for reading the data stored in a cache memory having a predetermined number of set areas storing data and a tag area storing a tag address, The set memory and the tag address are determined by an index to be input, and the cache memory accesses and outputs a predetermined number of set data corresponding to the determined tag address regardless of the determined set address, and stores the predetermined number of set data, respectively. A predetermined number of registers, a selector for selectively outputting set data respectively stored in the predetermined number of registers in response to the set selection address, and a determined set address and a determined tag address and a program address are compared and set according to a comparison result. Outputs a selection signal to the selector It is characterized in that outputs the selected set of data or determined to update the tag and set address corresponds to the tag and set address kaengsin comprising a comparison means for controlling access to a cache memory.

In order to achieve the above object, a cache memory having a predetermined number of set areas for storing data and a tag area for storing tag addresses is included, and the set addresses and tag addresses determined by an index input to the cache memory are provided. The method of reading data of the cache memory according to the present invention, which reads the corresponding set data, includes determining whether the determined tag address has been missed. If the tag address determined in the steps (a) and (a) is missed, The tag address and the set address are updated accordingly, and if the tag address is hit in steps (b) and (a), the method determines whether the determined set address has been missed. If the set address determined in step 2 is missed, step (d) of selecting another set address corresponding to the determined tag address If the set address determined in steps (e) and (c) of reading the set data corresponding to the selected set address is hit, the step (f) of reading set data corresponding to the determined set address is performed. It features.

Now, an apparatus and method for reading data of a cache memory according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a schematic block diagram illustrating an apparatus for reading data of a cache memory according to an exemplary embodiment of the present invention. The cache memory 100 including a first and second set regions 105 and a tag region 115 may be described. And second registers 120 and 125, selector 130, comparator 135, and hit / miss logic 140.

The apparatus illustrated in FIG. 2 is a data reading apparatus of a cache memory using a 2-way set association method. Two set data correspond to one tag address, and the two set data are selected by the set address, respectively.

3 is a flowchart illustrating a data reading method of a cache memory according to an embodiment of the present invention. If a tag address is missed, the method further includes determining whether the tag address is missed after correcting the tag address and set address according to a predetermined misflow. If the tag address is hit (steps 200 to 205), the set data are selected and output (steps 210 to 225) according to whether or not the set address is hit or missed.

In the cache memory 100 illustrated in FIG. 2, a set address and a tag address are determined according to an input index ID. At this time, the cache memory 100 accesses and outputs both the first set data and the second set data corresponding to the determined tag address TADD regardless of the determined set address.

The first and second registers 120 and 125 store first and second set data respectively output from the cache memory 100. The selector 130 selects and outputs first or second set data in response to the set selection address ADD_SEL generated by the hit / miss logic 140.

The comparator 135 is generated by an address translator (not shown) that translates a tag address TADD and a set set address SADD determined from the cache memory 100 and an address designated by a process core (not shown), although not shown. The program address PADD is input and compared, and the comparison result is output to the hit / miss logic 140. The hit / miss logic 70 determines the hit / miss based on the comparison result from the comparator 135 and controls the cache memory accordingly.

First, it is determined whether the determined tag address TADD is missed (step 200). If the determined tag address TADD is missed, the tag address TADD and the set address SADD are corrected according to a predetermined miss flow. The process proceeds to step 200 again (step 205). In contrast, if the tag address TADD determined in operation 200 is hit, it is determined whether the determined set address SADD is missed (operation 210). If the determined set address is missed, another set address corresponding to the determined tag address TADD is output to the selector 130 as the set selection address SADD_SEL (step 215). After operation 215, the selector 130 selectively reads and outputs set data corresponding to the set selection address SADD_SEL from the first or second registers 120 and 125.

For example, it is assumed that a set address SADD determined by the index ID corresponds to the first set data, and a program address PADD specifies a set address corresponding to the second set data so that a miss occurs in the set address. Then, the hit / miss logic 140 outputs the set address corresponding to the second set data to the selector 130 as the set selection address SADD_SEL, and the selector 130 selectively outputs the second set data. . That is, although the set address SADD determined by the index ID input to the cache memory 100 corresponds to the first set data, the data output by the selector 130 is finally the second desired by the process core. The set data is output.

If the set address SADD determined in operation 210 is hit, the hit / miss logic 140 outputs the determined set address SADD to the selector 130 as the cell selection address SADD_SEL and selector 130. In operation 225, the set data corresponding to the cell selection address SADD_ADD may be selectively read from the first or second register 120 or 125.

For example, it is assumed that the set address SADD determined by the index ID corresponds to the first set data, and the program address PADD also specifies a set address corresponding to the first set data. Then, the hit / miss logic 140 outputs the set address corresponding to the first set data to the selector 130 as the set selection address SADD_SEL, and the selector 130 selectively outputs the first set data. . That is, the first set data by the set address SADD determined by the index ID input to the cache memory 100 is finally output as the data desired by the process core.

In the above description, the 2-way set association method is described. In the 4-way set association method, four registers are used.

As a result, when the CPU accesses the cache memory, the apparatus and method for reading data from the cache memory according to the present invention access all the set data corresponding to the tag address and store them in the registers, and the hit / miss logic 140 The set data stored in the registers may be selectively read in correspondence to the set select address SADD_SEL generated at. As a result, when the tag address is hit but the set address is missed, the CPU accesses the set data desired by simply changing the cell select address SADD_SEL in the hit / miss logic 140 without having to access the cache memory again. You can do it.

As described above, the apparatus and method for reading data of the cache memory according to the present invention accesses and stores all set data corresponding to the tag address in the registers when the CPU accesses the cache memory, so that the tag address is a hit. However, if the set address is missed, the CPU performance can be improved by selectively reading the set data stored in the registers corresponding to the set select address generated by the hit / miss logic without having to access the cache memory again. .

FIG. 1 is a schematic block diagram illustrating an apparatus for reading a cache memory according to the prior art.

2 is a schematic block diagram illustrating a data reading apparatus of a cache memory according to the present invention.

3 is a flowchart illustrating a data reading method of a cache memory according to the present invention.

Claims (3)

A data reading apparatus of a cache memory for reading out the data stored in a cache memory having a predetermined number of set areas storing data and a tag area storing tag addresses, The cache memory determines a set address and a tag address by an input index, and accesses and outputs all the predetermined number of set data corresponding to the determined tag address regardless of the determined set address. A predetermined number of registers respectively storing the predetermined number of set data; A selector for selectively outputting the set data respectively stored in the predetermined number of registers in response to a set selection address; And Comparing the determined set address and the determined tag address with a program address, and outputting the set selection signal according to a result of the comparison to output the set data selected by the selector, or updating the determined tag and the set address and performing the kinexin tag. And comparison means for controlling the cache memory to be accessed again in correspondence with a set address. The method of claim 1, wherein the comparing means A comparator for comparing whether the determined set address and the determined tag address are hit to the program address, respectively; And If the determined set address and the determined tag address are both hit by the comparator, the determined set address is output as the selected set address, and if the determined tag address is hit, but the determined set address is missed, the determined tag address is output to the determined tag address. And a hit / miss logic for outputting another corresponding set address to the selected set address, and controlling to access the cache memory again according to a predetermined miss flow when both the set set address and the determined tag address are missed. The data reading device of the cache memory. A cache memory having a predetermined number of set areas storing data and a tag area storing tag addresses, wherein the set address determined by an index input to the cache memory and set data corresponding to the tag addresses are stored. In the data read method of the cache memory to read, (a) determining whether the determined tag address has been missed; (b) if the determined tag address is missed in step (a), updating the tag address and the set address according to a predetermined miss flow, and proceeding to step (a); (c) determining whether the determined set address is missed if the tag address is hit in step (a); (d) if the determined set address is missed in step (c), selecting another set address corresponding to the determined tag address; (e) reading set data corresponding to the selected set address; And (f) if the determined set address is hit in step (c), reading the set data corresponding to the determined set address.