KR100500922B1 - Logic operational circuit for operating stably in low voltage - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a logic operation circuit capable of performing a logic operation stably at a low voltage. To this end, the present invention provides an exclusive logic sum circuit of two inputs that performs an exclusive OR operation on two input signals. First pull-down driving means for pull-down driving the output signal in response to the first and second input signals; Second pull-down driving means for pull-down driving the output signal in response to the inverted first and second input signals; First pull-up driving means for pull-up driving the output signal in response to the inverted first input signal and the second input signal; And second pull-up driving means for pull-up driving the output signal in response to the first input signal and the inverted second input signal.

Description

Logic operation circuit for performing stable operation at low voltage {LOGIC OPERATIONAL CIRCUIT FOR OPERATING STABLY IN LOW VOLTAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic operational circuit, in particular an exclusive OR circuit capable of stable logic operation without malfunction due to a voltage drop at a low voltage and an exclusive NOR circuit. Hereinafter referred to as XNOR).

Recently developed memory is designed to operate at low power and low voltage at high speed. Therefore, the logic arithmetic circuit employed in such a low voltage memory must also be able to operate stably at low voltage.

As is well known, the XOR circuit and the XNOR circuit perform logical operations as shown in the truth table shown in Table 1 below.

TABLE 1

1 is a conventional two-input XOR circuit diagram, and FIG. 2 is a conventional two-input XNOR circuit diagram.

As shown in the figure, the conventional two-input XOR circuit is connected in series to the power supply voltage terminal VCC and receives two input PMOS transistors P1 and P2 and PMOS transistors, respectively. It is connected to the drain terminal of P2 and is connected to the drain terminal of the NMOS transistor N1 and PMOS transistor P2 to which the input signals A and B are sequentially applied to the gate terminal and the source terminal. The signals output from the common drain terminal of the NMOS transistor N2, the PMOS transistor P2, and the NMOS transistors N1 and N2 to which the signals B and A are sequentially applied are inverted to the final output signal X of the XOR circuit. It consists of an inverter I1 which exports.

The conventional two-input XNOR circuit is configured in the same manner as the XNOR circuit, and the signal output from the common drain terminal of the PMOS transistor P2 and the NMOS transistors N1 and N2 without the inverter I1 is outputted to the final output of the XNOR circuit. It is configured to export as signal (/ X).

3 and 4 are operational waveform diagrams for a conventional two-input XOR circuit and an XNOR circuit.

1 to 4, when the "HIGH, VCC level" signal is input to the two input signals A and B in the conventional two-input XOR circuit and the XNOR circuit made as described above. Look at the behavior.

First, the PMOS transistors P1 and P2 and the NMOS transistors N1 and N2 are turned off and turn-on by input signals A and B of "high" level, respectively. do. At this time, a "high" signal is simultaneously applied to the gate terminal and the source terminal of the NMOS transistors N1 and N2 so that the signals VCC-VTN, which are voltage-falled by the threshold voltage VTN of the NMOS transistor at the VCC level, are NMOS transistors N1 , To the common drain stage of N2). The XOR circuit inverts the " VCC-VTN " signal delivered to the common drain terminal of the NMOS transistors N1 and N2 through the inverter I1 to output a " LOW " as an output signal X, and the XNOR circuit The "VCC-VTN" signal transmitted to the common drain terminal of the NMOS transistors N1 and N2 is output as it is as an output signal / X.

When the conventional XOR and XNOR circuits as described above are applied to a memory device operating at a low voltage, such a voltage drop may cause a malfunction of the memory device, and also cause the memory to operate at a lower speed. .

The present invention has been proposed to solve the above problems, and an object thereof is to provide a logic operation circuit capable of stably performing a logic operation operation at a low voltage.

In order to achieve the above object, the present invention provides a multiple input exclusive OR circuit for performing an exclusive OR operation on a plurality of input signals, the first pull-down driving output signals in response to the plurality of input signals. Down drive means; Second pull-down driving means for pull-down driving the output signal in response to the inverted plurality of input signals; And a plurality of pull-up driving means for pull-up driving the output signal in response to at least one inverted input signal of the plurality of input signals.

The present invention also provides a multiple input exclusive negative logic circuit for performing an exclusive negative logic operation on a plurality of input signals, the first pull-up driving for pull-up driving an output signal in response to the plurality of input signals. Way; Second pull-up driving means for pull-up driving the output signal in response to the inverted plurality of input signals; And a plurality of pull-down driving means for pull-down driving the output signal in response to at least one inverted input signal of the plurality of input signals.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

5 is a two-input XOR circuit diagram in accordance with an embodiment of the present invention.

As shown in FIG. 5, the XOR circuit of the present invention includes a pull-down driving unit 100 for pull-down driving the output signal X in response to the input signals A and B, and an inverted input signal (/). A pull-down driving unit 200 which pull-downs the output signal X in response to A and / B, and an output signal X in response to the inverted input signal / A and the input signal B A pull-up driver 300 for driving a pull-up, and a pull-up driver 400 for driving a pull-up of an output signal X in response to an input signal A and an inverted input signal / B. Is made of.

The pull-down driver 100 is connected in series between an output terminal for outputting the output signal X and a ground power supply terminal, and is connected to two NMOS transistors N10 and N11 that receive the input signals A and B sequentially. The pull-down driving unit 200 is connected in series between an output terminal for outputting the output signal X and a ground power supply terminal, and two NMOSs sequentially receiving the inverted input signals (/ A, / B) to the gate. It consists of transistors N12 and N13.

In addition, the pull-up driving unit 300 is connected in series between the power supply voltage terminal and the output terminal, and two PMOS transistors P10 and P11 which receive the input signal / A and the inverted signal B inverted to the gate in turn. The pull-up driving unit 400 is connected in series between a power supply voltage terminal and an output terminal, and includes two PMOS transistors P12 that sequentially receive an input signal A and an inverted input signal / B through a gate. P13).

FIG. 6 is a waveform diagram illustrating the 2-input XOR circuit of FIG. 5.

5 and 6, the operation of the XOR circuit of the present invention will be described.

When a "high" signal is applied to both input signals A and B, the NMOS transistors N10 and N11 of the pull-down driving unit 100 are turned on to "low" the VSS level to the output terminal X. Output the signal. At this time, the pull-down driving unit 200 and the pull-up driving units 300 and 400 are turned off and do not drive the output terminal X.

Next, when a "low" signal is applied to both input signals A and B, the NMOS transistors N12 and N13 of the pull-down driving unit 200 are turned on to output V to the output terminal X. Outputs a "low" signal. At this time, the pull-down driving unit 100 and the pull-up driving units 300 and 400 are turned off and do not drive the output terminal X.

Next, when the "high" signal is applied as the input signal A and the "low" signal as the input signal B, the PMOS transistors P10 and P11 of the pull-up driving unit 300 are turned on to output the output terminal ( X) outputs a "high" signal at the VCC level. At this time, the pull-up driving unit 400 and the pull-down driving units 100 and 200 are turned off and do not drive the output terminal X.

Lastly, when a "low" signal is applied as the input signal A and a "high" signal as the input signal B, the PMOS transistors P12 and P13 of the pull-up driver 400 are turned on to output an output terminal ( X) outputs a "high" signal at the VCC level. At this time, the pull-up driving unit 300 and the pull-down driving units 100 and 200 are turned off and do not drive the output terminal X.

Therefore, the XOR circuit of the present invention outputs a "low" signal when the same level signal is input to the two input signals A and B, and outputs a "high" signal when the signals of different levels are input, respectively. The logic operation of the XOR circuit is implemented, but a voltage drop phenomenon occurring in the conventional XOR circuit does not occur.

7 is a two-input XNOR circuit diagram according to another embodiment of the present invention.

As shown in FIG. 7, the XNOR circuit of the present invention includes a pull-up driver 500 that pull-ups the output signal / X in response to the input signals A and B, and an inverted input signal (/). A pull-up driving unit 600 for pull-up driving the output signal / X in response to A and / B, and an output signal X in response to the input signal A and the inverted input signal / B. ), A pull-down driver 700 for pull-down driving, and a pull-down driver 800 for pull-down driving the output signal X in response to the inverted input signal / A and the input signal B. )

The pull-up driver 500 is connected in series between a power supply voltage terminal and an output terminal, and is composed of two PMOS transistors P14 and P15 sequentially receiving input signals A and B through gates. 600 is connected in series between the power supply voltage terminal and the output terminal, and consists of two PMOS transistors (P16, P17) which in turn receives the input signal / A, / B inverted to the gate.

In addition, the pull-down driving unit 700 is connected in series between the output terminal and the ground power supply terminal, and two NMOS transistors N14 and N15 which sequentially receive an input signal A and an inverted input signal / B through a gate. The pull-down driving unit 800 is connected in series between the output terminal and the ground power supply terminal, and two NMOS transistors N16, which receive an input signal (A) and an input signal B inverted to the gate in sequence, N17).

FIG. 8 is a waveform diagram illustrating the two-input XNOR circuit of FIG. 7.

7 and 8, the operation of the XNOR circuit of the present invention will be described.

When the "low" signal is applied to the two input signals A and B, the PMOS transistors P14 and P15 of the pull-up driving unit 500 are turned on to "high" the VCC level to the output terminal X. Output the signal. At this time, the pull-up driving unit 600 and the pull-down driving unit 700 and 800 are turned off and do not drive the output terminal X.

Next, when the "high" signal is applied to both input signals A and B, the PMOS transistors P16 and P17 of the pull-up driving unit 600 are turned on to output the output terminal X to the VCC level. Outputs a "high" signal. At this time, the pull-up driving unit 500 and the pull-down driving unit 700 and 800 are turned off to not drive the output terminal X.

Next, when the "high" signal is applied as the input signal A and the "low" signal as the input signal B, respectively, the NMOS transistors N14 and N15 of the pull-down driving unit 700 are turned on to output the output terminal ( X) outputs a "low" signal at the VSS level. At this time, the pull-down driving unit 800 and the pull-up driving units 500 and 600 are turned off and do not drive the output terminal X.

Finally, when the "low" signal is applied as the input signal A and the "high" signal as the input signal B, the NMOS transistors N16 and N17 of the pull-down driver 800 are turned on to output the output terminal ( X) outputs a "low" signal at the VSS level. At this time, the pull-down driving unit 700 and the pull-up driving unit 500 and 600 are turned off and do not drive the output terminal X.

Therefore, the XNOR circuit of the present invention outputs a "high" signal of the VCC level when the same level of signal is input to the two input signals A and B, and "the VSS level" when the signals of different levels are input. The logic operation of the XOR circuits respectively outputting the "low" signal is implemented, but the voltage drop phenomenon occurring in the conventional XNOR circuit does not occur.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention made as described above, there is an effect that the logic operation operation of XOR or XNOR can be stably performed even at low voltage because no voltage drop phenomenon occurs.

1 is a conventional two-input XOR circuit diagram.

2 is a conventional two-input XNOR circuit diagram.

3 is an operational waveform diagram of a conventional two-input XOR circuit of FIG.

4 is a diagram of a conventional operation waveform for the two-input XNOR circuit of FIG.

5 is a two-input XOR circuit diagram in accordance with an embodiment of the present invention.

6 is a waveform diagram of the two-input XOR circuit of FIG.

7 is a two-input XNOR circuit diagram in accordance with another embodiment of the present invention.

8 is a waveform diagram of the two-input XNOR circuit of FIG.

* Description of the main parts of the drawing

100, 200, 700, 800: pull-down drive

300, 400, 500, 600: pull-up drive

Claims (4)

In a multi-input exclusive OR circuit that performs an exclusive OR operation on a plurality of (three or more) input signals, First pull-down driving means for pull-down driving an output signal in response to the plurality of input signals, in series between an output terminal for outputting the output signal and a ground power supply terminal, the plurality of inputs being gated to respective gates; A plurality of first NMOS transistors that receive signals in sequence; Second pull-down driving means for pull-down driving the output signal in response to the plurality of inverted input signals, in series between the output terminal and the ground power supply terminal, the plurality of inverted inputs to respective gates A plurality of second NMOS transistors that receive signals in sequence; And A plurality of pull-up driving means for pull-up driving the output signal in response to at least one inverted input signal of the plurality of input signals, in series between a power supply voltage terminal and an output terminal for outputting the output signal; And a plurality of PMOS transistors receiving the plurality of input signals through respective gates, at least one of which receives the inverted input signals. And a multi-input exclusive OR circuit. In a two-input exclusive OR circuit that performs an exclusive OR operation on two input signals, First pull-down driving means for pull-down driving an output signal in response to first and second input signals, the series being connected between an output terminal for outputting the output signal and a ground power supply terminal; First and second NMOS transistors that sequentially receive two input signals; Second pull-down driving means for pull-down driving the output signal in response to the inverted first and second input signals, the first and inverted gates being connected in series between the output terminal and the ground power supply terminal; A third and fourth NMOS transistors which in turn receive a second input signal; First pull-up driving means for pull-up driving the output signal in response to the inverted first input signal and the second input signal, being serially connected between a power supply voltage terminal and an output terminal for outputting the output signal, First and second PMOS transistors sequentially receiving the first input signal and the second input signal inverted to a gate; And Second pull-up driving means for pull-up driving the output signal in response to the first input signal and the inverted second input signal, a series connected between a power supply voltage terminal and the output terminal, the first to a gate; Third and fourth PMOS transistors that sequentially receive an input signal and the inverted second input signal; A 2-input exclusive OR circuit comprising: In a multi-input exclusive negative logic circuit for performing an exclusive negative logic operation on a plurality of (three or more) input signals, First pull-up driving means for pull-up driving an output signal in response to the plurality of input signals, in series between a power supply voltage terminal and an output terminal for outputting the output signal, the plurality of inputs being gated to respective gates; A plurality of first PMOS transistors for sequentially receiving signals; Second pull-up driving means for pull-up driving the output signal in response to the plurality of inverted input signals, the second plurality of pull-up driving means being serially connected between a power supply voltage terminal and the output terminal, and each of the inverted plurality of gates A plurality of second PMOS transistors, which in turn receive input signals; And A plurality of pull-down driving means for pull-down driving the output signal in response to at least one inverted input signal of the plurality of input signals-serially connected between an output terminal for outputting the output signal and a ground power supply terminal; And a plurality of NMOS transistors receiving the plurality of input signals through respective gates, at least one of which receives the inverted input signals. A multi-input exclusive negative logic circuit comprising: In a two-input exclusive negative logic circuit performing an exclusive negative logic operation on two input signals, First pull-up driving means for pull-up driving an output signal in response to first and second input signals, the series being connected between a power supply voltage terminal and an output terminal for outputting the output signal, the first and second gates being connected to a gate; First and second PMOS transistors that in turn receive two input signals; Second pull-up driving means for pull-up driving the output signal in response to the inverted first and second input signals, the first and second inverted gates being connected in series between a power supply voltage terminal and the output terminal; A third and fourth PMOS transistors which in turn receive a second input signal; First pull-down driving means for pull-down driving the output signal in response to the first input signal and the inverted second input signal-being connected in series between an output terminal for outputting the output signal and a ground power supply terminal; First and second NMOS transistors that sequentially receive the input signal and the inverted second input signal through a gate; And Second pull-down driving means for pull-down driving the output signal in response to the inverted first input signal and the second input signal, the series being connected in series between the output terminal and the ground power supply terminal; Third and fourth NMOS transistors sequentially receiving a first input signal and the second input signal; A 2-input exclusive negative logic circuit comprising: