KR100496795B1 - Static random access memory device - Google Patents

Abstract

The semiconductor memory device of the present invention has an array of memory cells for storing information, is connected to the array, and senses and amplifies data of addressed memory cells among the memory cells in response to a sense amplification reference signal and a sense amplification activation signal. A sense amplifying circuit for; A voltage detection circuit which receives an external power supply voltage and detects when the external power supply voltage becomes higher than a reference level and sequentially generates detection signals at regular intervals as the external power supply voltage gradually increases; A band gap reference circuit that receives the external power supply voltage and generates a reference voltage in response to the detection signals when the chip is activated; And a sense amplification reference signal generation circuit that receives the reference voltage and generates the sense amplification reference signal.

Description

Static random access memory device {STATIC RANDOM ACCESS MEMORY DEVICE}

The present invention relates to a static random access memory device, and more particularly, to a static random access memory device for reducing an operating current.

Recently, high speed static random access memory (SRAM) devices have been shown to have the biggest problem of increased power consumption due to high speed and byte-wide trends.

1 is a circuit diagram showing a main sense amplifier circuit used in a high speed SRAM device. FIG. 2 is a circuit diagram illustrating a band gap reference circuit according to the related art, and FIG. 3 is a diagram illustrating an output characteristic of FIG. 2.

The signal REFSA applied to the main sense amplifier circuit of FIG. 1 is a reference voltage level input signal and has a constant voltage level with respect to the supply voltage increase. Accordingly, the constant current flows in the NMOS transistors 10 controlled by the signal REFSA so as to maintain a constant gate-source potential difference at all times.

Therefore, a large current flows in the read state in which all the main sense amplifier circuits are operated. At this time, the operating current consumed by the main sense amplifier circuit accounts for a large proportion of the operating current (ICC) consumed in the entire chip. Accordingly, by reducing the current consumed in the main sense amplifier circuit when the external power supply voltage EVC is increased, the overall operating current consumption can be reduced.

Accordingly, an object of the present invention is to provide a static random access memory device capable of lowering the output level of a band gap reference circuit as the power supply voltage increases, thereby lowering the output level of circuits following the output level of the band gap reference circuit.

(Configuration)

According to one aspect of the present invention for achieving the above object, a semiconductor memory device having an array of memory cells for storing information, comprising: connected to the array, a sense amplification reference signal and a sense amplification activation signal A sense amplification circuit for responsively sensing and amplifying data of addressed memory cells of the memory cells; A voltage detection circuit which receives an external power supply voltage and detects when the external power supply voltage becomes higher than a reference level and sequentially generates detection signals at regular intervals as the external power supply voltage gradually increases; A band gap reference circuit that receives the external power supply voltage and generates a reference voltage in response to the detection signals when the chip is activated; A sense amplification reference signal generation circuit that receives the reference voltage and generates the sense amplification reference signal; The band gap reference circuit generates the reference voltage which is sequentially lowered according to the detection signals that are sequentially generated when the external power supply voltage is increased, thereby generating the reference signal generated from the sense amplification reference signal generation circuit. Characterized in that the level is lowered.

In this embodiment, the band gap reference circuit is connected to its output terminal and is characterized in that it comprises discharge means for lowering the potential of the output terminal in response to the detection signals.

In this embodiment, the discharge means comprises a plurality of first group of NMOS transistors connected between the output terminal and ground, the gates of the transistors being controlled by corresponding detection signals. .

In this embodiment, the discharging means comprises: a second group of NMOS transistors and a second group of NMOS transistors, operating as diodes, respectively connected between the first group of NMOS transistors and the ground; And a third group of NMOS transistors connected to the ground and controlled in the chip activation signal controlled in the chip activation signal to reduce current consumed in the standby state.

(Action)

With such a device, it is possible to reduce the current consumed in the main sense amplifier circuit by detecting when a power supply voltage having a level above the reference voltage is supplied and varying the output level of the band gap reference circuit according to the detected result. .

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 4 to 7 according to embodiments of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those skilled in the art, the present invention may be practiced only by the above description without these details.

4 is a block diagram illustrating a configuration of a static random access memory device according to the present invention. 5 is a diagram illustrating output characteristics of a level detection circuit according to a level change of an external power supply voltage.

Referring to FIG. 4, a static random access memory device according to the present invention includes a level detecting circuit 100, a band-gap reference circuit 120, a CS buffer 140, and a sensing circuit. A sense amplifier reference signal generating circuit 160 and a main sense amplifier circuit 180.

The level detection circuit 100 receives an external power supply voltage and detects when the external power supply voltage increases by more than a certain voltage (eg, 3.3V in FIG. 5) and sequentially as the external power supply voltage gradually increases. To generate detection signals HVi (where i = 1, 2, 3, 4). As shown in FIG. 5, the detection signal HV1 is at 3.2V, the detection signal HV2 is at 3.4V, the detection signal HV3 is at 3.6V, and the detection signal HV4 is 3.8. Transition from low level to high level respectively at V.

The band gap reference circuit 120 is configured to change an external power supply voltage according to the detection signals HVi when the signal CSP is activated through the CS buffer 140, that is, while the chip is selected. Generates (REF0). Detailed operation thereof will be described later.

The sense amplification reference signal generation circuit 160 generates a sense amplification reference signal REFSA having the same level as the reference voltage REF0 provided from the band gap reference circuit 120. In addition, the main sense amplifier circuit 180 sense-amplifies the data stored in the addressed memory cell, although not shown, in response to the signal REFSA provided from the circuit 160.

6 is a circuit diagram illustrating a band gap reference circuit according to a preferred embodiment of the present invention. FIG. 7 is a diagram illustrating output characteristics of the band gap reference circuit of FIG. 6 according to a change in the level of a power supply voltage.

Referring to FIG. 6, the band gap reference circuit 120 according to the present invention has the same configuration as that of FIG. 2, but further includes a discharge circuit at its output terminal REF0. Therefore, the operation and configuration description for the same configuration as that of FIG. 2 is omitted here.

The discharge circuit 122 according to the present invention consists of strings S1, S2, S3 and S4 of three NMOS transistors connected in series between the output terminal REF0 and ground. Since each string has the same configuration, the configuration of one string S1 will be described as an example, but the remaining strings S2, S3, and S4 have the same configuration. The first string S1 is composed of three NMOS transistors MN1, MN5, and MN9.

The current paths of the transistors MN1, MN5, and MN9 are sequentially formed in series between the output terminal REF0 and ground. The gate of the transistor MN1 is controlled to the corresponding detection signal HV1, the gate of the transistor MN5 is connected to its drain, and the gate of the transistor MN9 is the signal CSP output from the CS buffer 140. Is controlled.

According to this circuit configuration, the NMOS transistors MN1-(MN4) of each of the strings S1, S2, S3 and S4 according to the signals HVi which are sequentially activated as the power supply voltage increases. ) Is turned on. At this time, since the signal CSP is at a high level while the chip is activated, the strings may be changed because the detection signals HV1 and HV2 are activated according to the detection signal activated, that is, when the power supply voltage is higher than 3.4V. The level of the output terminal REF0 is lowered through the transistors constituting S1 and S2.

The change in the voltage REF0 according to the change in the power supply voltage is shown in FIG. 7. Here, the transistors MN9, MN10, MN11, and MN12 are for preventing the current flowing in the chip standby state, in particular, the CMOS ISB1 from being increased. Accordingly, the level of the signal REFSA generated from the sense amplification reference signal generation circuit 160 is lowered as the level of the reference voltage REF0 is lowered. As a result, it is possible to reduce the current consumption of the main sense amplifier circuit 180 which accounts for a large proportion of the operating current consumed during the read operation.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, as the power supply voltage increases, the output level of the band gap reference circuit is lowered, thereby lowering the output level of circuits following the output level of the band gap reference circuit. Therefore, the current consumed by the main sense amplifier circuit can be reduced, and as a result, the overall consumption current can be reduced.

1 is a circuit diagram showing a main sense amplifier circuit of a static random access memory device;

2 is a circuit diagram showing a band gap reference circuit according to the prior art;

3 is a view showing output characteristics of a band gap reference circuit that varies according to the level of an external power supply voltage;

4 is a block diagram showing a configuration of a static random access memory device according to the present invention;

5 is a diagram illustrating output characteristics of a level detection circuit according to a level change of an external power supply voltage;

6 is a circuit diagram illustrating a band gap reference circuit according to a preferred embodiment of the present invention;

7 is a view showing output characteristics of a band gap reference circuit according to the present invention;

* Explanation of symbols on the main parts of the drawings

100 level detection circuit 120 band gap reference circuit

140: CS buffer 160: detection amplification reference signal generation circuit

180: main sense amplifier circuit

Claims (4)

A semiconductor memory device having an array of memory cells for storing information, said semiconductor device comprising: A sense amplifying circuit coupled to the array and configured to sense and amplify data of an addressed memory cell among the memory cells in response to a sense amplification reference signal and a sense amplification activation signal; A voltage detection circuit which receives an external power supply voltage and detects when the external power supply voltage becomes higher than a reference level and sequentially generates detection signals at regular intervals as the external power supply voltage gradually increases; A band gap reference circuit that receives the external power supply voltage and generates a reference voltage in response to the detection signals when the chip is activated; A sense amplification reference signal generation circuit that receives the reference voltage and generates the sense amplification reference signal; The band gap reference circuit generates the reference voltage which is sequentially lowered according to the detection signals that are sequentially generated when the external power supply voltage is increased, thereby generating the reference signal generated from the sense amplification reference signal generation circuit. A semiconductor memory device, characterized in that the level is lowered. The method of claim 1, And the band gap reference circuit is connected to its output terminal and includes discharge means for lowering the potential of the output terminal in response to the detection signals. The method of claim 2, And the discharging means comprises a plurality of first group of NMOS transistors connected between the output terminal and ground, the gates of the transistors being controlled by corresponding detection signals. The method of claim 3, wherein The discharging means is connected between the NMOS transistors of the second group and the second group of NMOS transistors, operating as a diode, respectively connected between the NMOS transistors of the first group and the ground; And a third group of NMOS transistors controlled by the chip activation signal controlled by the chip activation signal to reduce current consumed in the standby state.

Images