KR100493000B1 - Phase-locked loop with stabilization function for error components of optical system and its stabilization method - Google Patents

Abstract

A phase locked loop having a stabilization function for error components in an optical system and a stabilization method thereof are disclosed. A phase locked loop having a stabilization function for an error component in an optical system according to the present invention compares the frequencies of E.F.M data and N-divided oscillation signals applied from an external slice circuit, and compares the results. In a phase locked loop having a frequency detecting means for outputting as an up / down signal, phase detection means for comparing the phase of the E.M.data and the reference clock signal and outputting the compared result as an up / down signal, Adjusts the amount of current in response to the up / down signal output from the frequency detecting means or the phase detecting means, generates a control voltage of direct current by low-pass filtering the adjusted result, and turns on the current control in response to a predetermined constant speed lock signal. Charge pump / low pass filter on / off, generate oscillation signal with frequency corresponding to control voltage, and in response to constant speed lock signal Voltage controlled oscillation means for fixing the oscillation signal, first division means for dividing the oscillation signal by N (> 0), outputting the N divided signal, and M (> 0) division of the N divided signal and a reference clock signal It characterized by comprising a second dispensing means for generating a.

Description

Phase-locked loop with stabilization against error component of optical system and its stabilization method

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to optical systems such as Compact Disc Players (CDPs) and Digital Versatile Disk Players (DVDPs). A phase locked loop having a stabilization function for error components of an optical system that operates stably against error components such as defects and glitches, and a stabilization method thereof.

Generally, a phase locked loop (PLL) is essential when playing a compact disc (CD), a digital multifunction disc (DVD), or a video compact disc. In order to increase the response speed of the optical system, a reproduction clock signal for variably reproducing the EFM modulated signal according to the frequency change is required, and a phase locked loop is generated to generate such a reproduction clock signal. In other words, in order to slice the voltage / current-converted EFM modulation data through a high frequency amplifier and convert it into a signal that can be interpreted by a digital signal processor, a phase locked loop must be used to synchronize frequency and phase. Normal EFM data consists of 3T to 11T (CD) or 14T (DVD) based on the clock component (T), and the PLL is responsible for generating this clock component (T). Thus, an important measure in evaluating the performance of a PLL depends on how fast and stable T is supplied.

Currently, all disc-related systems, except for some CDP and video-CD players, employ variable playback. In other words, unlike the method in which the spindle motor rotating the disk enters the normal speed and starts demodulation after the data rate becomes constant, the variable reproducing method uses the spindle motor as long as the system allows the data to be read. Play unconditionally regardless of speed. Determining whether this data is readable is the role of the PLL, and the performance of the PLL is directly related to the performance of the system. In reality, in evaluating optical systems such as CDP and DVDP, simple readability, that is, simple disc playback capability, is considered to be very important, rather than the enhancement of the function and performance of the system.

1 is a schematic block diagram illustrating a PLL of a conventional optical system, wherein a frequency detector 10, a phase detector 11, a charge pump / low pass filter 12, a voltage controlled oscillator (VCO) 13), the first divider 14 and the second divider (15).

The frequency detector 10 shown in FIG. 1 compares the sliced EFM data with the N-divided VCO oscillation signal, and outputs the up / down signal (UP / DN) corresponding to the compared frequency difference. The phase detector 11 phase compares the sliced EFM data with the reference clock signal PLCK and outputs the compared result as an up / down signal UP / DN corresponding to the phase difference. The charge pump / low pass filter 12 sources or sinks a predetermined current in response to an applied up / down signal UP / DN, and low pass filters the result to generate a control voltage of direct current. do. The VCO 13 generates an oscillation signal having a frequency corresponding to the control voltage. The first divider 14 divides the oscillation signal output from the VCO 13 by N, and applies the N-divided signal to the frequency detector 10. The second divider 15 divides the N divided oscillation signals by M to generate a reference clock signal PLCK. In addition, the reference clock signal PLCK is applied to the phase detector 110 and compared with the sliced EFM data.

Actual discs generally have nonuniformities due to manufacturing process inhomogeneities and handling carelessness. That is, the length of every pit of the disk should be an integer multiple of the period T of the clock signal output from the VCO of the PLL, which actually has some errors due to lack of uniformity of the etching process. In addition, scratches, fingerprints, and the like on the surface of the disk caused by careless handling act as a large number of error elements in playing the disk.

Therefore, the stability of the PLL, which first processes the data stored on the disk in the optical system, is the stability of the system. In terms of stability, the best readability can be obtained depending on how quickly the above-mentioned problems of the disk are ignored. For example, an error component that cannot be followed by the phase detector 11, such as a surface defect or fingerprint, will break the locked state of the PLL, but ideally recovered during subsequent normal operation, the best readability is obtained. Can be. However, the error in the pit length due to the nonuniformity in the disk manufacturing process can be largely controlled by the filtering characteristics of the PLL.

2 (a) and 2 (b) are waveform diagrams for explaining data reading errors due to general error pits, where 2 (a) shows EFM data in a normal case, and 2 (b) shows nonuniform feet. Shows EFM data.

That is, it is assumed that ΔT shown in FIG. The relation between ΔT and normal EFM data and read EFM data is expressed as follows.

Here, n represents 3, 4, 5,-9, 11 for CD, 3, 4, 5, 10, 14 for DVD, and T _EFM denotes the period of read EFM data ( T), and T _NORMAL represents the period T of normal EFM data. T denotes one period of the clock signal PLCK in the PLL. SIGN represents a sign. When n is even, SIGN (n) becomes 1, and when n is odd, SIGN (n) becomes -1.

That is, when an error pit is detected on a disk that is normally driving or when there is a scratch on the surface, the high frequency signal RF input to the slicer circuit has an abnormal period or disappears. When an error pit is detected by generating a pit length longer or shorter than actually in the pit manufacturing process, the clock component T of the EFM data applied to the PLL is misinterpreted and the frequency detector 10 of the PLL is operated. Accordingly, the charge pump / low pass filter 12 operates in accordance with the frequency comparison result of the frequency detector 10, and changes the control voltage. As a result, when an error pit is detected, there is a problem that the PLL stops phase alignment and performs frequency alignment to wait for the PLL to lock again.

In addition to the error pits of the disk, the above-mentioned disk defects may be mentioned as an error factor that may cause a problem in stabilization of the PLL. That is, when a defect is generated in the disk and the high frequency signal RF is damaged, the amplitude detection unit generates a high level defect detection signal DFCT when the amplitude of the output RF signal does not exceed a predetermined level. . Conventionally, the operation of the PLL is unconditionally held during this defect period. However, the defect detection signal DFCT is a signal that is determined only by the output level of the high frequency signal RF. Even when it is determined that the actual defect is completed, the high frequency signal RF remains different from the normal signal for a period of time. do. That is, when the PLL is normally operated again depending on the defect detection signal DFCT, an error component is introduced, and the PLL spends time to pull back again (PULL-IN: frequency introduction) in response to the error component. Therefore, the PLL needs to temporarily suspend normal operation until a stable high frequency signal RF is output.

3 (a) and 3 (b) are waveform diagrams for explaining the output signal when a defect occurs, where 3 (a) shows a high frequency signal RF applied from an optical pickup, and 3 (b) shows a The defect detection signal DFCT generated by the defect detection unit (not shown) is shown.

That is, even when the defect is terminated and the defect detection signal DFCT output from the defect detection unit (not shown) is at a low level, the high frequency signal RF shown in FIG. 3 (a) and the EFM signal sliced by the slice circuit are shown. Has a predetermined transient period until it normally recovers. Here, reference numeral 31 in FIG. 3 (a) denotes a section in which a normal RF signal is output, 32 denotes a section in which a defect occurs and an RF signal disappears, and reference numerals 34a and 34b in FIG. An RF signal not detected by the defect detection signal DFCT is distorted. After the defect detection signal DFCT becomes low level, an error occurs in the frequency detector 10 for a predetermined time until the RF signal and the sliced EFM signal are restored to normal, thereby changing the VCO control voltage. Even if a normal signal is input, it has to enter the PULL-IN process again, which causes considerable time loss. As a result, errors within the phase synchronization range (1 BEAT NOTE) of the phase detector 11 can be controlled by the PLL, but if the frequency detector 10 is operated sensitively to errors exceeding this, the system stability will be degraded. In other words, there is a problem that the video or audio data to be reproduced is broken.

In addition to the error pitting and defect of the disk, an error factor that may cause a problem in stabilization of the PLL may include a glitch component due to comparating noise of a slice circuit and an inflow of error data. Can be. In general, an EFM slice circuit zero-crosses a high frequency signal (RF) with a reference signal to generate a high or low level signal. Normal data flow is maintained when driving a normal disc, but error data may be introduced when jumping between tracks, when defects or scratches occur, or when the disc is stopped. In particular, all the EFM data generated when the disk is completely stopped is error data, which is the main cause of the PLL malfunctioning.

That is, the only signal applied to the PLL is the EFM data obtained by slicing the RF signal, which may cause various other problems when an error occurs in the EFM data. However, in addition to the problem outside the circuit, there is also a problem of the slice circuit itself. For example, EFM data may still be output in a disk stop situation where no RF signal is generated. This is because the RF signal is not present because there is no offset between the inputs of two + and-amplifiers in the comparator circuit inside the slice circuit. Even if it is not applied, noise is compared to output abnormal EFM data. Therefore, such abnormal EFM data causes the PLL to malfunction, and the noise caused by the comparator in the slicer circuit is always caused during normal driving as well as the disk stop situation due to the characteristics of the analog slice circuit. Such noise causes slippage (SIP) in the stable phase locking of the PLL, resulting in the loss of data at that moment.

SUMMARY OF THE INVENTION The first technical problem to be solved by the present invention is to provide a phase locked loop having a stabilization function for an error component of an optical system that can stably control its operation by using a fixed speed lock signal when detecting a disc error pit. It is.

It is a second technical object of the present invention to provide a stabilization method performed in the phase locked loop.

A third technical problem to be achieved by the present invention is to provide a phase locked loop that can stably control its operation by using a PLL hold signal when a disc defect occurs.

A fourth technical object of the present invention is to provide a stabilization method performed in the phase locked loop.

The fifth technical problem to be achieved by the present invention is to provide a phase locked loop which can stably control its operation upon error data inflow by adding an error data removal circuit.

The sixth technical problem to be solved by the present invention is to provide a stabilization method performed in the phase locked loop.

In order to achieve the first task, a phase locked loop having a stabilization function for an error component according to the present invention compares the frequency of E.F.M data applied from an external slice circuit with an N-divided oscillation signal, Frequency synchronization means for outputting the compared result as an up / down signal; phase synchronization with phase detection means for comparing the phase of the E.F.M data and the reference clock signal and outputting the compared result as an up / down signal. In the loop, the amount of current is adjusted in response to the up / down signal output from the frequency detecting means or the phase detecting means, the low pass filtering of the adjusted result is generated to generate a control voltage of direct current, and in response to a predetermined constant speed lock signal. Charge pump / low pass filter to turn current regulation on / off, generate oscillation signal with frequency corresponding to control voltage, A voltage-controlled oscillation means for fixing the oscillation signal in response, N (> 0) division of the oscillation signal, first division means for outputting the N division signal, and M (> 0) division of the N division signal by reference. It is preferable to comprise a second division means for generating a clock signal.

In order to achieve the second task, the stabilization method of the phase-locked loop according to the present invention includes an internal charge pump / low pass filter in response to a fixed speed lock signal applied from an external fixed speed control unit at the time of detecting an error pit of a disk. A method of stabilizing a phase locked loop for fixing an oscillation signal of a voltage controlled oscillation means by turning on / off current control in a phase, the phase locked loop being pulled in to generate a frame synchronization confirmation signal in an external digital signal processor, frame synchronization Determining whether the confirmation signal has been maintained for a predetermined time, if the frame synchronization confirmation signal has been maintained for a predetermined time, generating a fixed speed lock signal, holding frequency detection in response to the fixed speed lock signal, and oscillation of the voltage controlled oscillation means Fixing the frequency, the frame synchronization confirmation signal is maintained for a predetermined time Otherwise, releasing the fixed speed lock signal, and performing frequency detection after the fixed speed lock signal is released, and generating an oscillation frequency of the voltage controlled oscillation means in response to the detected frequency error. desirable.

In order to achieve the third technical problem, a phase locked loop having a stabilization function for an error component according to the present invention compares the frequency of E.F.M data applied from an external slice circuit with an N-divided oscillation signal. A phase detecting means for outputting the compared result as an up / down signal, and a phase detecting means for comparing the phase of the E.M. data and the reference clock signal and outputting the compared result as an up / down signal. In the synchronous loop, a phase locked loop hold for holding frequency detection and phase detection by generating a phase locked loop hold signal in response to a predetermined defect detection signal, and releasing the hold state after a predetermined time after the completion of the defect detection signal. The control means adjusts the amount of current in response to the up / down signals and generates a control voltage of direct current by low-pass filtering the result of the current regulation. A charge pump / low pass filter that turns current regulation on / off in response to the phase locked loop hold signal, generates an oscillation signal having a frequency corresponding to the control voltage, and locks the oscillating signal in response to the phase locked loop hold signal. Preferably, the voltage controlled oscillation means comprises: N division of the oscillation signal, first division means for outputting the N divided signal, and second division means for M division of the N divided signal to generate a reference clock signal. .

In order to achieve the fourth task, the stabilization method of the phase locked loop according to the present invention comprises the oscillation signal of the voltage controlled oscillation means by turning on / off current regulation in an internal charge pump / low pass filter when a disc defect occurs. A method of stabilizing a phase locked loop for fixing a phase, the method comprising: determining whether a defect has occurred; (a) generating a phase locked loop hold signal and fixing an oscillation signal of a voltage controlled oscillation means if a defect has occurred; (b) Determining whether the defect is finished, and if the defect is not finished, returning to step (a), and (c) If the defect is finished in step (b), maintain the phase locked loop hold signal. Counting the E.F.M data, (d) determining whether the counted value exceeds a predetermined number of frames, and if the predetermined number exceeds the predetermined number of frames, the phase synchronization is performed. Releasing the loop hold signal, generating an oscillation signal of the voltage controlled oscillation means corresponding to the frequency and phase difference after the step (d), and returning to the step (c) if the counted value does not exceed a predetermined number It is preferably composed of a step.

In order to achieve the fifth task, a phase locked loop having a stabilization function for an error component according to the present invention compares the frequency of E.M.data applied from an external slice circuit with a frequency of an N divided oscillation signal. And frequency detection means for outputting the compared result as an up / down signal, detecting whether the frequencies of the E.M data and the N-divided oscillation signal are locked, and outputting the detected result as a phase locked loop lock signal. A phase locked loop lock detecting means for removing the error component of the E.F. and M data in response to the phase locked loop lock signal, and outputting the E.F.M data from which the error component has been removed. Phase detection means and frequency detection means for comparing the phases of the removed E.M data with the reference clock signal and outputting the compared result as an up / down signal. Or a charge pump / low pass filter that adjusts the amount of current in response to the up / down signal output from the phase detection means, filters the adjusted result to generate a control voltage of direct current, and an oscillation signal having a frequency corresponding to the control voltage. A voltage-controlled oscillation means for generating an N, an first division means for dividing an oscillation signal, and outputting an N-divided signal, and a second division means for dividing the N-divided signal by M to generate a reference clock signal. desirable.

In order to achieve the sixth task, the method of stabilizing a phase locked loop according to the present invention includes (a) applying E.F.M data from an external slice circuit, determining whether the phase locked loop is locked, If it is not locked, outputting the E.F.M data as it is, returning to step (a), (b) if the phase lock loop is locked, determining whether the applied data is less than 3T, (c) If the E.M data is less than 3T, it is determined as error data, and if the error is eliminated, outputting the E.M data, (d) If the approved E.M data is 3T or more and 11T or 14T or less, Determining the normal data and outputting the applied E.M. data, and performing phase detection and frequency detection based on the E.F.M data output in step (c) or (d). It is preferred to be configured.

Hereinafter, a phase locked loop having a stabilization function for error pits of a disk and a stabilization method thereof according to the present invention will be described as follows.

4 is a schematic block diagram illustrating a phase locked loop having a stabilization function for an error pit according to the present invention, which includes a frequency detector 400, a phase detector 410, a charge pump / low pass filter 420, A VCO 430, a first divider 440, a second divider 450, and a constant linear velocity controller (CLV) controller 460 are included.

The frequency detector 400 shown in FIG. 4 compares the EFM data applied from the slicer circuit (not shown) with the frequency of the N-divided VCO oscillation signal, and compares the result as an up / down signal (UP / DN). Output The phase detector 410 compares the phases of the sliced EFM data with the N-divided VCO oscillation signal, M, that is, the reference clock signal PLCK, and compares the result as an up / down signal UP / DN. Output The charge pump / low pass filter 420 adjusts the amount of current by sourcing / sinking the current in response to the up / down signals UP / DN output from the frequency detector 400 and the phase detector 410, and filters the results. To generate a control voltage of direct current. In addition, it is controlled to turn on / off current sourcing / sinking in response to the CLV lock signal CLV_LOCK output from the CLV control unit 460. The CLV controller 460 outputs a high or low level CLV lock signal CLV_LOCK in response to a frame synchronization check signal (GFS) output from a digital signal processor (DSP) (not shown). do. VCO 430 generates an oscillation signal having a frequency corresponding to the control voltage output from charge pump / low pass filter 420. The first divider 440 divides the VCO oscillation signal by N and outputs the N-divided result. The second divider 450 divides the N-divided VCO oscillation signal into M to generate the reference clock signal PLCK. Here, the division ratios N and M are set at the microcomputer.

FIG. 5 is a circuit diagram for describing the charge pump / low pass filter 420 of the phase locked loop shown in FIG. 4, which is composed of a control signal input 500, a charge pump 520, and a low pass filter 540. Here, the control signal input unit 500 is composed of the end gates (502, 504), the charge pump 520 is a first current source (I52) to function as a current source and a second current source (I53) to function as a current sink. ) And switches SW51 and SW52, the low pass filter 540 is implemented with a capacitor C54.

The control signal input unit 500 illustrated in FIG. 5 controls the flow of current by inputting an up / down signal UP / DN and a CLV lock signal CLV_LOCK output from the frequency detector 400 or the phase detector 410. To generate a switch control signal. That is, the AND gate 502 has a CLV lock signal inverted from the up signal UP. ) Is multiplied and output as a control signal of the switch SW51. The AND gate 504 is a CLV lock signal inverted by the down signal DN. ) Is multiplied and output as a control signal of the switch SW52. The switch SW51 of the charge pump 520 controls the frequency of the VCO oscillation signal to increase by charging the low pass filter 540 implemented by the capacitor C54 to increase the VCO control voltage, and the switch SW52. Is controlled to reduce the frequency of the VCO oscillation signal by discharging the charge charged in the capacitor C54 to lower the VCO control voltage. That is, when the switch SW51 is turned on in accordance with the output of the AND gate 502, a predetermined current is sourced from the first current source I52 to charge the capacitor C54 so that the output control voltage is increased to increase the control voltage. ) Off turns the output into a high impedance state. In addition, when the switch SW52 is turned on in accordance with the output of the AND gate 504, the predetermined current is sinked to the ground GND through the second current source I52 to discharge the current charged in the capacitor C54 and output the same. The control voltage is lowered and the output is made high when the switch SW52 is turned off. In this case, when the switch SW51 or the switch SW52 is forcibly turned off, the CLV lock signal CLV_LOCK is at a high level, and at that moment, the output of the frequency detector 400 is in a high impedance state and the frequency is changed. Prevents detector 400 from intervening unnecessarily. Therefore, the frequency of the VCO oscillation signal output from the VCO 430 is fixed and only controls the PLL by the phase detector 410.

That is, the phase locked loop shown in FIG. 4 can stabilize the operation of the phase locked loop by holding the frequency detection at the time of detecting the error pit of the disc using the fixed speed lock signal CLV_LOCK applied from the CLV controller 460. There is a characteristic.

FIG. 6 is a flowchart for describing a stabilization method of the phase locked loop shown in FIG. 4, in which a PLL is pulled in to generate a frame synchronization confirmation signal GFS (step 60), and a frame synchronization confirmation signal GFS. After a predetermined time has elapsed, generate a CLV lock signal CLV_LOCK to hold the frequency detection in the PLL and fix the VCO oscillation frequency (steps 62 to 65), and the frame synchronization confirmation signal GFS is a predetermined time. If not maintained, the method further comprises releasing the CLV lock signal CLV_LOCK and performing frequency detection to generate a VCO oscillation frequency corresponding to the frequency error (steps 67 to 69).

4, 5 and 6 will be described in detail with respect to the operation and stabilization method of a phase locked loop having a stabilization function for a disk error pit according to the present invention.

First, when the disk rotation speed is monotonically increased or monotonically decreased and the PLL is pulled in and the data can be read while the normal speed is reached, the DSP (not shown) determines that the data is ready to be read, A frame synchronization confirmation signal GFS is generated (step 60). At this time, the CLV control unit 460 determines whether the input high level frame synchronization confirmation signal GFS has been maintained for a predetermined time or more (step 62). If the GFS signal has been maintained for a predetermined time or more, the CLV controller 460 generates a high level CLV lock signal CLV_LOCK (step 63). Therefore, the high level of the CLV lock signal CLV_LOCK indicates that it is no longer necessary to detect the frequency in the PLL, so that the PLL of the frequency detector 400 at the time when the CLV lock signal CLV_LOCK becomes the high level. The output can be held to prevent the frequency detector 400 from intervening unnecessarily. In more detail, when the CLV lock signal CLV_LOCK becomes high level, the inverted CLV lock signal input to the AND gate 502 or the AND gate 504 of the control signal input unit 500 ( ) Becomes a low level, so the output of the AND gate 502 or 504 becomes a low level, regardless of the state of the up / down signal UP / DN output from the frequency detector 400, the switches SW51 and SW52. Is off. As a result, the output of the charge pump 520 is in a high impedance state, and the flow of current is interrupted. Accordingly, the PLL holds the frequency detection performed in the frequency detector 400 and fixes the current VCO oscillation frequency (step 65).

On the other hand, if the high level frame synchronizing confirmation signal GFS is not maintained for a predetermined time and is not applied continuously, in step 62, the CLV lock signal CLV_LOCK is released to reach a low level (step 67). In this case, in order for the CLV lock signal CLV_LOCK to go back to the low level, the GFS signal must not be continuously detected a predetermined number of times, and errors that are determined to be very large errors, such as a disk defect, fingerprint, or scratch, may occur. In this case, the system can be stabilized using the CLV lock signal CLV_LOCK. That is, when the CLV lock signal CLV_LOCK is at the low level, the inverted CLV lock signal applied to the AND gate 502 of the control signal input unit 500 shown in FIG. ) Becomes the high level. Therefore, the PLL operates normally and operates the charge pump / low pass filter 420 in response to the frequency error output from the frequency detector 400, that is, the up / down signal UP / DN, and corresponds to the filtered control voltage. In operation 69, an oscillation frequency is generated. For example, if the up signal UP is generated corresponding to the frequency error output from the frequency detector 400, the output of the AND gate 502 becomes a high level, and thus, the switch SW51 of the charge pump 520 ) Is turned on to charge capacitor C54 with current flowing from current source I52. Therefore, the control voltage output through the output terminal OUT is high, and accordingly the frequency of the oscillation signal output from the VCO 430 is high.

In addition, if the down signal DN is generated corresponding to the frequency error output from the frequency detector 400, a high level signal is output from the AND gate 504 of the control signal input unit 500 to turn on the switch SW52. Let's do it. Therefore, the predetermined current is sinked through the current source I53, and the electric charge charged in the capacitor C54 is discharged to lower the control voltage. Therefore, the frequency of the oscillation signal output from the VCO 430 is lowered.

The stabilization method through the above-described process can eliminate not only non-uniformity occurring in the pit, but also change in data due to variation in CLV control or constant angular velocity (CAV) control.

Hereinafter, a phase locked loop and a stabilization method having a stabilization function when a defect occurs in an optical system according to the present invention will be described with reference to the accompanying drawings.

7 is a schematic block diagram illustrating a phase locked loop having a stabilization function when a defect occurs in accordance with the present invention, and includes a frequency detector 700, a phase detector 710, a charge pump / low pass filter 720, and a VCO. 730, a first divider 740, a second divider 750, and a PLL hold control unit 760, where the PLL hold control unit 760 includes a PLL lock signal generation unit 762 and a frame. It consists of a counter 764.

The frequency detector 700 shown in FIG. 7 compares the frequencies of the EFM data applied from the slicer circuit (not shown) and the N-divided VCO oscillation signal PLCK, and up / downs the comparison results. Output as. The phase detector 710 compares the phases of a signal obtained by M-dividing the sliced EFM data with the N-divided VCO oscillation signal, that is, the reference clock signal PLCK, and compares the result as an up / down signal UP / DN. Output The PLL hold control unit 760 generates the PLL hold signal PLL_HOLD in response to the defect detection signal DFCT, and releases the PLL hold signal PLL_HOLD after a predetermined time after the defect detection signal DFCT ends. That is, the frame counter 764 counts the rising or falling edge of the EFM data in response to the defect detection signal DFCT applied from an external defect detection unit (not shown), and the counted value is 5 or 10 frames. The set signal SET is output to the PLL lock signal generator 762. The PLL lock signal generator 762 generates a PLL lock signal PLL_LOCK in response to the defect detection signal DFCT, and generates a PLL lock signal PLL_LOCK in response to the set signal SET output from the frame counter 764. ) To generate a PLL hold signal (PLL_HOLD) for holding the PLL. The charge pump / low pass filter 720 adjusts the amount of current by sourcing / sinking the current in response to the up / down signals UP / DN output from the frequency detector 700 and the phase detector 710, and filters the results. To generate a control voltage of direct current. In addition, in response to the PLL hold signal PLL_HOLD output from the PLL hold control unit 760, it is controlled to turn on / off sourcing / sinking of the current. VCO 730 generates an oscillation signal having a frequency corresponding to the control voltage output from charge pump / low pass filter 720. The first divider 740 divides the VCO oscillation signal by N and outputs the N-divided result. The second divider 750 divides the N-divided VCO oscillation signal into M to generate the reference clock signal PLCK.

FIG. 8 is a circuit diagram illustrating the charge pump / low pass filter 720 of the PLL shown in FIG. 7, and includes a control signal input 800, a charge pump 820, and a low pass filter 840. In one embodiment, the control signal input unit 800 includes end gates 802 and 804, the charge pump 820 includes a first current source I81 serving as a current source, and a second current source I82 serving as a current sink. And switches SW82 and SW84, and the low pass filter 840 is implemented with a capacitor C84.

The AND gate 802 of the control signal input unit 800 shown in FIG. 8 is an up signal UP output from the frequency detector 700 or the phase detector 710 and a PLL hold signal output from the PLL hold control unit 760. Inverted signal of (PLL_HOLD) ( ), And the result of the AND is output as a switch (SW82) control signal. In addition, the AND gate 804 is a PLL hold signal (inverted from the down signal DN output from the frequency detector 700 or the phase detector 710). ) And the result of the AND is output as the switch SW83 control signal. The current source I81 and the current source I82 of the charge pump 820 source or sink current according to the on / off state of the switch SW82 or the switch SW83, respectively, and filter the result to generate a control voltage. .

9 (a) to 9 (c) are waveform diagrams for explaining signals of the phase locked loop shown in FIG. 7 at the time of defect generation, and FIG. 9 (a) shows an RF signal applied from an optical pickup, 9 (b) indicates the defect detection signal DFCT output from the defect detection unit, and 9 (c) indicates the PLL hold signal PLL_HOLD.

Referring to FIG. 9, reference numeral 91 of 9 (a) denotes a section in which a normal RF signal is output, 93 denotes a section in which a defect occurs and an RF signal disappears, and 95a and 95b of 9 (b) indicate a decode. An RF signal section not detected by the defect is shown, and reference numeral 98 in 9 (c) indicates a predetermined time T _HOLD at which the PLL is held after the completion of the defect. Here, T _HOLD is determined at the microcomputer, this time While not intervening the frequency detector 700 of the PLL. In other words, if the PLL is held, the DSP which applies and processes the output of the PLL (PLCK) increases the error margin in the ECC circuit, which is an internal error correction block (ECC), thereby bringing about systemic stability. .

FIG. 10 is a flowchart for describing a stabilization method performed in the phase-lock loop shown in FIG. 7. The method of determining a defect has occurred, and if so, generates a PLL hold signal to fix the VCO oscillation signal. Step 101-102), it is determined whether the defect has ended, and if it is finished, maintaining the PLL hold signal and counting the EFM data (step 103-104), and the value counting the EFM data exceeds a predetermined number of frames. If it is not exceeded, the PLL hold signal is maintained and counting EFM data is continued (step 105). If the predetermined number of frames is exceeded, the PLL hold signal is released, and the VCO oscillates corresponding to the frequency and phase difference. Generating signals (steps 107 to 108).

7, 8, 9 and 10 will be described in detail with respect to the operation and stabilization method of the phase locked loop having a stabilization function when the defect occurs in accordance with the present invention.

First, the defect detection unit (not shown) outside the PLL bottom-holds the RF signal shown in FIG. 9 (a) applied from the optical pickup to generate the defect detection signal DFCT shown in FIG. 9 (b). It is determined whether a defect has occurred (step 101). Here, when the defect occurs, the starting point of the defect detection signal DFCT is not important because it is possible to output the EFM data at least during the defect detection interval. That is, even if the generation of the defect detection signal DFCT is delayed slightly, the frequency detector 710 of the PLL can be prevented from intervening for a predetermined period of time by using the CLV lock signal CLV_LOCK. However, when the defect occurs for a long time, the CLV lock signal CLV_LOCK is no longer generated, and thus the intervention of the frequency detector 710 cannot be suppressed. In the case of DVDs with 1x speed, the time that ECC can compensate for is limited, and the wasted time will eventually degrade the system's performance. Therefore, in the present invention, the rising or falling edge of the EFM data at the time of notifying the end of the defect detection signal DFCT output from the defect detection unit, that is, the moment when the defect detection signal DFCT changes from a high level to a low level. Is detected to generate a PLL hold signal PLL_HOLD extending 5 or 10 frames further from the end point of the defect detection signal DFCT.

That is, when it is determined that the defect has occurred in step 101, the PLL hold control unit 760 shown in FIG. 7 generates the PLL hold signal PLL_HOLD to fix the VCO oscillation signal at the time when the defect starts. Step 102). That is, the PLL lock signal generation unit 762 of the PLL hold control unit 760 generates a high level PLL lock signal PLL_LOCK when the EFM data and the reference clock signal PLCK are locked, and is applied from the defect detection unit. When the defect detection signal DFCT becomes the high level, the high level PLL hold signal PLL_HOLD is generated to hold the frequency and phase detection operation of the PLL. The PLL hold signal PLL_HOLD output from the PLL hold control unit 760 is input to the charge pump / low pass filter 720 to block current sourcing / sinking and thus to fix the output control voltage constantly. The AND gate 802 of the charge pump / low pass filter 720 has an inverted PLL hold signal having a low level. ) Generates a low level output signal, and since the switch SW82 is turned off, current sourcing does not occur and the output becomes a high impedance state. Similarly, since the switch SW83 is also turned off by the output of the AND gate 804, no current sinking occurs, and the control voltage output through the low pass filter 840 does not change, so the oscillation signal output from the VCO 730 is constant. Is fixed. In addition, the PLL hold control unit 760 determines whether the defect has ended (step 103). When the defect is detected in step 103 and the defect detection signal DFCT becomes low, the PLL hold control unit 760 maintains the PLL hold signal PLL_HOLD and counts the EFM data in the frame counter 764. Step 104). If the defect detection signal DFCT is not finished yet and maintains a high level, the process returns to step 102. After step 104, it is determined whether the value counted in the frame counter 764 has exceeded a predetermined number, preferably 5 or 10 frames (step 105). If not, the process returns to step 104 and continues high. Hold the PLL hold signal at the level and lock the VCO oscillation signal. In addition, if the value counted in step 105 exceeds 5 or 10 frames, the PLL hold control unit 760 releases the PLL hold signal (step 107). That is, at the time when the defect detection signal DFCT ends, the PLL hold control unit 760 extends the PLL lock signal PLL_LOCK by 5 or 10 frames to generate the PLL hold signal PLL_HOLD. If the frame is exceeded, the PLL hold signal PLL_HOLD shown in FIG. 9C is released (step 107). Here, if the number of rising and falling edges of the EFM data is 512, it is regarded as 1 frame, and whether to extend 5 frames or 10 frames is determined according to the asymmetry compensation filter characteristic of the slice circuit. If the cutoff frequency of the filter is high, it is sufficient to set 5 frames since the speed of restoring the normal slice level after the completion of the defect detection signal DFCT is sufficient. However, if the cutoff frequency is low, after the completion of the defect detection signal DFCT, It is preferable to set to 10 frames because the speed of restoring the normal slice level is slow. However, adjusting the number of frames by increasing the cutoff frequency of the filter has a problem that it follows the slice level against the pinhole (PIN-HOLE) phenomenon in which the EFM data disappears instantaneously.

If the PLL hold signal PLL_HOLD is released in step 107, the frequency detector 700 and the phase detector 710 of the PLL generate an up / down (UP / DN) corresponding to the frequency and the phase difference. Accordingly, the charge pump / low pass filter 720 sources / sinks the current to generate a control voltage corresponding to the frequency or phase difference, and the VCO 730 generates an oscillation signal corresponding to the control voltage (step 108). ). Here, the oscillation signal output from the VCO 730 is divided at a predetermined rate in the first divider 740 and the second divider 750 to generate the reference clock signal PLCK.

If a defect occurs in the disk through the above-described process, a stable operation can be performed by holding the PLL for a predetermined time after the completion of the defect.

Hereinafter, a phase locked loop and a stabilization method having a stabilization function for error data according to the present invention will be described with reference to the accompanying drawings.

11 is a schematic block diagram illustrating a phase locked loop having a stabilization function for error data according to the present invention, wherein the error data removal unit 100, the PLL lock detection unit 170, the frequency detector 110, and the phase are shown. Detector 120, charge pump / low pass filter 130, VCO 140, first divider 150, and second divider 160.

The frequency detector 110 shown in FIG. 11 compares the frequency of the EFM data applied from the slicer circuit (not shown) with the frequency of the N-divided VCO oscillation signal PLCK and up / downs the result of the comparison (UP / DN). Output as. The error data removal unit 100 removes an error component such as diglych mixed with EFM data applied from a slice circuit (not shown), and outputs EFM data (DEFM) from which the error component has been removed. The phase detector 120 compares the phases of the EFM data (DEFM) from which the error component is removed, the signal obtained by dividing the N-divided VCO oscillation signal, that is, the reference clock signal PLCK, and up / down the comparison result. It outputs as a signal (UP / DN). The charge pump / low pass filter 130 adjusts the amount of current by sourcing / sinking the current in response to the up / down signals UP / DN output from the frequency detector 110 and the phase detector 120, and filters the results. To generate a control voltage of direct current. VCO 140 generates an oscillation signal having a frequency corresponding to the control voltage output from charge pump / low pass filter 130. The first divider 150 divides the VCO oscillation signal by N and outputs the N-divided result. The second divider 160 divides the N divided VCO oscillation signals by M to generate a reference clock signal PLCK. The PLL lock detector 170 inputs the EFM data and the N-divided oscillation signal, detects whether the two signals are locked, and generates a high level PLL lock signal (PLL_LOCK).

FIG. 12 is a detailed circuit diagram illustrating the error data removing unit 100 of the phase locked loop shown in FIG. 11, and includes NAND gates 210 and 220, a flip-flop 200, and a counter 230. Here, flip-flop 200 is composed of inverter 202 and NAND gates 204, 206, 208, and 209, and counter 230 is D flip-flops 232, 234, 236 and inverter 238. It is composed of

The NAND gate 210 shown in FIG. 12 inverts ANDs the PLL lock signal PLL_LOCK and the positive output Q of the counter 230, and inverts the result of the inverted AND product of the NAND gate 204 of the flip-flop 200. To the first input of. In addition, the NAND gate 220 has a PLL lock signal PLL_LOCK and a negative output of the counter 230. ) Is applied to the second input of the NAND gate 208 of the flip-flop 200. The flip-flop 200 inputs EFM data from an external slice circuit, and outputs the applied EFM data as a high or low level signal in response to an output of the NAND gate 210 or the NAND gate 220. The output data is output to the phase detector 120 of the PLL as data (DEFM) from which error components such as diglyc have been removed. The EFM data output from the flip-flop 200 is applied to the counter 230, and the counter 230 is a high or low level of the EFM data in response to the reference clock signal PLCK output from the second divider 160. Count the segments. The counted result, that is, the positive output (Q) and the negative output ( ) Is applied to the first and second inputs of the NAND gate 210 and the NAND gate 220 to be inversely ANDed with the PLL lock signal PLL_LOCK, respectively. Here, if the counted result of the EFM data is less than 3T, the counter 230 does not output the data, but only the data of 3T or more.

13 (a) and 13 (b) are waveform diagrams for explaining input and output signals of the error data removal unit 100 shown in FIG. 12, and FIG. 13 (a) shows a mixture of glitches and abnormal data applied from a slice circuit. EFM data is shown, and 13 (b) shows EFM data (DEFM) from which an error component has been removed. Here, reference numeral 131 in Fig. 13A shows glitch and error data due to comparison noise of the slice circuit. FIG. 14 is a flowchart for describing a stabilization method performed in the phase locked loop shown in FIG. 11. The step of applying EFM data from a slice circuit (step 40), determines whether the PLL is locked, Otherwise, outputting the EFM data as it is (steps 42 to 44). If it is locked, it is determined whether the applied EFM data is less than 3T. If it is less than 3T, it is determined as error data and the EFM data from which the error is removed is output. If it is less than 11T or 14T or less, the method determines phase data and outputs the applied EFM data (steps 46 to 49) and performing phase detection and frequency detection based on the EFM data output in the 48th or 49th steps. (50 steps).

11, 12, 13 and 14 will be described in detail with respect to the operation of the phase locked loop having a stabilization function for the error data and the stabilization method according to the present invention.

The EFM data shown in FIG. 13A which is initially applied by the slice circuit (not shown) is applied to the error data removal unit 100 (step 40). As described above, even during normal driving, the EFM data applied to the phase detector 120 of the PLL may be input by mixing an abnormal component such as GLITCH by an internal comparator when sliced in the slice circuit. The data represented by the glitch component as shown in 131 of FIG. 13 (a) may be actual noise glitches, and the clock component of normal EFM data, i.e., 3T to 11T, when the disc is track jumped during play or the RF signal is distorted by the fingerprint. Alternatively, the error data may be 3T or less, which is different from 3T to 14T. When such error data is input, the phase detector 120 outputs the up signal UP according to the phase comparison result, and the charge pump / low pass filter 130 performs current sourcing to charge the low pass filter. It becomes larger than the amount to discharge, and makes a control voltage high. That is, since the data of the component smaller than the normal EFM data is applied, the PLL operates as described above. Therefore, noise EFM data of 3T or less recorded on the disk can stably operate the PLL by blocking a path flowing into the PLL. At this time, it is determined whether the PLL is in the locked state (step 42), and if it is not locked, the applied EFM data is output as it is (step 44). However, when the frequency of the EFM data and the N-divided oscillation signal coincide with each other, the PLL enters the locked state and the PLL lock signal PLL_LOCK is at a high level. In this case, the error data removal unit 100 applies the glitch component of the applied EFM data. Eliminate error components. That is, the error data removal unit 100 determines whether the component of the EFM data is less than 3T by counting the rising / falling edge of the EFM data to detect whether an error component exists in the applied EFM data (step 46). . If the EFM data is 3T or more and 11T or 14T or less in step 46, it is determined that the normal data is output and the applied EFM data is output to the phase detector 120 (step 49). Accordingly, the phase detector 120 compares the sliced EFM data with the reference clock signal PLCK and generates an up / down signal UP / DN corresponding to the compared phase difference. The generated up / down signal UP / DN is current regulated in the charge pump / low pass filter 130 to generate a control voltage of direct current, and the VCO 140 has an oscillation signal having a frequency corresponding to the applied control voltage. Create

On the other hand, if the EFM data applied to the error data removal unit 100 is determined to be a glitch component or an abnormal component less than 3T, the error data removal unit 100 determines that the data less than 3T is error data and removes the error component. Output the EFM data (step 48). That is, the error data removal unit 100 counts the high level section or the low level section of the EFM data when the PLL lock signal PLL_LOCK is at the high level, that is, when the PLL lock state is locked, and the counted result is less than 3T. It does not output the data because it is regarded as error data such as glitches. At this time, the up / down signals UP / DN output from the phase detector 120 are generated at the rising edge and the falling edge of the applied EFM data, respectively. That is, as shown in FIG. 13B, the up / down signal UP / DN output from the phase detector 120 is changed by the change of the EFM data DEFM from which the error is removed, and thus the charge The amount of current regulated in the pump / low pass filter 130, that is, the amount of sourcing / sinking, is likewise changed. However, due to the generation of the control voltage in accordance with the regulated amount of current, the PLL is subsequently controlled to balance. Of course, if the generated control voltage is not within the 1-bit note (VEAT) of the VCO oscillation signal, that is, within the phase detectable range (-π / 2 to π / 2), the frequency detector 110 must be pulled in again. do. That is, since data having a clock component T smaller than normal EFM data is applied, the PLL may operate as described above, thereby preventing the error component from flowing into the phase detector 120. Accordingly, the phase detector 120 performs phase detection with the reference clock signal PLCK based on the EFM data output in step 48 or 49, and if the control voltage is not within the phase detectable range, the frequency detector ( 100 performs frequency detection (step 50).

Here, since the EFM data of 3T or less is not necessary at all to control the PLL, the above process is not a problem even when the PLL operates in a wide range. In this way, it is possible to stably operate the PLL by eliminating the error upon inflow of error data such as a glitch component and performing phase detection from the error-free data.

According to the present invention, it is possible to eliminate the malfunction of the PLL itself by eliminating not only the disc pit irregularity but also the data change due to the variation of the CLV control or the CAV control, and by holding the PLL for a certain time when the defect occurs, the PLL This stable operation can be performed. In addition, by eliminating error data such as glitch components that are mixed with sliced EFM data, not only a stable PLL can be realized but also it can be applied to a data demodulation circuit related to all CDs or DVDs. In addition, by adding simple circuits for interfacing the PLL with other external circuits, an economical PLL circuit with low power consumption can be realized without significantly affecting the size of the entire circuit.

1 is a schematic block diagram illustrating a phase locked loop of a conventional optical system.

2 (a) and 2 (b) are waveform diagrams for explaining the error of the disk rotational speed due to general error pits.

3 (a) and 3 (b) are waveform diagrams for explaining the output signal at the time of normal defect generation.

4 is a schematic block diagram illustrating a phase locked loop having a stabilization function for error pits of a disc according to the present invention.

FIG. 5 is a circuit diagram illustrating the charge pump / low pass filter of the phase locked loop shown in FIG. 4.

FIG. 6 is a flowchart for describing a stabilization method performed in the phase locked loop shown in FIG. 4.

7 is a schematic block diagram illustrating a phase locked loop having a stabilization function for a defect component according to the present invention.

FIG. 8 is a circuit diagram illustrating the charge pump / low pass filter of the phase locked loop shown in FIG. 7.

9A to 9C are waveform diagrams for describing signals of the phase locked loop shown in FIG. 7 when a defect occurs.

FIG. 10 is a flowchart for describing a stabilization method performed in the phase locked loop shown in FIG. 7.

11 is a schematic block diagram illustrating a phase locked loop having a stabilization function for error data according to the present invention.

FIG. 12 is a detailed circuit diagram illustrating an error data removal unit of the phase locked loop shown in FIG. 11.

13A and 13B are waveform diagrams for explaining input and output signals of the error data removal unit shown in FIG. 12.

FIG. 14 is a flowchart for describing a stabilization method performed in the phase locked loop illustrated in FIG. 11.

Claims (11)

Frequency detection means for comparing the frequency of the E.F.M data applied from an external slice circuit with the N-divided oscillation signal and outputting the compared result as an up / down signal, the E.F.M data and the reference A phase locked loop comprising phase detection means for comparing phases of a clock signal and outputting the compared result as an up / down signal, The amount of current is adjusted in response to the up / down signal output from the frequency detecting means or the phase detecting means, low-pass filtering the adjusted result to generate a control voltage of direct current, and the current in response to a predetermined constant speed lock signal. Charge pump / low pass filter to turn regulation on / off; A voltage controlled oscillation that generates the oscillation signal having a frequency corresponding to the control voltage and fixes the oscillation signal in response to the control voltage held constant when the current regulation is turned off in response to the constant speed lock signal Way; First division means for dividing the oscillation signal by N (> 0) and outputting the N divided signal; And And second dividing means for dividing the N-divided signal by M (> 0) to generate a reference clock signal. The method of claim 1, wherein the charge pump / low pass filter, Control signal input means for logically combining the up / down signal and the inverted signal of the constant speed lock signal, and outputting the logical combined result as a switch control signal; A charge pump for sourcing / sinking a predetermined current corresponding to the up / down signal or stopping the sourcing / sinking of a current in response to the switch control signal; And A low pass filter for filtering the output of the charge pump and outputting the filtered result as the control voltage. Phase synchronization to fix the oscillation signal of the voltage controlled oscillation means by turning on / off current regulation in the internal charge pump / low pass filter in response to a constant speed lock signal applied from an external constant speed control unit upon detecting a fault pit of the disc. In the stabilization method of the loop, Generating a frame synchronizing confirmation signal by an external digital signal processing unit by pulling in the phase synchronizing loop; Determining whether the frame synchronization confirmation signal has been maintained for a predetermined time; Generating a constant speed lock signal if the frame synchronization confirmation signal has been maintained for a predetermined time; Holding frequency detection in response to the constant speed lock signal and fixing the oscillation frequency of the voltage controlled oscillation means; If the frame synchronizing confirmation signal has not been maintained for a predetermined time, releasing a fixed speed lock signal; And Performing frequency detection after the fixed speed lock signal is released, and generating an oscillation frequency of the voltage controlled oscillation means in response to the detected frequency error. Frequency detection means for comparing the frequency of the E.F.M data applied from an external slice circuit with the N-divided oscillation signal and outputting the compared result as an up / down signal, the E.F.M data and the reference A phase locked loop comprising phase detection means for comparing phases of a clock signal and outputting the compared result as an up / down signal, Phase locked loop hold control means for holding the frequency detection and phase detection by generating a phase locked loop hold signal in response to a predetermined defect detection signal, and releasing the hold state after a predetermined time after the completion of the defect detection signal; ; A charge pump / adjusting the amount of current in response to the up / down signal, low-pass filtering the result of the current regulation to generate a control voltage of direct current, and turning on / off the current regulation in response to the phase locked loop hold signal / Low pass filter; A voltage control that generates the oscillation signal having a frequency corresponding to the control voltage and fixes the oscillation signal in response to the control voltage held constant when the current regulation is turned off in response to the phase locked loop hold signal Oscillation means; First dividing means for dividing the oscillation signal by N and outputting the N-divided signal; And And second dividing means for dividing the N-divided signal by M to generate the reference clock signal. The method of claim 4, wherein the phase locked loop hold control means, A frame counter that counts the E.F.M data at an end point of the defect detection signal and outputs the counted result; And And a phase locked loop lock signal generating means for generating a phase locked loop lock signal in response to the defect detection signal and extending the phase locked loop lock signal for a predetermined time in response to an output of the frame counter. Phase locked loop. The method of claim 5, wherein the charge pump / low pass filter, Control signal input means for logically combining the up / down signal and the inverted signal of the phase locked loop hold signal and outputting the logical combined result as a switch control signal; A charge pump for sourcing / sinking a predetermined current in response to the switch control signal or stopping the sourcing / sinking of the current; And And a low pass filter for filtering the output of the charge pump and outputting the filtered result as the control voltage. A stabilization method of a phase locked loop for fixing an oscillation signal of a voltage controlled oscillation means by turning on / off current regulation in an internal charge pump / low pass filter when a disc defect occurs. Determining whether the defect has occurred; (a) if the defect has occurred, generating a phase locked loop hold signal to fix the oscillation signal of the voltage controlled oscillation means; (b) determining whether the defect is finished, and if the defect is not finished, returning to the step (a); (c) if the defect is completed in step (b), maintaining the phase locked loop hold signal and counting E.M. data; (d) determining whether the counted value exceeds a predetermined number of frames, and if the counted value exceeds the predetermined number of frames, releasing the phase locked loop hold signal; Generating an oscillation signal of the voltage controlled oscillation means corresponding to the frequency and phase difference after step (d); And And returning to step (c) if the counted value does not exceed the predetermined number. 8. The method of claim 7, wherein step (d) determines whether the counted value exceeds 5 or 10 frames. Frequency detecting means for comparing the frequencies of the E.M.data applied from the external slice circuit with the N-divided predetermined oscillation signal and outputting the compared result as an up / down signal; Phase-locked loop lock detection means for detecting whether the frequencies of the E.M. data and the N-divided oscillation signal are locked and outputting the detected result as a phase-locked loop lock signal; Error data removal means for removing the error component of the E.F.M data in response to the phase locked loop lock signal and outputting the E.F.M data from which the error component has been removed; Phase detection means for comparing the phase of the E.F.M data from which the error component has been removed and the reference clock signal, and outputting the compared result as an up / down signal; A charge pump / low pass filter for adjusting an amount of current in response to an up / down signal output from the frequency detecting means or a phase detecting means, and filtering the adjusted result to generate a control voltage of direct current; And Voltage controlled oscillation means for generating an oscillation signal having a frequency corresponding to the control voltage; First dividing means for dividing the oscillation signal by N and outputting the N-divided signal; And And second dividing means for dividing the N-divided signal by M to generate the reference clock signal. (a) applying E.F. data from an external slice circuit; Determining whether the phase locked loop is in a locked state, and if not, outputting the E.F.M data as it is and returning to step (a); (b) if the phase locked loop is locked, determining whether the applied data is less than 3T; (c) determining that the E.F.M data is less than 3T as error data and outputting E.F.M data from which the error is removed; (d) if the applied E.M. data is more than 3T and less than 11T or 14T, determining normal data and outputting the applied E.M. data; And And performing phase detection and frequency detection based on the E.F.M data output in step (c) or (d). The method of claim 10, wherein step (b) comprises counting a high or low period of the E.M. data in response to a reference clock signal.