KR100482460B1 - Method for forming polysilicon thin film transistor of liquid crystal display device - Google Patents

Abstract

The present invention discloses a method of forming a polysilicon-thin film transistor of a liquid crystal display device capable of improving the mobility characteristics of the polysilicon-thin film transistor. According to an embodiment of the present invention, a method of forming a source and a drain electrode on an insulating substrate so as to be spaced apart from each other by a predetermined distance may include forming the source and drain electrodes by tapering etching the sidewalls of the source and drain electrodes to a tapered shape. Forming an amorphous silicon layer on a predetermined portion of the substrate, forming an insulating pattern on the amorphous silicon layer between the source drain electrode, ion implanting impurities into the exposed amorphous silicon layer, and insulating Forming a gate electrode on the pattern, and laser annealing the exposed amorphous silicon layer to polyimide, wherein the distance between the source and drain electrodes is an integer multiple of the laser beam wavelength used in the laser annealing. It is done.

Description

Method for forming polysilicon thin film transistor of liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a polysilicon thin film transistor, and more particularly, to a CMOS forming method of a polysilicon thin film transistor in a liquid crystal display device capable of improving electric field mobility characteristics.

In general, a thin film transistor using polysilicon as a channel layer can be miniaturized and has a fast driving capability as compared with a thin film transistor including amorphous silicon as a channel layer.

In addition, when applied to a liquid crystal display device, a thin and small module can be formed to implement a compact display device, and the cost is reduced by forming a drive IC and a thin film transistor at the same time.

In the case of manufacturing a CMOS using such a conventional polysilicon thin film transistor, as shown in FIG. 1, an amorphous silicon layer is deposited on the insulating substrate 1 on which a buffer layer (not shown) is formed. Patterning is to limit the area of. The patterned amorphous silicon layer is laser annealed to a polysilicon layer 2. Then, the gate insulating film 3 and the metal film for the gate electrode are sequentially stacked, and then the metal film is partially patterned to form the gate electrode 4.

Thereafter, the p-MOS transistor region PA is covered, and then n-type impurities are injected into the exposed polysilicon layer 2 of the n-MOS transistor NA region, so that the source and drain regions 5a and 5b of the n-MOS transistor are removed. ). Subsequently, after opening the p MOS transistor region PA, the n MOS transistor region NA is again covered. Thereafter, p-type impurities are implanted into the exposed polysilicon layer 2 of the p-MOS transistor region PA to form the source and drain regions 6a and 6b of the p-MOS transistor.

Then, an interlayer insulating film 7 is deposited on the resultant, and each of the source and drain regions 5a, 5b, 6a, and 5b are etched to be exposed, and then the exposed source and drain regions 5a, 5b, 6a, An aluminum metal film is deposited so as to be in contact with 6b), and a predetermined portion is patterned to form a source and a drain electrode 8.

However, a coplanar type thin film transistor having a channel layer below and a gate electrode formed thereon forms a polysilicon layer by laser annealing an amorphous silicon layer defined as a thin film transistor region. . At this time, since the laser beam of several shots is applied during laser annealing, the laser beam is not uniformly irradiated, so that the grain size in the polysilicon film is not uniform and defects are likely to occur in the polysilicon film.

For this reason, the problem that the mobility of a thin film transistor falls is produced.

Accordingly, an object of the present invention is to solve the above-mentioned conventional problems, and to provide a method of forming a polysilicon-thin film transistor of a liquid crystal display device capable of improving the mobility characteristics of the polysilicon-thin film transistor.

In order to achieve the above object of the present invention, in accordance with an embodiment of the present invention, forming a source, a drain electrode spaced apart from the predetermined distance on the insulating substrate, so that the sidewalls of the source, drain electrode is tapered Forming by tapering etching, forming an amorphous silicon layer on a predetermined portion of the substrate on which the source and drain electrodes are formed, forming an insulating pattern on the amorphous silicon layer between the source and drain electrodes, and exposing the Implanting impurities into the formed amorphous silicon layer, forming a gate electrode on the insulating pattern, and laser annealing the exposed amorphous silicon layer to form a polysilicon layer; The distance is an integer multiple of the laser beam wavelength used in the laser annealing.

In addition, the source and drain electrodes are formed to be spaced apart from each other by a predetermined distance in each of the MOS regions on the upper portion of the insulating substrate where the N-MOS region and the P-MOS region are defined.The source and drain electrodes are formed by tapering etching so that sidewalls are tapered. Forming an amorphous silicon layer on the substrate on which the source and drain electrodes are formed, and forming a first insulating pattern on the amorphous silicon layer between the source and drain electrodes of the NMOS region, wherein the NMOS region is all Forming a second insulating pattern to cover, ion implanting N-type impurities into the exposed amorphous silicon layer, and patterning the second insulating pattern to exist between the source drain electrode of the PMOS region And covering the N-MOS region with a photoresist pattern, and implanting P-type impurities into the exposed P-MOS region. And removing the photoresist pattern, laser annealing the exposed amorphous silicon layer, polylating, and forming a gate electrode over each of the insulating patterns. The distance between the electrodes is characterized in that the integer multiple of the laser beam wavelength used in the laser annealing.

While the source and drain electrodes are formed on the substrate surface, the sidewalls thereof are formed in a tapered form, and the source and drain electrodes are formed to be spaced by an integer multiple of the laser wavelength, and an amorphous silicon layer is deposited thereon. Then, an insulating layer and a gate electrode are formed over the source and drain electrodes, and then laser annealing is performed. As such, the air-conditioning phenomenon of the laser beam occurs in the amorphous silicon layer under the insulating layer, so that the polyimation is more uniform. As a result, the already doped dopants diffuse toward the channel, reducing the contact area of the contact area, thereby improving channel mobility.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2D are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to the present invention.

First, referring to FIG. 2A, a metal film such as Ni, Al, MoW, AlNd., Mo, Ta, or MoTa is deposited on the insulating substrate 10 on which the buffer layer 11 is formed to a predetermined thickness, and then patterned by a predetermined portion. Source and drain electrodes 12 and 13 are formed. At this time, the source and drain electrodes 12 have a predetermined interval, preferably an integer multiple of the laser wavelength λ, and the sidewalls of the source and drain electrodes 12 and 13 are tapered so as to be tapered. Etch. Here, the angle between the sidewalls of the source and drain electrodes 12 and 13 and the substrate should be formed to be the same. Then, an amorphous silicon layer 14 is deposited on the substrate 10 on which the source and drain electrodes 12 and 13 are formed, and then patterned to define a MOS transistor region (N-MOS region, P-MOS region), respectively. do. After that, after depositing the insulating layer, the insulating layer is patterned to exist between the source and drain electrodes 12 and 13 on the N-MOS region, that is, only on the channel region, thereby forming the first insulating pattern 15a. On the P MOS region, the insulating layer is patterned to cover all of the P MOS regions to form the second insulating pattern 15b. Then, an N-type impurity such as phosphorus ion is implanted into the exposed amorphous silicon layer 14 of the N-MOS region, thereby forming a junction region of the N-MOS transistor.

Thereafter, as shown in FIG. 2B, the second insulating pattern 15b of the P-MOS region is patterned to exist only in the channel region on the P-MOS region. Subsequently, a photoresist film is applied on the resultant, exposed and developed so as to exist only on the N-MOS region, thereby forming a photoresist pattern. Then, P-type impurities such as boron ions are implanted into the amorphous silicon layer 14 of the exposed P-MOS region to form a junction region of the P-MOS transistor.

Then, the photoresist pattern is removed in a known manner, and then, as shown in FIG. 2C, a metal film for the gate electrode is deposited on the resultant, and then patterned so as to be present on the first and second insulating patterns 15a. The electrode 16 is formed. In this case, the gate electrode 16 is formed to be narrower than the insulating patterns 15a and 15b in consideration of an offset margin.

Then, the exposed amorphous silicon layer 14 is subjected to a laser annealing process to form the polysilicon layer 14a. In this process, the amorphous silicon layer under the insulating patterns 15a and 15b, that is, the amorphous silicon layer serving as a channel, is polypolized by the air conditioning phenomenon of the laser beam. More specifically, the laser beam incident on the front surface is reflected from the sidewalls of the tapered source and drain electrodes 12 and 13 to polylize the amorphous silicon layer under the insulating patterns 15a and 15b. . At this time, since the distance between the source and the drain electrodes 12 and 13 is an integer multiple of the laser wavelength, the laser beams applied from both sides cause constructive interference, and a laser beam having greater intensity is applied to the channel portion. In order to have more uniform grains, the poly-forming is carried out. In this process, the dopants already doped are diffused toward the channel, thereby reducing the contact area of the contact area, thereby improving channel mobility.

Then, as shown in FIG. 2D, the passivation layer 17 is coated on the completed polysilicon-thin film transistor, and then an input signal Vin is applied to the gate electrodes of the N-MOS and P-MOS transistors, whereby the N-MOS transistor is applied. The output signal Vout is obtained from the drain electrode 13 of and the source electrode 12 of PMOS.

As described in detail above, according to the present invention, while the source and drain electrodes are formed on the substrate surface, the sidewalls thereof are tapered, and the source and drain electrodes are formed to be spaced by an integer multiple of the laser wavelength, and the upper portion thereof. An amorphous silicon layer is deposited on the substrate. Then, an insulating layer and a gate electrode are formed over the source and drain electrodes, and then laser annealing is performed. As such, the air-conditioning phenomenon of the laser beam occurs in the amorphous silicon layer under the insulating layer, so that the polyimation is more uniform. As a result, the already doped dopants diffuse toward the channel, reducing the contact area of the contact area, thereby improving channel mobility.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

1 is a cross-sectional view of a polysilicon-thin film transistor CMOS of a conventional liquid crystal display.

2A to 2D are cross-sectional views for explaining a method of forming a polysilicon-thin film transistor CMOS of a liquid crystal display device according to the present invention;

(Explanation of symbols for the main parts of the drawing)

10: insulating substrate 11: buffer layer

12 source electrode 13 drain electrode

14: amorphous silicon layer 14a: polysilicon layer

15a, 15b: insulation pattern 16: gate electrode

17: interlayer insulation film

Claims (2)

Forming a source and a drain electrode on the insulating substrate so as to be spaced apart from each other by a predetermined distance, wherein the sidewalls of the source and the drain electrode are tapered to form a tapered shape; Forming an amorphous silicon layer on a predetermined portion of the substrate on which the source and drain electrodes are formed; Forming an insulating pattern on an amorphous silicon layer between the source drain electrodes; Implanting impurities into the exposed amorphous silicon layer; Forming a gate electrode on the insulating pattern; Laser annealing the exposed amorphous silicon layer to form a polyolefin; And the distance between the source and drain electrodes is an integer multiple of the wavelength of the laser beam used in the laser annealing. Forming source and drain electrodes spaced apart from each other by a predetermined distance in each MOS region of the upper portion of the insulating substrate having an N-MOS region and a P-MOS region, wherein the source and drain electrodes are formed by tapering etching such that sidewalls are tapered; Forming an amorphous silicon layer on the substrate on which the source and drain electrodes are formed; Forming a first insulating pattern on an amorphous silicon layer between the source drain electrodes of the N-MOS region, and forming a second insulating pattern to cover all of the N-MOS regions; Ion implanting N-type impurities into the exposed amorphous silicon layer; Patterning the second insulating pattern to exist between the source and drain electrodes of the P-MOS region; Covering the N-MOS region with a photoresist pattern; Ion implanting P-type impurities into the exposed P-MOS region; Removing the photoresist pattern; Laser annealing the exposed amorphous silicon layer to polylize; And Forming a gate electrode on each of the insulating patterns; And the distance between the source and drain electrodes is an integer multiple of the wavelength of the laser beam used in the laser annealing.