[go: up one dir, main page]

KR100481831B1 - Capacitor Manufacturing Method for Semiconductor Devices - Google Patents

Capacitor Manufacturing Method for Semiconductor Devices Download PDF

Info

Publication number
KR100481831B1
KR100481831B1 KR1019970034705A KR19970034705A KR100481831B1 KR 100481831 B1 KR100481831 B1 KR 100481831B1 KR 1019970034705 A KR1019970034705 A KR 1019970034705A KR 19970034705 A KR19970034705 A KR 19970034705A KR 100481831 B1 KR100481831 B1 KR 100481831B1
Authority
KR
South Korea
Prior art keywords
film
barrier metal
interlayer insulating
metal film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019970034705A
Other languages
Korean (ko)
Other versions
KR19990011567A (en
Inventor
이문희
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1019970034705A priority Critical patent/KR100481831B1/en
Publication of KR19990011567A publication Critical patent/KR19990011567A/en
Application granted granted Critical
Publication of KR100481831B1 publication Critical patent/KR100481831B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 장벽 금속막의 산화를 방지할 수 있는 반도체 장치의 커패시터 제조 방법에 관한 것으로, 반도체 기판 상에 층간절연막을 형성하는 공정과, 상기 반도체 기판의 상부 표면이 노출되도록 상기 층간 절연막을 식각하여 콘택홀을 형성하는 공정과, 상기 콘택홀에 폴리실리콘막을 충전하는 공정과, 상기 콘택홀의 상부 양측면이 노출되도록 상기 폴리실리콘막을 소정의 두께로 식각하는 공정과, 상기 폴리실리콘막 상에 Ti 실리사이드막을 형성하는 공정과, 상기 Ti 실리사이드막을 포함하여 상기 층간 절연막 상에 장벽 금속막을 형성하는 공정과, 상기 층간 절연막의 상부 표면이 노출되도록 상기 장벽 금속막을 평탄화하는 공정을 포함한다. 이와 같은 반도체 장치의 커패시터 제조 방법에 의해서, 장벽 금속막의 산화를 방지할 수 있고, 또한 BST 커패시터의 커패시턴스를 감소 및 유전손실의 증가를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device capable of preventing oxidation of a barrier metal film, the method comprising: forming an interlayer insulating film on a semiconductor substrate; and etching the interlayer insulating film to expose the upper surface of the semiconductor substrate. Forming a hole, filling a polysilicon film into the contact hole, etching the polysilicon film to a predetermined thickness so that both sides of the upper surface of the contact hole are exposed, and forming a Ti silicide film on the polysilicon film And a step of forming a barrier metal film on the interlayer insulating film including the Ti silicide film, and planarizing the barrier metal film to expose an upper surface of the interlayer insulating film. By the capacitor manufacturing method of such a semiconductor device, the oxidation of the barrier metal film can be prevented, and the capacitance of the BST capacitor can be reduced and the increase in dielectric loss can be prevented.

Description

반도체 장치의 커패시터 제조 방법Method of manufacturing capacitors in semiconductor devices

본 발명은 반도체 장치의 제조 방법에 관한 것으로, 좀 더 구체적으로는, 장벽 금속막(barrier metal)의 산화를 방지하는 반도체 장치의 커패시터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device that prevents oxidation of a barrier metal film.

반도체 소자의 고집적화에 따른 디자인 룰(design rule)의 감소는 커패시터와 같은 구조에 새로운 유전물질의 사용을 요구한다. 일반적으로 커패시턴스는 유전물질(dielectric material)의 유전율과 유전체가 접촉하는 전극(electrode)의 표면적, 그리고 유전체의 두께와 직접 관련이 있다.The reduction of design rules due to the high integration of semiconductor devices requires the use of new dielectric materials in structures such as capacitors. In general, capacitance is directly related to the dielectric constant of the dielectric material, the surface area of the electrode to which the dielectric is in contact, and the thickness of the dielectric.

디자인 룰 및 이용 면적의 감소에 따라 기존의 커패시터에 사용되던 유전 물질인 ONO(Oxide Nitride Oxide) 유전막의 표면적 넓이는 이미 한계에 다다랐고, 또한 유전체를 통한 일렉트론 터널링(electron tunneling)현상 때문에 두께를 감소시키는 것도 매우 어렵다.As the design rules and footprint decrease, the surface area of the oxide Nitride Oxide (ONO) dielectric film used in conventional capacitors has already reached its limit, and the thickness is reduced due to the electron tunneling through the dielectric. It is also very difficult to make.

따라서, ONO 유전막을 사용하여 256M급 이상의 고집적 반도체에서 충분한 커패시턴스를 얻기는 매우 힘들기 때문에, 근래에는 (Ba, Sr)TiO3(이하 BST)와 같은 고유전물(HDC ;high dielectric constant)물질을 사용하는 방법이 제기되고 있다.Therefore, it is very difficult to obtain sufficient capacitance in high-integration semiconductors of 256M or higher by using ONO dielectric films. Recently, high dielectric constant (HDC) materials such as (Ba, Sr) TiO 3 (hereinafter referred to as BST) are used. How to do this is being raised.

반도체 소자에 BST와 같은 신물질의 도입은 기존의 실리콘 기반(Si-based)공정과는 다른 독특한 공정을 필요로 한다. 특히, 매몰 콘택 플러그(Buried Contact plug)로 사용되는 폴리실리콘막은 BST와의 반응으로 저유전체(low dielectric)인 SiO2를 생성하고, 이는 전체 유전율을 급격히 감소시키기 때문에 이들의 반응을 막기 위한 새로운 전극을 필요로 한다.The introduction of new materials, such as BST, into semiconductor devices requires a unique process that is different from conventional silicon-based processes. In particular, the polysilicon film used as a buried contact plug generates a low dielectric SiO 2 in reaction with BST, which dramatically reduces the overall dielectric constant and thus provides a new electrode to prevent their reaction. in need.

이와 같은 전극으로는 노블 메탈(noble metal) 예컨대, Pt, Ru, Ir이나 이들의 산화막 화합물인 RuO2, 및 IrO2 등이 널리 이용되고 있다. 그러나, 이러한 전극은 전극 물질의 그레인 바운더리(grain boundary)를 따라 산소 확산(oxygen diffusion)이 빠르게 진행되어 이웃한 실리사이드 콘택(silicide contact)등을 산화시킬 뿐 아니라, Pt와 같은 물질은 Si와 반응하여 Pt-Si를 형성하기도 한다.As such an electrode, a noble metal such as Pt, Ru, Ir or RuO 2 and IrO 2 which are oxide film compounds thereof are widely used. However, such an electrode not only oxidizes oxygen diffusion rapidly along the grain boundary of the electrode material to oxidize neighboring silicide contacts, but also reacts with Si such as Pt. It also forms Pt-Si.

또한, BST 커패시터와 관련된 공정의 또다른 문제점으로는, BST 형성이나 어닐링(annealing)시 장벽 금속막(barrier metal layer)이 산화되는 현상이다.In addition, another problem of the process associated with the BST capacitor is a phenomenon in which a barrier metal layer is oxidized during BST formation or annealing.

장벽 금속막이 산화되면 새로운 얇은 절연층이 형성되고, 이는 원하지 않는 또 다른 커패시터의 형성을 초래하여서 BST 커패시터의 커패시턴스를 감소시킬 뿐만 아니라, 유전손실(tanδ)이 크게 증가하는 심각한 문제점이 발생된다.When the barrier metal film is oxidized, a new thin insulating layer is formed, which leads to the formation of another unwanted capacitor, which not only reduces the capacitance of the BST capacitor, but also causes a serious problem of greatly increasing the dielectric loss tanδ.

상술한 문제점을 해결하기 위해 제안된 본 발명은, 장벽 금속막의 산화를 방지할 수 있는 반도체 장치의 커패시터 제조 방법을 제공하는 데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention proposed to solve the above problems is to provide a method of manufacturing a capacitor of a semiconductor device capable of preventing oxidation of a barrier metal film.

(구성)상술한 바와 같은 목적을 달성하기 위한 본 발명에 의하면, 반도체 장치의 커패시터 제조 방법은, 반도체 기판 상에 층간절연막을 형성하는 공정과; 상기 반도체 기판의 상부 표면이 노출되도록 상기 층간 절연막을 식각하여 콘택홀을 형성하는 공정과; 상기 콘택홀에 폴리실리콘막을 충전하는 공정과; 상기 콘택홀의 상부 양측면이 노출되도록 상기 폴리실리콘막을 소정의 두께로 식각하는 공정과; 상기 폴리실리콘막 상에 도전성 박막을 형성하는 공정과; 상기 도전성 박막을 포함하여 상기 층간 절연막 상에 장벽 금속막을 형성하는 공정과; 상기 층간 절연막의 상부 표면이 노출되도록 상기 장벽 금속막을 평탄화하는 공정을 포함한다.(Configuration) According to the present invention for achieving the above object, a capacitor manufacturing method of a semiconductor device includes the steps of forming an interlayer insulating film on a semiconductor substrate; Etching the interlayer insulating film to expose the upper surface of the semiconductor substrate to form a contact hole; Filling a polysilicon film into the contact hole; Etching the polysilicon film to a predetermined thickness so that both upper side surfaces of the contact hole are exposed; Forming a conductive thin film on the polysilicon film; Forming a barrier metal film on the interlayer insulating film including the conductive thin film; And planarizing the barrier metal film so that an upper surface of the interlayer insulating film is exposed.

이 방법의 바람직한 실시예에 있어서, 상기 반도체 장치의 커패시터 제조 방법은, 상기 평탄화된 장벽 금속막을 상기 층간 절연막 보다 상대적으로 낮은 단차를 갖도록 소정의두께로 식각하는 공정을 부가한다.In a preferred embodiment of this method, the capacitor manufacturing method of the semiconductor device adds a step of etching the planarized barrier metal film to a predetermined thickness so as to have a step lower than the interlayer insulating film.

이 방법의 바람직한 실시예에 있어서, 상기 폴리실리콘막은 200-1000Å 범위내에서 식각된다.In a preferred embodiment of this method, the polysilicon film is etched in the range of 200-1000 kPa.

이 방법의 바람직한 실시예에 있어서, 상기 폴리실리콘막은 NH4OH, H2O2, 그리고 초순수의 혼합 용액을 이용하여 식각된다.In a preferred embodiment of this method, the polysilicon film is etched using a mixed solution of NH 4 OH, H 2 O 2 , and ultrapure water.

이 방법의 바람직한 실시예에 있어서, 상기 혼합 용액은 NH4OH, H2O2, 그리고 초순수의 혼합비가 10:1:100이다.In a preferred embodiment of this method, the mixed solution has a mixing ratio of NH 4 OH, H 2 O 2 , and ultrapure water of 10: 1: 100.

이 방법의 바람직한 실시예에 있어서, 상기 도전성 박막은 Ti 실리사이드막으로 형성된다.In a preferred embodiment of this method, the conductive thin film is formed of a Ti silicide film.

이 방법의 바람직한 실시예에 있어서, 상기 장벽 금속막은 200-1000Å 범위내의 두께로 형성된다.In a preferred embodiment of this method, the barrier metal film is formed to a thickness in the range of 200-1000 kPa.

이 방법의 바람직한 실시예에 있어서, 상기 장벽 금속막은 TiN, TiSiN, TaSiN, 그리고 TaAlN 중 적어도 하나로 형성된다.In a preferred embodiment of this method, the barrier metal film is formed of at least one of TiN, TiSiN, TaSiN, and TaAlN.

(작용)이와 같은 반도체 장치의 커패시터 제조 방법에 의해서, 장벽 금속막의 산화를 방지할 수 있고, 또한 BST 커패시터의 커패시턴스를 감소 및 유전손실의 증가를 방지할 수 있다.(Action) By the capacitor manufacturing method of the semiconductor device as described above, the oxidation of the barrier metal film can be prevented, and the capacitance of the BST capacitor can be reduced and the increase in dielectric loss can be prevented.

(실시예)이하, 본 발명의 바람직한 실시예를 첨부 도면 도 1a 내지 도 1f에 의거해서 상세히 설명한다.(Examples) Hereinafter, preferred embodiments of the present invention will be described in detail with reference to Figs. 1A to 1F.

도 1a 내지 도 1f에는 본 발명의 실시예에 따른 반도체 장치의 커패시터 제조 방법이 순차적으로 도시되어 있다.1A to 1F sequentially illustrate a capacitor manufacturing method of a semiconductor device according to an embodiment of the present invention.

먼저, 도 1a를 참조하면, 반도체 기판(10)상에 층간절연막(12)을 형성하고, 이어서, 이 기술 분야에서 잘 알려진 포토리소그라피(photography)공정을 이용하여 상기 반도체 기판(10)의 상부 표면이 노출되도록 상기 층간 절연막(12)을 식각하여 콘택홀을 형성한다. 그리고, 상기 콘택홀에 폴리실리콘막(14)을 충전한다.First, referring to FIG. 1A, an interlayer insulating film 12 is formed on a semiconductor substrate 10, and then an upper surface of the semiconductor substrate 10 using a photolithography process well known in the art. The interlayer insulating layer 12 is etched so as to expose the contact hole. The polysilicon film 14 is filled in the contact hole.

다음, 도 1b에 도시된 바와 같이, 상기 콘택홀의 상부 양측면이 노출되도록 상기 폴리실리콘막(14)을 약 200-1000Å 범위내에서 식각한다. 이때, 상기 폴리실리콘막(14)의 식각은 NH4OH, H2O2, 그리고 초순수가 약 10:1:100 또는 20:1:100으로 혼합된 혼합 용액을 이용하여 식각된다.Next, as shown in FIG. 1B, the polysilicon film 14 is etched within a range of about 200-1000 kPa so that both upper sides of the contact hole are exposed. In this case, the polysilicon layer 14 is etched using NH 4 OH, H 2 O 2 , and a mixed solution mixed with ultrapure water of about 10: 1: 100 or 20: 1: 100.

이어서, 도 1c에 있어서, 상기 폴리실리콘막(14)상에 Ti 실리사이드막(16)을 형성하고, 그리고, 도 1d를 참조하면, 상기 콘택홀 상부의 Ti 실리사이드막(16)을 포함하여 상기 층간 절연막(12)상에 장벽 금속막(18)을 형성한다.Next, in FIG. 1C, a Ti silicide film 16 is formed on the polysilicon film 14, and referring to FIG. 1D, the interlayer including the Ti silicide film 16 on the contact hole is included. A barrier metal film 18 is formed on the insulating film 12.

도 1e를 참조하면, 상기 층간 절연막(12)의 상부 표면이 노출되도록 상기 장벽 금속막(18)을 CMP(Chemical Mechanical Polishing)공정을 이용하여 평탄화시킨다. 이때, 상기 장벽 금속막(18)은 약 200-1000Å 범위내에서 형성되고, 그리고 상기 장벽 금속막(18)은 TiN, TiSiN, TaSiN, 그리고 TaAlN 중, 어느 하나로 형성된다.Referring to FIG. 1E, the barrier metal film 18 is planarized using a chemical mechanical polishing (CMP) process so that the upper surface of the interlayer insulating film 12 is exposed. At this time, the barrier metal film 18 is formed in the range of about 200-1000 GPa, and the barrier metal film 18 is formed of any one of TiN, TiSiN, TaSiN, and TaAlN.

마지막으로, 도 1f에 도시된 바와 같이, 상기 평탄화된 장벽 금속막(18)을 상기 층간 절연막(12) 보다 상대적으로 낮은 단차를 갖도록 식각하는데, 이는 상기 장벽 금속막(18)의 에지 부위의 내산화성을 강화시키기 위한 공정이다.Finally, as shown in FIG. 1F, the planarized barrier metal film 18 is etched to have a relatively lower step than the interlayer insulating film 12, which is in the edge portion of the barrier metal film 18. It is a process for enhancing oxidative properties.

상술한 바와 같은 반도체 장치의 제조 방법에 의하면, 장벽 금속막의 산화를 방지할 수 있고, 또한 BST 커패시터의 커패시턴스를 감소 및 유전손실의 증가를 방지할 수 있다.According to the method of manufacturing a semiconductor device as described above, the oxidation of the barrier metal film can be prevented, and the capacitance of the BST capacitor can be reduced and the increase in dielectric loss can be prevented.

도 1a 내지 도 1f는 본 발명의 실시예에 따른 반도체 장치의 커패시터 제조 방법을 순차적으로 보이는 공정도.1A to 1F are flowcharts sequentially showing a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호 설명* Explanation of symbols on the main parts of the drawing

10 : 반도체 기판 12 : 층간절연막10 semiconductor substrate 12 interlayer insulating film

14 : 폴리실리콘막 16 : Ti 실리사이드14 polysilicon film 16 Ti silicide

18 : 장벽 금속막18: barrier metal film

Claims (7)

반도체 기판(10)상에 층간절연막(12)을 형성하는 공정과;Forming an interlayer insulating film 12 on the semiconductor substrate 10; 상기 반도체 기판(10)의 상부 표면이 노출되도록 상기 층간 절연막(12)을 식각하여 콘택홀을 형성하는 공정과;Forming a contact hole by etching the interlayer insulating layer 12 so that the upper surface of the semiconductor substrate 10 is exposed; 상기 콘택홀에 폴리실리콘막(14)을 충전하는 공정과;Filling the contact hole with a polysilicon layer (14); 상기 콘택홀의 상부 양측면이 노출되도록 상기 폴리실리콘막(14)을 소정의 두께로 식각하는 공정과;Etching the polysilicon film (14) to a predetermined thickness so that both upper surfaces of the contact hole are exposed; 상기 폴리실리콘막(14)상에 도전성 박막(16)을 형성하는 공정과;Forming a conductive thin film (16) on the polysilicon film (14); 상기 도전성 박막(16)을 포함하여 상기 층간 절연막(12)상에 장벽 금속막(18)을 형성하는 공정과;Forming a barrier metal film (18) on the interlayer insulating film (12) including the conductive thin film (16); 상기 층간 절연막(12)의 상부 표면이 노출되도록 상기 장벽 금속막(18)을 평탄화하는 공정과;Planarizing the barrier metal film (18) such that an upper surface of the interlayer insulating film (12) is exposed; 상기 평탄화된 장벽 금속막(18)을 상기 층간 절연막(12) 보다 상대적으로 낮은 단차를 갖도록 소정의 두께로 식각하여 상기 장벽 금속막(18)의 에지 부위의 내산화성을 강화하는 공정을 포함하는 반도체 장치의 커패시터 제조 방법.Etching the planarized barrier metal film 18 to a predetermined thickness so as to have a step lower than that of the interlayer insulating film 12 to enhance oxidation resistance of the edge portion of the barrier metal film 18. Method of manufacturing capacitors in the device. 제 1 항에 있어서, 상기 폴리실리콘막(14)은 200-1000Å 범위내에서 식각되는 반도체 장치의 커패시터 제조 방법.The method of claim 1, wherein the polysilicon film (14) is etched in the range of 200-1000 microseconds. 제 1 항에 있어서, 상기 폴리실리콘막(14)은 NH4OH, H2O2, 그리고 초순수의 혼합 용액을 이용하여 식각되는 반도체 장치의 커패시터 제조 방법.The method of claim 1, wherein the polysilicon film is etched using a mixed solution of NH 4 OH, H 2 O 2 , and ultrapure water. 제 3 항에 있어서, 상기 혼합 용액은 NH4OH, H2O2, 그리고 초순수의 혼합비가 10:1:100인 반도체 장치의 커패시터 제조 방법.The method of claim 3, wherein the mixed solution has a mixing ratio of NH 4 OH, H 2 O 2 , and ultrapure water of 10: 1: 100. 제 1 항, 제 3 항 또는 제 4 항 중에 어느 한 항에 있어서, 상기 도전성 박막(16)은 Ti 실리사이드막을 형성되는 반도체 장치의 커패시터 제조 방법.5. The method of claim 1, 3, or 4, wherein the conductive thin film (16) forms a Ti silicide film. 제 1 항에 있어서, 상기 장벽 금속막(18)은 200-1000Å 범위내의 두께로 형성되는 반도체 장치의 커패시터 제조 방법.2. The method of claim 1 wherein the barrier metal film (18) is formed to a thickness in the range of 200-1000 microseconds. 제 1 항에 있어서, 상기 장벽 금속막(18)은 TiN, TiSiN, TaSiN, 그리고 TaAlN 중 적어도 하나로 형성되는 반도체 장치의 커패시터 제조 방법.The method of claim 1, wherein the barrier metal film (18) is formed of at least one of TiN, TiSiN, TaSiN, and TaAlN.
KR1019970034705A 1997-07-24 1997-07-24 Capacitor Manufacturing Method for Semiconductor Devices Expired - Fee Related KR100481831B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019970034705A KR100481831B1 (en) 1997-07-24 1997-07-24 Capacitor Manufacturing Method for Semiconductor Devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019970034705A KR100481831B1 (en) 1997-07-24 1997-07-24 Capacitor Manufacturing Method for Semiconductor Devices

Publications (2)

Publication Number Publication Date
KR19990011567A KR19990011567A (en) 1999-02-18
KR100481831B1 true KR100481831B1 (en) 2006-05-16

Family

ID=37181295

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970034705A Expired - Fee Related KR100481831B1 (en) 1997-07-24 1997-07-24 Capacitor Manufacturing Method for Semiconductor Devices

Country Status (1)

Country Link
KR (1) KR100481831B1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332120B1 (en) * 1999-06-30 2002-04-10 박종섭 Method of manufacturing a capacitor in a semiconductor device
KR100545698B1 (en) * 1999-12-22 2006-01-24 주식회사 하이닉스반도체 How to Form Contact Plugs for Capacitors
KR100546108B1 (en) * 1999-12-30 2006-01-24 주식회사 하이닉스반도체 Method of forming contact plug of semiconductor device
KR100487416B1 (en) * 2000-12-30 2005-05-03 주식회사 하이닉스반도체 Method for manufacturing storage node barrier metal of storage capacitor
KR100443361B1 (en) * 2002-04-26 2004-08-09 주식회사 하이닉스반도체 Method for fabricating capacitor using electro chemical deposition
KR102352245B1 (en) * 2014-11-13 2022-01-18 삼성전자주식회사 Manufacturing method of semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5392189A (en) * 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US5489548A (en) * 1994-08-01 1996-02-06 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising sidewall spacers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5381302A (en) * 1993-04-02 1995-01-10 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same
US5392189A (en) * 1993-04-02 1995-02-21 Micron Semiconductor, Inc. Capacitor compatible with high dielectric constant materials having two independent insulative layers and the method for forming same
US5506166A (en) * 1993-04-02 1996-04-09 Micron Technology, Inc. Method for forming capacitor compatible with high dielectric constant materials having a low contact resistance layer
US5489548A (en) * 1994-08-01 1996-02-06 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising sidewall spacers

Also Published As

Publication number Publication date
KR19990011567A (en) 1999-02-18

Similar Documents

Publication Publication Date Title
US6001660A (en) Methods of forming integrated circuit capacitors using metal reflow techniques
KR0168346B1 (en) Capacitor using high deelectric material and its fabrication method
KR100411353B1 (en) How to Form Capacitors and Capacitors
US6750500B1 (en) Capacitor electrode for integrating high K materials
KR100285066B1 (en) Method of forming a capacitor having a high dielectric material
KR100587635B1 (en) Manufacturing Method of Semiconductor Device
JPH11243184A (en) High dielectric constant capacitor and manufacturing method
KR20020035792A (en) Dielectric device and method for manufacturing the same
WO2002056383A1 (en) Semiconductor storage device and its manufacturing method
KR100481831B1 (en) Capacitor Manufacturing Method for Semiconductor Devices
US6171898B1 (en) Method of fabricating an oxygen-stable layer/diffusion barrier/poly bottom electrode structure for high-K-DRAMS using a disposable-oxide processing
KR100418586B1 (en) Method of forming memory device
US20080179645A1 (en) Semiconductor device and method of producing the same
KR100190112B1 (en) Ferroelectric capacitors and manufacturing method thereof
KR100269301B1 (en) Capacitor for preventing barrier layer from oxidizing and manufacturing method thereof
JP2003218235A (en) Storage device having composite contact plug and method of manufacturing the same
KR100415539B1 (en) Method for fabricating semiconductor device
KR100546151B1 (en) Capacitor Manufacturing Method of Semiconductor Device
KR100700330B1 (en) Manufacturing method of capacitor
KR100275116B1 (en) Method for forming capacitor of semiconductor device
KR100734640B1 (en) Capacitor Manufacturing Method of Semiconductor Device
KR100680937B1 (en) Method for manufacturing semiconductor device
KR100846384B1 (en) Manufacturing Method of Semiconductor Device
KR20010105885A (en) Semiconductor fabrication method capable of preventing misalign between bottom electrode and storage node contact and oxidation of diffusion barrier layer
KR20010113320A (en) Method of manufacturing a capacitor in a semiconductor device

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R13-asn-PN2301

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20080331

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20080331

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000