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KR100477835B1 - Ferroelectric Capacitor Formation Method - Google Patents

Ferroelectric Capacitor Formation Method Download PDF

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KR100477835B1
KR100477835B1 KR1019970077957A KR19970077957A KR100477835B1 KR 100477835 B1 KR100477835 B1 KR 100477835B1 KR 1019970077957 A KR1019970077957 A KR 1019970077957A KR 19970077957 A KR19970077957 A KR 19970077957A KR 100477835 B1 KR100477835 B1 KR 100477835B1
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forming
ferroelectric capacitor
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diffusion
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김남경
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H10D1/688—Capacitors having no potential barriers having dielectrics comprising perovskite structures comprising barrier layers to prevent diffusion of hydrogen or oxygen
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes

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Abstract

본 발명은 유전막으로 SrBi2Ta2O5막을 이용하는 강유전체 캐패시터 형성 방법으로, 화학기상증착법으로 증착 가능한 Ta2O5막을 확산방지막으로 형성하여 층덮힘 특성을 향상시키고, 또한, Ta2O5막에 표면에 얇은 TaNy막을 형성하여 수소의 확산을 보다 효과적으로 방지해서 유전막의 조성 변화를 방지함으로써 소자의 안정된 전기적 특성 및 신뢰성 향상을 꾀할 수 있다.The present invention provides a method of forming a ferroelectric capacitor using an SrBi 2 Ta2O 5 film as a dielectric film, and forms a Ta 2 O 5 film that can be deposited by chemical vapor deposition as a diffusion barrier to improve layer covering properties, and further, on the surface of the Ta 2 O 5 film. By forming a thin TaN y film to more effectively prevent the diffusion of hydrogen to prevent a change in the composition of the dielectric film, it is possible to improve the stable electrical characteristics and reliability of the device.

Description

강유전체 캐패시터 형성 방법How to Form Ferroelectric Capacitors

본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 강유전체 캐패시터 형성 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a ferroelectric capacitor.

강유전체는 상온에서 유전상수가 크고, 안정한 잔류분극(remanent polarization) 특성이 있어, 비휘발성(nonviolation) 메모리 소자에 응용되고 있다. 강유전체 박막을 비휘발성 메모리 소자로 사용하는 경우 가해주는 전기장의 방향으로 분극의 방향을 조절하여 신호를 입력하고, 전기장을 제거하였을 때 남아있는 잔류분극의 방향에 의해 디지털 신호(digital) 1과 0을 저장하게 되는 원리를 이용하는 것이다.Ferroelectrics have a large dielectric constant at room temperature and have stable residual polarization characteristics, and thus are being applied to nonvolatile memory devices. When using a ferroelectric thin film as a nonvolatile memory device, the signal is input by adjusting the direction of polarization in the direction of an electric field applied to the ferroelectric thin film, and the digital signals 1 and 0 are determined by the direction of residual polarization remaining when the electric field is removed. Is to use the principle of storage.

이하, 종래 기술에 따른 반도체 장치의 강유전체 캐패시터 형성 공정 단면도인 도1을 참조하여 종래 기술을 설명한다.The prior art will now be described with reference to FIG. 1, which is a cross-sectional view of a ferroelectric capacitor forming process of a semiconductor device according to the prior art.

도1에 도시한 바와 같이 반도체 기판(10) 상에 형성된 층간절연막(14, 16)을 선택적으로 식각하여 콘택홀을 형성하고, 콘택홀 내부에 폴리실리콘 플러그(17)를 형성한 후, 반도체 기판(10) 전면에 장벽금속막으로 티타늄(Ti)막(18)을 형성한 다음, 하부전극을 형성하기 위하여 Ti막(18) 상에 백금(pt)막(19)을 스퍼터링(sputtering) 방법으로 형성하고, Pt막(19) 상에 강유전체막(20)을 형성한다. 이어서, 강유전체막(20), Pt막(19), Ti막(18)을 패터닝하고, 반도체 기판(10) 전면에 에 제1 확산방지산화막(21) 및 제2 확산방지산화막(22)을 형성하고 선택적으로 식각하여 강유전체막(20)을 노출시킨다. 다음으로, 노출된 강유전체막(20)과 접하는 상부전극(23)을 형성한다. 도1에서 미설명 도면부호 '11'은 필드산화막, '12'는 게이트 산화막, '13'은 게이트 전극, '15'는 비트라인을 각각 나타낸다.As shown in FIG. 1, the interlayer insulating films 14 and 16 formed on the semiconductor substrate 10 are selectively etched to form contact holes, and then the polysilicon plugs 17 are formed in the contact holes. (10) A titanium (Ti) film 18 is formed on the entire surface by a barrier metal film, and then a platinum film 19 is sputtered on the Ti film 18 to form a lower electrode. The ferroelectric film 20 is formed on the Pt film 19. Subsequently, the ferroelectric film 20, the Pt film 19, and the Ti film 18 are patterned, and the first diffusion preventing oxide film 21 and the second diffusion preventing oxide film 22 are formed on the entire surface of the semiconductor substrate 10. And selectively etch to expose the ferroelectric film 20. Next, the upper electrode 23 in contact with the exposed ferroelectric film 20 is formed. In FIG. 1, reference numeral '11' denotes a field oxide film, '12' a gate oxide film, '13' a gate electrode, and '15' a bit line.

상기와 같이 강유전체 캐패시터의 상부전극(23)을 형성한 후, 층간절연막을 형성하여 평탄화를 이루는 과정에서 발생되는 수소는 강유전체막(20)의 표면에 흡착되어 산소 결핍 및 조성 변화를 일으켜 강유전체막의 전기적 특성을 저하시킨다. 종래에, 수소의 확산을 방지하기 위하여 강유전체막 상에 확산방지막으로 실리콘산화막(SiO2)을 형성하고, 실리콘산화막 상에 확산방지산화막으로 TiO2막을 형성하여 보다 효과적으로 수소의 확산을 방지하기 위한 방법이 제시되고 있으나, TiO2막은 스퍼터링(sputtering) 방법으로 형성되기 때문에 층덮힘(step coverage)이 불량하여, 이후 식각 공정여유도를 감소시키며, 또한 SiO2막은 증착 소오스 자체가 수소를 포함하고 있어 수소의 확산 방지에는 한계가 존재한다.After the upper electrode 23 of the ferroelectric capacitor is formed as described above, hydrogen generated in the planarization process by forming the interlayer insulating film is adsorbed on the surface of the ferroelectric film 20 to cause oxygen deficiency and composition change, thereby causing the ferroelectric film to be electrically Decreases the properties. Conventionally, a method for more effectively preventing hydrogen diffusion by forming a silicon oxide film (SiO 2 ) as a diffusion barrier film on the ferroelectric film and a TiO 2 film as a diffusion barrier oxide film on the silicon oxide film to prevent diffusion of hydrogen. However, since TiO 2 film is formed by sputtering method, the step coverage is poor, thereby reducing the etch process margin.SiO 2 film also contains hydrogen because the deposition source itself contains hydrogen. There is a limit to the prevention of diffusion.

또한, (Pb, Zr)TiO(이하 PZT라 함)계열의 물질을 유전막으로 사용하여 캐패시터를 형성할 때, PZT를 이루는 물질과 Ti의 치환이 가능하여 PZT 계열의 유전막상에 TiO2 절연막을 얇게 형성하여 전기적 특성 저하를 방지하는 것이 가능하다. 그러나, SrBi2Ta2O5막으로 이루어지는 강유전체 캐패시터의 확산방지막으로 TiO2막을 형성하면 Ti 금속이 오히려 박막의 내부에 격자간 결함(interstitial defect)으로 존재하다가 그레인 경계(grain boundary)나 결함 부분에 몰려 있다가 산화되거나, 전기장이 인가될 때 박막의 누설전류 경로로 제공되는 등 전기적 특성을 감소시킨다.In addition, when a capacitor is formed using a material of (Pb, Zr) TiO (hereinafter referred to as PZT) series as a dielectric film, the TiO 2 insulating film is thinly formed on the PZT-based dielectric film by allowing the substitution of PZT material and Ti. It is possible to prevent the electrical characteristics deterioration by forming. However, when the TiO 2 film is formed as a diffusion barrier of the ferroelectric capacitor composed of SrBi 2 Ta 2 O 5 film, the Ti metal is rather present as an interstitial defect in the inside of the thin film. It reduces the electrical properties such as being concentrated and oxidized or provided to the leakage current path of the thin film when an electric field is applied.

상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 유전막으로 SrBi2Ta2O5막을 이용하는 강유전체 캐패시터의 특성 저하를 방지할 수 있는 강유전체 캐패시터 형성 방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method of forming a ferroelectric capacitor capable of preventing the degradation of the characteristics of the ferroelectric capacitor using the SrBi 2 Ta 2 O 5 film as a dielectric film.

상기와 같은 목적을 달성하기 위한 본 발명, 반도체 기판 상에 하부전극을 형성하는 단계; 상기 하부전극 상에 SrBixTayOz막을 형성하는 단계; 상부전극과 접할 부분을 제외한 SrBixTayOz막을 둘러싸는 Ta2O5막을 형성하는 단계; 상기 Ta2O5막 상에 TaxNy막을 형성하는 단계; 및 상기 SrBixTayOz막과 접하는 상부전극을 형성하는 단계를 포함하여 이루어지는 강유전체 캐패시터 형성 방법을 제공한다.The present invention for achieving the above object, forming a lower electrode on a semiconductor substrate; Forming an SrBi x Ta y O z film on the lower electrode; Forming a Ta 2 O 5 film surrounding the SrBi x Ta y O z film except for a portion to be in contact with the upper electrode; Forming a Ta x N y film on the Ta 2 O 5 film; And forming an upper electrode in contact with the SrBi x Ta y O z film.

본 발명은 유전막으로 SrBi2Ta2O5막을 이용하는 강유전체 캐패시터의 확산방지막으로, 화학기상증착법으로 증착 가능한 Ta2O5막을 확산방지막으로 형성하여 층덮힘 특성을 향상시키고, 또한, Ta2O5막에 표면에 얇은 TaxNy막을 형성하여 수소의 확산을 효과적으로 방지함으로써 유전막으로 SrBi2Ta2O5막을 이용하는 강유전체 캐패시터 특성 저하를 방지하는 방법이다.The present invention is a diffusion barrier of a ferroelectric capacitor using an SrBi 2 Ta 2 O 5 film as a dielectric film, and a Ta 2 O 5 film that can be deposited by chemical vapor deposition is formed as a diffusion barrier to improve layer covering properties, and further, a Ta 2 O 5 film. A thin Ta x N y film is formed on the surface to effectively prevent the diffusion of hydrogen, thereby preventing the deterioration of ferroelectric capacitor characteristics using the SrBi 2 Ta 2 O 5 film as a dielectric film.

이하, 본 발명의 일실시예에 따른 강유전체 캐패시터 형성 공정 단면도인 도2a 내지 도2c를 참조하여 본 발명의 일실시예를 설명한다.Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 2A to 2C which are cross-sectional views of a ferroelectric capacitor forming process according to an embodiment of the present invention.

먼저, 도2a에 도시한 바와 같이 반도체 기판(30) 상에 형성된 층간절연막(34, 36)을 선택적으로 식각하여 콘택홀을 형성하고, 반도체 기판(30) 전면에 폴리실리콘막을 형성하고 화학적기계적연마법(chemical mechanical polishing)으로 폴리실리콘막을 연마하여 콘택홀을 내에 폴리실리콘 플러그(37)를 형성한 후, 반도체 기판(30) 전면에 장벽금속막으로 Ti막(38)을 형성한 다음, Ti막(38) 상에 하부전극을 형성하기 위하여 Pt막(39)을 형성하고, Pt막(39) 상에 1000 Å 내지 2500 Å 두께의 SrBi2Ta2O5막(40)을 형성한다. 이어서, SrBi2Ta2O5막(40), Pt막(39) 및 Ti막(38)을 패터닝한다.First, as shown in FIG. 2A, a contact hole is formed by selectively etching the interlayer insulating films 34 and 36 formed on the semiconductor substrate 30, a polysilicon film is formed on the entire surface of the semiconductor substrate 30, and a chemical mechanical bond is formed. After polishing the polysilicon film by chemical mechanical polishing to form the polysilicon plug 37 in the contact hole, the Ti film 38 is formed as a barrier metal film on the entire surface of the semiconductor substrate 30, and then the Ti film is formed. A Pt film 39 is formed on the 38 to form a lower electrode, and a SrBi 2 Ta 2 O 5 film 40 having a thickness of 1000 GPa to 2500 GPa is formed on the Pt film 39. Subsequently, the SrBi 2 Ta 2 O 5 film 40, the Pt film 39, and the Ti film 38 are patterned.

다음으로, 도2b에 도시한 바와 같이, 반도체 기판(30) 전면에 층덮힘 특성이 양호한 화학기상증착법(chemical vapor deposition) 방법 또는 플라즈마 화학기상증착법(plasma enhanced chemical vapor deposition)으로 제1 확산방지막인 탄탈륨산화막(tantalum oxide, Ta2O5)(41)을 형성한다. Ta2O5막(41)의 증착 두께는 수소확산방지를 위한 기능을 수행하기 위한 것으로서 200 Å 내지 500 Å 두께가 바람직하다. 상기 Ta2O5막(41)은 탄탈늄에톡사이드[(Ta(OC2H5)5]로 형성하며, 산화제는 O2 또는 N2O이다.Next, as shown in FIG. 2B, the first diffusion barrier layer is formed by a chemical vapor deposition method or a plasma enhanced chemical vapor deposition method having a good layer covering property on the entire surface of the semiconductor substrate 30. Tantalum oxide (Ta 2 O 5 ) 41 is formed. The deposition thickness of the Ta 2 O 5 film 41 is for performing a function for preventing hydrogen diffusion, and the thickness of 200 to 500 mm is preferable. The Ta 2 O 5 film 41 is formed of tantalum ethoxide [(Ta (OC 2 H 5 ) 5 ], and the oxidizing agent is O 2 or N 2 O.

다음으로, 도2c에 도시한 바와 같이 급속열처리(rapid thermal process, RTP)를 실시하여 상기 Ta2O5막(41) 상에 제2 확산방지막인 탄탈륨질화막(tantalum nitride,TaxNy)(42)을 형성한다. 그 형성 두께는 더 효과적으로 수소확산방지를 위한 기능을 수행할 수 있도록 30 Å 내지 50 Å 두께로 하는 것이 바람직하다. TaxNy막(42) 및 Ta2O5막(41)을 선택적으로 식각하여 상부전극이 접합될 SrBi2Ta2O5막(40) 부분을 노출시킨다.Next, as shown in FIG. 2C, a rapid thermal process (RTP) is performed to form a tantalum nitride (Ta x N y ) film as a second diffusion barrier layer on the Ta 2 O 5 film 41 ( 42). The formation thickness is preferably 30 kPa to 50 kPa in order to more effectively perform a function for preventing hydrogen diffusion. The Ta x N y film 42 and the Ta 2 O 5 film 41 are selectively etched to expose a portion of the SrBi 2 Ta 2 O 5 film 40 to which the upper electrode is bonded.

도2a 내지 도2c에서 미설명 도면부호 '31'은 필드산화막, '32'는 게이트 산화막, '33'은 게이트 전극, '35'는 비트라인을 각각 나타낸다.2A to 2C, reference numeral 31 denotes a field oxide film, 32 a gate oxide film, 33 a gate electrode, and 35 a bit line.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

상기와 같이 이루어지는 본 발명은 유전막으로 SrBi2Ta2O5막을 이용하는 강유전체 캐패시터 형성 방법에 있어서, 화학기상증착법으로 증착 가능한 Ta2O5막을 확산방지막으로 형성하여 층덮힘 특성을 향상시키고, 또한, Ta2O5막에 표면에 얇은 TaxNy막을 형성하여 수소의 확산을 보다 효과적으로 방지해서 유전막의 조성 변화를 일으키지 않음으로써 안정된 전기적 특성 및 소자의 신뢰성 향상을 꾀할 수 있다.According to the present invention made of a ferroelectric capacitor forming method using a SrBi 2 Ta 2 O 5 film as a dielectric film, by forming a Ta 2 O 5 film that can be deposited by chemical vapor deposition as a diffusion barrier to improve the layer covering properties, By forming a thin Ta x N y film on the surface of the 2 O 5 film, it is possible to more effectively prevent the diffusion of hydrogen and thereby not to change the composition of the dielectric film, thereby achieving stable electrical characteristics and improving the reliability of the device.

도1은 종래 기술에 따른 강유전체 캐패시터 형성 공정 단면도1 is a cross-sectional view of a ferroelectric capacitor forming process according to the prior art

도2a 내지 도2c는 본 발명의 일실시예에 따른 강유전체 캐패시터 형성 공정 단면도2A through 2C are cross-sectional views of a ferroelectric capacitor forming process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

30: 반도체 기판 31: 필드산화막30: semiconductor substrate 31: field oxide film

32: 게이트 산화막 33: 게이트 전극32: gate oxide film 33: gate electrode

34, 36: 층간절연막 35: 비트라인34, 36: interlayer insulating film 35: bit line

36: 폴리실리콘 플러그 38: Ti막36: polysilicon plug 38: Ti film

39: Pt막 40: SrBi2Ta2O5막39: Pt film 40: SrBi 2 Ta 2 O 5 film

41: Ta2O5막 42: TaNy막41: Ta 2 O 5 film 42: TaN y film

Claims (6)

반도체 기판 상에 하부전극을 형성하는 단계;Forming a lower electrode on the semiconductor substrate; 상기 하부전극 상에 SrBixTayOZ막을 형성하는 단계;Forming an SrBi x Ta y O Z film on the lower electrode; 상부전극과 접할 부분을 제외한 SrBixTayOZ막을 둘러싸는 Ta2O5막을 형성하는 단계;Forming a Ta 2 O 5 film surrounding the SrBi x Ta y O Z film except for a portion to be in contact with the upper electrode; 상기 Ta2O5막 상에 TaxNy막을 형성하는 단계; 및Forming a Ta x N y film on the Ta 2 O 5 film; And 상기 SrBixTayOz막과 접하는 상부전극을 형성하는 단계를 포함하여 이루어지는 강유전체 캐패시터 형성 방법.And forming an upper electrode in contact with the SrBi x Ta y O z film. 제 1 항에 있어서,The method of claim 1, 상기 SrBixTayOz은The SrBi x Ta y O z is SrBi2Ta2O5막으로 형성하는 강유전체 캐패시터 형성 방법.A method of forming a ferroelectric capacitor formed of an SrBi 2 Ta 2 O 5 film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 Ta2O5막은,The Ta 2 O 5 film, 화학기상증착법 방법 또는 플라즈마 화학기상증착법으로 형성하는 강유전체 캐패시터 형성 방법.A method of forming a ferroelectric capacitor formed by a chemical vapor deposition method or a plasma chemical vapor deposition method. 제 3 항에 있어서,The method of claim 3, wherein 상기 Ta2O5막은,The Ta 2 O 5 film, 탄탈늄에톡사이드[(Ta(OC2H5)5]로 형성하는 강유전체 캐패시터 형성 방법.A method of forming a ferroelectric capacitor formed from tantalum ethoxide [[Ta (OC 2 H 5 ) 5 ]. 제 4 항에 있어서,The method of claim 4, wherein 상기 Ta2O5막은,The Ta 2 O 5 film, O2 또는 N2O를 산화제로 사용하여 형성하는 강유전체 캐패시터 형성 방법.A method of forming a ferroelectric capacitor formed by using O 2 or N 2 O as an oxidizing agent. 제 3 항에 있어서,The method of claim 3, wherein 상기 TaxNy막은,The Ta x N y film, 급속열처리에 의해 형성하는 것을 특징으로 하는 강유전체 캐패시터 형성 방법.A method of forming a ferroelectric capacitor, which is formed by rapid heat treatment.
KR1019970077957A 1997-12-30 1997-12-30 Ferroelectric Capacitor Formation Method Expired - Fee Related KR100477835B1 (en)

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