KR100475045B1 - Method for manufacturing metal layer for capacitor electrode of semiconductor device - Google Patents
Method for manufacturing metal layer for capacitor electrode of semiconductor device Download PDFInfo
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- KR100475045B1 KR100475045B1 KR10-1998-0026827A KR19980026827A KR100475045B1 KR 100475045 B1 KR100475045 B1 KR 100475045B1 KR 19980026827 A KR19980026827 A KR 19980026827A KR 100475045 B1 KR100475045 B1 KR 100475045B1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
본 발명의 반도체 소자의 커패시터 전극용 금속층의 제조 방법은, 반도체 기판 상에 콘택 홀을 갖는 제1 절연막을 형성하는 단계와, 제1 절연막의 콘택 홀에 실리콘막을 형성하는 단계와, 제1 절연막 및 실리콘막 상에 제2 절연막을 형성하는 단계와, 제1 절연막의 일부 및 실리콘막이 노출되도록 제2 절연막을 식각하는 단계와, 제1 및 제2 절연막과 실리콘막의 노출 표면상에 반구형 그레인 실리콘막을 형성하는 단계와, 반구형 그레인 실리콘막이 덮여지도록 금속층을 형성하는 단계와, 제2 절연막 상부에 형성되어 있는 금속층과 반구형 그레인 실리콘막을 제거하는 단계와, 제2 절연막을 제거하는 단계, 및 금속층의 측면에 노출된 반구형 그레인 실리콘막을 제거하는 단계를 포함한다.A method of manufacturing a capacitor electrode metal layer of a semiconductor device of the present invention includes the steps of forming a first insulating film having a contact hole on a semiconductor substrate, forming a silicon film in a contact hole of the first insulating film, a first insulating film and Forming a second insulating film on the silicon film, etching the second insulating film to expose a portion of the first insulating film and the silicon film, and forming a hemispherical grain silicon film on the exposed surfaces of the first and second insulating films and the silicon film. Forming a metal layer to cover the hemispherical grain silicon film; removing the metal layer and the hemispherical grain silicon film formed on the second insulating film; removing the second insulating film; and exposing the metal layer to the side surface. Removing the hemispherical grain silicon film.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 상세하게는 반도체 소자의 커패시터 전극용 금속층의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for producing a metal layer for a capacitor electrode of a semiconductor device.
DRAM(Dynamic Random Access Memory) 장치에 있어서, 셀 커패시턴스의 증가는 메모리 셀의 독출능력을 향상시키고 소프트 에러율을 감소시키는 역할을 하므로 셀의 메모리 특성을 향상시키는데 크게 기여한다. 그러나 반도체 소자의 집적도가 점차 증가함에 따라 하나의 칩에서 단위 셀이 차지하는 면적이 줄어들게 되어, 결과적으로 셀 커패시터의 영역 감소를 초래하였으므로, 집적도의 증가와 더불어 단위 면적에 확보되어야 할 셀 커패시턴스의 증가가 필수적인 상황이다. 따라서, 셀 커패시턴스를 증가시키기 위한 많은 연구 보고들이 계속되어 왔는데, 이들의 대부분은 셀 커패시터를 구성하는 하부 전극의 표면을 극대화하고, 고유전막을 사용하는 방법이다. 이 중에서, 하부 전극에 반구형 그레인(HemiSpherical Grain; 이하 HSG)의 실리콘막을 사용하여 전극의 표면적을 증가시키고, Ta2O5(비유전율=25)와 같은 고유전 물질로 형성된 유전막을 사용하는 방법이 주로 사용된다.In a DRAM (Dynamic Random Access Memory) device, the increase in cell capacitance contributes to improving the memory characteristics of the cell because it increases the readability of the memory cell and reduces the soft error rate. However, as the degree of integration of semiconductor devices gradually increases, the area occupied by a unit cell in one chip is reduced, resulting in a decrease in the area of a cell capacitor. As a result, an increase in the density and an increase in cell capacitance that must be secured in a unit area are caused. It is an essential situation. Therefore, many studies have been conducted to increase cell capacitance, most of which are methods of maximizing the surface of the lower electrode constituting the cell capacitor and using a high dielectric film. Among these, a method of using a dielectric film formed of a high dielectric material such as Ta 2 O 5 (relative dielectric constant = 25) to increase the surface area of the electrode by using a silicon film of hemispherical grain (HSG) for the lower electrode is disclosed. Mainly used.
이와 같이 유전막인 Ta2O5막과 하부 전극으로서 HSG의 실리콘막을 사용하는 경우에는, Ta2O5막과 실리콘과의 반응을 억제하기 위한 실리콘질화막의 사용이 필수적이다. 그런데, 이 실리콘질화막의 비유전율은 7로서 Ta2O5막에 비해 작으며, 따라서 전체 커패시터의 용량을 감소시킨다. 또한, Ta2O5막 증착 후의 후속 공정인 산화 공정, 예컨대 건식 산화 공정시에는 반응 억제막인 실리콘질화막과 실리콘막의 계면에서 산화막(비유전율=3.9)이 형성되어 전체 커패시터의 용량은 더욱 낮아진다.As described above, when using the Ta 2 O 5 film as the dielectric film and the HSG silicon film as the lower electrode, the use of a silicon nitride film for suppressing the reaction between the Ta 2 O 5 film and silicon is essential. However, the dielectric constant of this silicon nitride film is 7, which is smaller than that of the Ta 2 O 5 film, thus reducing the capacity of the entire capacitor. In addition, during the oxidation process, for example, a dry oxidation process after the Ta 2 O 5 film deposition, an oxide film (a dielectric constant = 3.9) is formed at the interface between the silicon nitride film and the silicon film, which is a reaction suppressing film, so that the capacity of the entire capacitor is further lowered.
이와 같은 문제점을 해결하기 위하여, 하부 전극으로서 금속층을 이용하는 방법이 제안된 바 있다. 그러나 하부 전극으로서 금속층을 이용하는 경우에는 하부 전극 표면에 HSG의 실리콘막을 형성하기가 어렵다는 문제가 있다.In order to solve this problem, a method of using a metal layer as a lower electrode has been proposed. However, when the metal layer is used as the lower electrode, it is difficult to form a silicon film of HSG on the lower electrode surface.
본 발명은 상기와 같은 문제점을 개선하기 위하여 창출된 것으로서, 반도체 소자의 커패시터 전극으로서 금속층을 이용하면서 그 표면에 HSG의 실리콘막에 의한 표면적 증가 효과를 얻을 수 있는 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and using a metal layer as a capacitor electrode of a semiconductor device, the metal layer for the capacitor electrode of the semiconductor device can obtain the surface area increase effect of the silicon film of HSG on the surface thereof The purpose is to provide a method.
상기 목적을 달성하기 위하여 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법은, (가) 반도체 기판 상에 콘택 홀을 갖는 제1 절연막을 형성하는 단계; (나) 상기 제1 절연막의 콘택 홀에 실리콘막을 형성하는 단계; (다) 상기 제1 절연막 및 실리콘막 상에 제2 절연막을 형성하는 단계; (라) 상기 제1 절연막의 일부 및 상기 실리콘막이 노출되도록 상기 제2 절연막을 식각하는 단계; (마) 상기 제1 및 제2 절연막과 상기 실리콘막의 노출 표면상에 반구형 그레인 실리콘막을 형성하는 단계; (바) 상기 반구형 그레인 실리콘막이 덮여지도록 금속층을 형성하는 단계; (사) 상기 제2 절연막 상부에 형성되어 있는 금속층과 반구형 그레인 실리콘막을 제거하는 단계; (아) 상기 제2 절연막을 제거하는 단계; 및 (자) 상기 금속층의 측면에 노출된 반구형 그레인 실리콘막을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to the present invention includes the steps of: (a) forming a first insulating film having a contact hole on a semiconductor substrate; (B) forming a silicon film in the contact hole of the first insulating film; (C) forming a second insulating film on the first insulating film and the silicon film; (D) etching the second insulating film to expose a portion of the first insulating film and the silicon film; (E) forming a hemispherical grain silicon film on the exposed surfaces of the first and second insulating films and the silicon film; (F) forming a metal layer to cover the hemispherical grain silicon film; (G) removing the metal layer and the hemispherical grain silicon film formed on the second insulating film; (H) removing the second insulating film; And (i) removing the hemispherical grain silicon film exposed on the side of the metal layer.
본 발명에 있어서, 상기 단계 (라)가 수행된 후에 상기 일부 노출된 실리콘막 상에 금속 실리사이드층을 형성시키는 단계를 더 포함하는 것이 바람직하며, 상기 반구형 그레인 실리콘에 불순물을 도핑하는 단계를 더 포함하는 것이 바람직하다.In the present invention, after the step (d) is performed, the method further comprises the step of forming a metal silicide layer on the partially exposed silicon film, and further comprising the step of doping impurities into the hemispherical grain silicon. It is desirable to.
상기 목적을 달성하기 위하여 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법은, (가) 반도체 기판 상에 제1 및 제2 절연막을 순차적으로 형성하는 단계; (나) 상기 제2 절연막의 커패시터 전극이 형성될 영역을 식각하는 단계; (다) 상기 제1 절연막의 일정 영역을 식각하여 콘택 홀을 형성하는 단계; (라) 상기 제1 및 제2 절연막의 노출 표면상에 반구형 그레인 실리콘막을 형성하는 단계; (마) 상기 반구형 그레인 실리콘막이 덮여지도록 금속층을 형성하되, 상기 제1 절연막 사이의 콘택 홀 내에는 상기 금속이 채워지도록 하는 단계; (바) 상기 제2 절연막 상부에 형성되어 있는 금속층 및 반구형 그레인 실리콘막을 제거하는 단계; (사) 상기 제2 절연막을 제거하는 단계; 및 (아) 상기 금속층의 측면에 형성된 반구형 그레인 실리콘막을 제거하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to the present invention includes: (a) sequentially forming a first and a second insulating film on a semiconductor substrate; (B) etching the region where the capacitor electrode of the second insulating layer is to be formed; (C) forming a contact hole by etching a predetermined region of the first insulating film; (D) forming a hemispherical grain silicon film on the exposed surfaces of said first and second insulating films; (E) forming a metal layer to cover the hemispherical grain silicon film, wherein the metal is filled in a contact hole between the first insulating film; (F) removing the metal layer and the hemispherical grain silicon film formed on the second insulating film; (G) removing the second insulating film; And (h) removing the hemispherical grain silicon film formed on the side of the metal layer.
이와 같은 본 발명에 따르면, 반도체 소자의 커패시터 전극으로서 금속층을 이용하면서 그 표면에 HSG의 실리콘막에 의한 표면적 증가 효과를 얻을 수 있다.According to the present invention as described above, it is possible to obtain the effect of increasing the surface area of the HSG silicon film on the surface while using the metal layer as the capacitor electrode of the semiconductor element.
이하, 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 6은 본 발명에 따른 커패시터 전극용 금속층의 제조 방법을 단계별 공정에 따라 나타내 보인 단면도들이다.1 to 6 are cross-sectional views illustrating a method of manufacturing a metal layer for a capacitor electrode according to the present invention according to a step-by-step process.
도 1을 참조하면, 먼저 커패시터 전극용 금속층을 형성하고자 하는 반도체 기판, 예컨대 실리콘 기판(100) 상에 제1 절연막(110)을 형성한다. 제1 절연막(110)은 층간 절연막으로서 실리콘 산화막이다. 다음에, 제1 절연막(110)의 일정 영역, 즉 스토리지 콘택 홀이 형성될 영역을 식각하여 스토리지 콘택 홀을 형성한다. 그리고, 스토리지 콘택 홀에 실리콘막(120)을 형성한다. 이 때, 실리콘막(120)은 비정질 실리콘막이다. 실리콘막(120)을 형성하기 위하여, 스토리지 콘택 홀 및 제1 절연막(110) 상에 실리콘막(120)을 증착한 후, 제1 절연막(110)이 노출될 때까지 에치백(etchback) 또는 화학 기계적 연마(Chemical Mechanical Polishing; 이하 CMP) 공정을 수행한다.Referring to FIG. 1, first, a first insulating layer 110 is formed on a semiconductor substrate, for example, a silicon substrate 100, on which a metal layer for capacitor electrodes is to be formed. The first insulating film 110 is a silicon oxide film as an interlayer insulating film. Next, a predetermined region of the first insulating layer 110, that is, a region where the storage contact hole is to be formed is etched to form a storage contact hole. The silicon film 120 is formed in the storage contact hole. At this time, the silicon film 120 is an amorphous silicon film. In order to form the silicon film 120, the silicon film 120 is deposited on the storage contact hole and the first insulating film 110, and then etchback or chemical until the first insulating film 110 is exposed. Mechanical Mechanical Polishing (CMP) process is performed.
다음에, 도 2를 참조하면, 제1 절연막(110) 및 실리콘막(120)의 노출 부분 상에 제2 절연막(130)을 형성한다. 제2 절연막(130)으로서 실리콘 산화막을 사용할 수 있다. 다음에, 제2 절연막(130)의 커패시터 전극이 형성될 영역을 식각하여 제1 절연막(110)의 일부 및 실리콘막(120)의 표면이 노출되도록 한다.Next, referring to FIG. 2, a second insulating film 130 is formed on the exposed portions of the first insulating film 110 and the silicon film 120. A silicon oxide film may be used as the second insulating film 130. Next, an area in which the capacitor electrode of the second insulating layer 130 is to be formed is etched to expose a part of the first insulating layer 110 and the surface of the silicon layer 120.
다음에, 도 3을 참조하면, 제1 및 제2 절연막(110, 130)과 실리콘막(120)의 노출 표면상에 HSG 실리콘막(150)을 형성한다. 이를 위하여, 제2 절연막(130) 및 제1 절연막(110)과 실리콘막(120)의 노출 부분에 비정질 실리콘 박막(미도시)을 형성한다. 그리고 실리콘을 포함한 반응 가스, 예컨대 다이사일레인(Si2H6) 또는 사일레인(SiH4) 가스를 일정 온도 및 일정 시간 동안 공급한 후, 반응 가스 공급을 중단하고 일정 시간동안 열처리 공정을 수행한다. 그러면, HSG 실리콘막(150)이 형성된다. 다른 방법으로서, 실리콘을 포함한 반응 가스, 예컨대 다이사일레인(Si2H6) 또는 사일레인(SiH4) 가스를 일정 시간 이상동안 공급한다. 이와 같은 공정을 일정 시간 이상동안 수행하면, HSG 실리콘막(150)이 형성된다. HSG 실리콘막(150)을 형성한 후, 금속층(160)의 하부에 형성된 HSG 실리콘막(150)과 실리콘막(120) 사이의 오믹 접촉 특성을 향상시키기 위해 HSG 실리콘막(150)을 불순물로 도핑시킬 수 있다. 이 경우에, 불순물로서 인(P)을 사용하는 것이 바람직하다.Next, referring to FIG. 3, the HSG silicon film 150 is formed on the exposed surfaces of the first and second insulating films 110 and 130 and the silicon film 120. To this end, an amorphous silicon thin film (not shown) is formed on the exposed portions of the second insulating film 130, the first insulating film 110, and the silicon film 120. Then, after supplying a reaction gas containing silicon, such as disilane (Si 2 H 6 ) or silane (SiH 4 ) gas for a predetermined temperature and for a predetermined time, the supply of the reaction gas is stopped and a heat treatment is performed for a predetermined time. . As a result, the HSG silicon film 150 is formed. Alternatively, a reactant gas containing silicon, such as disilane (Si 2 H 6 ) or silane (SiH 4 ) gas, is supplied for a period of time or longer. When such a process is performed for a predetermined time or more, the HSG silicon film 150 is formed. After the HSG silicon film 150 is formed, the HSG silicon film 150 is doped with impurities to improve ohmic contact between the HSG silicon film 150 and the silicon film 120 formed under the metal layer 160. You can. In this case, it is preferable to use phosphorus (P) as an impurity.
다음에, 도 4를 참조하면, HSG 실리콘막(150)이 덮여지도록 금속층(160)을 형성한다. 상기 금속층(160)은 통상의 증착법을 사용하여 형성시킬 수 있으며, 커패시터의 하부 전극으로 사용될 수 있다.Next, referring to FIG. 4, the metal layer 160 is formed to cover the HSG silicon film 150. The metal layer 160 may be formed using a conventional deposition method, and may be used as a lower electrode of a capacitor.
다음에, 도 5를 참조하면, CMP 공정 또는 에치백 공정을 수행하여 제2 절연막(130) 상의 금속층(160) 및 HSG 실리콘막(150)을 제거한다.Next, referring to FIG. 5, the metal layer 160 and the HSG silicon film 150 on the second insulating film 130 are removed by performing a CMP process or an etch back process.
다음에, 도 6을 참조하면, 제2 절연막(130)을 제거하고, 이어서 금속층(160)의 측면에 노출된 HSG 실리콘막(150)을 제거한다. 그러면, 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층이 완성된다.Next, referring to FIG. 6, the second insulating film 130 is removed, and then the HSG silicon film 150 exposed to the side surface of the metal layer 160 is removed. Then, the metal layer for the capacitor electrode of the semiconductor device according to the present invention is completed.
한편, 제2 절연막(130) 상의 금속층(160) 및 HSG 실리콘막(150)을 제거할 때(도 5참조), CMP 공정 또는 에치백 공정에 따른 하부막의 충격을 완화하기 위하여 금속층 내부에 소정의 물질을 채운 상태에서 CMP 공정 또는 에치백 공정을 수행하는 것이 바람직하다. 이를 도 7 및 도 8을 참조하여 설명하면 다음과 같다.Meanwhile, when removing the metal layer 160 and the HSG silicon film 150 on the second insulating film 130 (refer to FIG. 5), a predetermined inside of the metal layer may be predetermined to alleviate the impact of the lower film according to the CMP process or the etch back process. It is preferable to carry out the CMP process or the etch back process with the material filled. This will be described with reference to FIGS. 7 and 8 as follows.
먼저, 도 7에 도시된 바와 같이, HSG 실리콘막(150)이 덮여지도록 금속층(160)을 형성한 후에(도 4 참조), 금속층(160) 내부에 포토레지스트 또는 실리콘 온 글라스(170)를 채운다. 그리고, 도 8에 도시된 바와 같이, CMP 공정 또는 에치백 공정을 수행하여 제2 절연막(130) 상의 금속층(160) 및 HSG 실리콘막(150)을 제거한다. CMP 공정 또는 에치백 공정이 완료되면, 금속층(160) 내부의 포토레지스트 또는 실리콘 온 글라스(170)를 제거한다. 이후의 공정은 앞서 설명한 바와 같다.First, as shown in FIG. 7, after forming the metal layer 160 to cover the HSG silicon film 150 (see FIG. 4), the photoresist or silicon on glass 170 is filled in the metal layer 160. . As shown in FIG. 8, the metal layer 160 and the HSG silicon layer 150 on the second insulating layer 130 are removed by performing a CMP process or an etch back process. When the CMP process or the etch back process is completed, the photoresist or silicon on glass 170 inside the metal layer 160 is removed. The subsequent process is as described above.
도 9 내지 도 14는 본 발명의 다른 실시예에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 단계별 공정에 따라 개략적으로 나타내 보 인 단면도들이다. 본 실시예에서는, 실리콘막 및 금속층과 HSG 실리콘막 사이의 오믹 접촉 특성을 향상시키기 위하여, 그 사이에 금속 실리사이드층을 형성시키는 점에서 앞서 설명한 방법과 다르다. 이를 보다 상세히 설명하면 다음과 같다.9 to 14 are cross-sectional views schematically illustrating a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to another exemplary embodiment of the present inventive concept. This embodiment differs from the method described above in that a metal silicide layer is formed therebetween in order to improve ohmic contact characteristics between the silicon film and the metal layer and the HSG silicon film. This will be described in more detail as follows.
먼저, 도 9를 참조하면, 먼저 커패시터 전극용 금속층을 형성하고자 하는 반도체 기판, 예컨대 실리콘 기판(200) 상에 제1 절연막(210)을 형성한다. 제1 절연막(210)은 층간 절연막으로서 실리콘 산화막이다. 다음에, 제1 절연막(210)의 일정 영역, 즉 스토리지 콘택 홀이 형성될 영역을 식각하여 스토리지 콘택 홀을 형성한다. 그리고, 스토리지 콘택 홀에 실리콘막(220)을 채운다. 이 때, 실리콘막(220)은 비정질 실리콘이다. 실리콘막(220)을 형성하기 위하여, 스토리지 콘택 홀 및 제1 절연막(210) 상에 실리콘막(220)을 증착한 후, 제1 절연막(210)이 노출될 때까지 에치백(etchback) 또는 화학 기계적 연마(Chemical Mechanical Polishing; 이하 CMP) 공정을 수행한다.First, referring to FIG. 9, first, a first insulating layer 210 is formed on a semiconductor substrate, for example, a silicon substrate 200, on which a metal layer for capacitor electrodes is to be formed. The first insulating film 210 is a silicon oxide film as an interlayer insulating film. Next, a predetermined region of the first insulating layer 210, that is, a region where the storage contact hole is to be formed is etched to form a storage contact hole. Then, the silicon film 220 is filled in the storage contact hole. At this time, the silicon film 220 is amorphous silicon. In order to form the silicon layer 220, the silicon layer 220 is deposited on the storage contact hole and the first insulating layer 210, and then etchback or chemical until the first insulating layer 210 is exposed. Mechanical Mechanical Polishing (CMP) process is performed.
다음에, 도 10을 참조하면, 제1 절연막(210) 및 실리콘막(220)의 노출 부분 상에 제2 절연막(230)을 형성한다. 제2 절연막(230)으로서 실리콘 산화막을 사용할 수 있다. 다음에, 제2 절연막(230)의 커패시터 전극이 형성될 영역을 식각하여 제1 절연막(210)의 일부 및 실리콘막(220)의 표면이 노출되도록 한다.Next, referring to FIG. 10, a second insulating film 230 is formed on the exposed portions of the first insulating film 210 and the silicon film 220. A silicon oxide film can be used as the second insulating film 230. Next, an area in which the capacitor electrode of the second insulating layer 230 is to be formed is etched to expose a portion of the first insulating layer 210 and the surface of the silicon layer 220.
다음에, 도 11을 참조하면, 실리콘막(220)의 표면에 금속 실리사이드층(240)을 형성시킨다. 금속 실리사이드층(240)을 형성시키는 이유는 실리콘막(220)과 후속 공정에 의해 형성되는 HSG 실리콘막(250) 및 금속층(260)과의 오믹 접촉 특성을 향상시키기 위한 것이다.Next, referring to FIG. 11, a metal silicide layer 240 is formed on the surface of the silicon film 220. The reason for forming the metal silicide layer 240 is to improve ohmic contact characteristics between the silicon film 220 and the HSG silicon film 250 and the metal layer 260 formed by a subsequent process.
다음에, 도 12를 참조하면, 제1 및 제2 절연막(210, 230)과 금속 실리사이드층(240) 상에 HSG 실리콘막(250)을 형성한다. HSG 실리콘막(250)을 형성시키는 방법은 앞서 설명한 바와 같다.Next, referring to FIG. 12, the HSG silicon film 250 is formed on the first and second insulating films 210 and 230 and the metal silicide layer 240. The method of forming the HSG silicon film 250 is as described above.
다음에, 도 13을 참조하면, HSG 실리콘막(250)이 덮여지도록 금속층(260)을 형성한다. 상기 금속층(260)은 통상의 증착법을 사용하여 형성시킬 수 있으며, 커패시터의 하부 전극으로 사용될 수 있다.Next, referring to FIG. 13, the metal layer 260 is formed to cover the HSG silicon film 250. The metal layer 260 may be formed using a conventional deposition method, and may be used as a lower electrode of a capacitor.
다음에, 도 14를 참조하면, CMP 공정 또는 에치백 공정을 수행하여 제2 절연막(230) 상의 금속층(260) 및 HSG 실리콘막(250)을 제거한다.Next, referring to FIG. 14, the metal layer 260 and the HSG silicon film 250 on the second insulating film 230 are removed by performing a CMP process or an etch back process.
다음에, 도 15를 참조하면, 제2 절연막(230)을 제거하고, 이어서 금속층(260)의 측면에 노출된 HSG 실리콘막(250)을 제거한다. 그러면, 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층이 완성된다.Next, referring to FIG. 15, the second insulating film 230 is removed, and then the HSG silicon film 250 exposed to the side surface of the metal layer 260 is removed. Then, the metal layer for the capacitor electrode of the semiconductor device according to the present invention is completed.
한편, 도 16 내지 도 20은 본 발명의 또 다른 실시예에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 단계별 공정에 따라 개략적으로 나타내 보인 단면도들이다. 본 실시예에서는, 스토리지 콘택 홀상에 실리콘막을 형성하지 않고 금속층 및 HSG 실리콘막을 형성한다는 점에서 앞서 설명한 실시예와 다르다. 이를 보다 상세히 설명하면 다음과 같다.16 to 20 are cross-sectional views schematically illustrating a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to another exemplary embodiment of the present inventive concept. This embodiment differs from the above-described embodiment in that a metal layer and an HSG silicon film are formed without forming a silicon film on the storage contact hole. This will be described in more detail as follows.
먼저, 도 16을 참조하면, 먼저 커패시터 전극용 금속층을 형성하고자 하는 반도체 기판, 즉 실리콘 기판(300) 상에 제1 및 제2 절연막(310)(330)을 순차적으로 형성한다. 제1 및 제2 절연막(310)은 실리콘 산화막이다.First, referring to FIG. 16, first and second insulating layers 310 and 330 are sequentially formed on a semiconductor substrate, that is, a silicon substrate 300 on which a metal layer for capacitor electrodes is to be formed. The first and second insulating films 310 are silicon oxide films.
다음에, 도 17을 참조하면, 제2 절연막(330)의 커패시터 전극이 형성될 영역을 식각한 후, 제1 절연막(310)의 일정 영역, 즉 스토리지 콘택 홀이 형성될 영역을 식각하여 스토리지 콘택 홀을 형성한다.Next, referring to FIG. 17, after etching the region where the capacitor electrode of the second insulating layer 330 is to be formed, a predetermined region of the first insulating layer 310, that is, the region where the storage contact hole is to be formed, is etched. Form a hole.
다음에 도 18을 참조하면, 제1 및 제2 절연막(310)(330)의 노출 표면상에 HSG 실리콘막(350)을 형성한다. HSG 실리콘막(350)을 형성시키는 방법은 앞서 설명한 바와 같다. 그리고 상기 HSG 실리콘막(350)이 덮여지도록 금속층(360)을 형성한다. 이 때, 제1 절연막(310) 사이의 콘택 홀 내에는 상기 금속이 채워지도록 한다.Next, referring to FIG. 18, the HSG silicon film 350 is formed on the exposed surfaces of the first and second insulating films 310 and 330. The method of forming the HSG silicon film 350 is as described above. The metal layer 360 is formed to cover the HSG silicon film 350. In this case, the metal is filled in the contact hole between the first insulating layer 310.
다음에 도 19를 참조하면, CMP 공정 또는 에치백 공정을 수행하여 제2 절연막(330) 상의 금속층(360) 및 HSG 실리콘막(350)을 제거한다.Next, referring to FIG. 19, the CMP process or the etch back process is performed to remove the metal layer 360 and the HSG silicon film 350 on the second insulating film 330.
다음에, 도 20을 참조하면, 제2 절연막(330) 상의 금속층(360) 및 HSG 실리콘막(350)을 먼저 제거한다. 그리고 제2 절연막(330)을 제거하고, 이어서 금속층(360)의 노출된 측면에 형성된 HSG 실리콘막(350)을 제거한다. 그러면, 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층이 완성된다.Next, referring to FIG. 20, the metal layer 360 and the HSG silicon film 350 on the second insulating film 330 are first removed. The second insulating layer 330 is removed, and then the HSG silicon film 350 formed on the exposed side surface of the metal layer 360 is removed. Then, the metal layer for the capacitor electrode of the semiconductor device according to the present invention is completed.
이상, 본 발명을 바람직한 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않으며, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러가지 변형이 가능하다.In the above, the present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. Do.
이상의 설명에서와 같이, 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법에 의하면, 반도체 소자의 커패시터 전극, 특히 하부 전극으로서 금속층을 사용할 수 있으므로, 실리콘산화막이 불필요하고, 이에 따라 전체 커패시턴스가 감소하지 않는다. 또한, 금속층의 표면에 HSG의 실리콘막을 형성시킬 수 있으므로 표면적 증가 효과를 얻을 수 있다는 이점이 있다.As described above, according to the method of manufacturing the capacitor electrode metal layer of the semiconductor device according to the present invention, since the metal layer can be used as the capacitor electrode, in particular the lower electrode of the semiconductor device, the silicon oxide film is unnecessary, so that the total capacitance is Does not decrease. In addition, since the silicon film of HSG can be formed on the surface of the metal layer, there is an advantage that the surface area increase effect can be obtained.
도 1 내지 도 6은 본 발명의 실시예에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 개략적으로 나타내 보인 단면도들이다.1 to 6 are cross-sectional views schematically illustrating a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to an exemplary embodiment of the present invention.
도 7 및 도 8은 본 발명에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법에 있어서의 CMP 공정 또는 에치백 공정을 효과적으로 수행하기 위한 방법을 설명하기 위한 단면도이다.7 and 8 are cross-sectional views for explaining a method for effectively performing a CMP process or an etch back process in a method of manufacturing a capacitor electrode metal layer of a semiconductor device according to the present invention.
도 9 내지 도 15는 본 발명의 다른 실시예에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 개략적으로 나타내 보인 단면도들이다.9 to 15 are cross-sectional views schematically illustrating a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to another exemplary embodiment of the present invention.
도 16 내지 도 20은 본 발명의 또 다른 실시예에 따른 반도체 소자의 커패시터 전극용 금속층의 제조 방법을 개략적으로 나타내 보인 단면도들이다.16 to 20 are cross-sectional views schematically illustrating a method of manufacturing a metal layer for a capacitor electrode of a semiconductor device according to still another embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
100, 200, 300...실리콘 기판 110, 210, 310...제1 절연막100, 200, 300 ... silicon substrate 110, 210, 310 ... first insulating film
120, 220...실리콘막 130, 230, 330...제2 절연막120, 220 ... silicon film 130, 230, 330 ... second insulating film
240...금속 실리사이드층 150, 250, 350...HSG 실리콘막240 ... metal silicide layer 150, 250, 350 ... HSG silicon film
160, 260, 360...금속층160, 260, 360 ... metal layer
170...포토레지스트 또는 실리콘 온 글라스170.Photoresist or silicon on glass
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