KR100473237B1 - Thin film transistor and method for fabricating the same, and liquid crystal display comprising the same - Google Patents

Abstract

The present invention provides a thin film transistor which suppresses OFF current (photoconductive current) during light irradiation and realizes high performance and high reliability.

That is, it has a polycrystalline silicon semiconductor layer having a channel region and source and drain regions disposed on both sides of the channel region, and a depletion layer is formed between the channel region and the drain region. It has a proportional relationship with the width of the pip layer and the photoconductive current generated when light is irradiated to the channel region, and the width of the depletion layer is less than or equal to the width obtained based on the proportional relationship in order to keep the photoconductive current within a predetermined allowable value. A thin film transistor having one configuration is provided.

Description

Thin film transistor, its manufacturing method and liquid crystal display device using the same {THIN FILM TRANSISTOR AND METHOD FOR FABRICATING THE SAME, AND LIQUID CRYSTAL DISPLAY COMPRISING THE SAME}

The present invention relates to a thin film transistor, a method for manufacturing the same, and a liquid crystal display device using the same.

(First background)

Conventionally, the driving performance of a pixel of an active matrix type liquid crystal display device formed of amorphous silicon (hereinafter referred to as "a-Si") is sufficiently satisfied with a-Si, but the signal lines are provided by the same process on the same substrate. It is difficult in performance to construct a drive circuit, and the panel is driven using an external drive circuit (driver) composed of single crystal Si.

However, the mobility of a-Si is 0.5 to ¹ cm ² · s ⁻¹ · V ⁻¹ , and when the number of pixels of the liquid crystal panel increases in the future, the time for turning on the TFT of pixels corresponding to a maximum of one horizontal period is generally Is gradually shortened, and the writing capability to the pixel is insufficient.

On the other hand, since the TFT of the pixel is made of polysilicon (hereinafter referred to as "p-Si"), the mobility of the TFT is higher than one to two digits compared with the case of a-Si, The charging capacity is increased.

Therefore, it is advantageous to form the pixel TFT as p-Si as the resolution of the liquid crystal panel is advanced (FPD Expo Forum 97, 2-14).

In general, as the structure of p-SiTFT, there are two types of top gate type in which the gate electrode is located above the channel layer, and bottom gate type in which the gate electrode is present on the substrate side with respect to the channel layer.

Compared with the bottom gate type structure, the top gate type structure is capable of producing a TFT with a small parasitic capacitance by self-doped impurities with a gate electrode as a mask, and is advantageous for miniaturization.

When the top gate type TFT is applied to, for example, a liquid crystal display, and the light is irradiated from the rear surface of the TFT, the light of the backlight is directly irradiated to the channel region of the TFT.

When light is irradiated to the channel region, there is a problem that a photoconductive current is generated in this portion and the OFF current is increased. Here, "photoconductive current" is demonstrated.

The mechanism of generating photoconductive current in semiconductors has been introduced in many papers (e.g., Tanaka Kazunori, 1982), based on solar cells, but photoelectricity in p-SiTFT. There is little discussion about the mechanism of generation of conduction current.

In general, generation of a photoconductive current generates electrons / hole bands through a band gap in a state where an electric field is applied, and the generated electrons / hole bands drift by an electric field, An increase in the number of carriers in each region is observed in the form of a carrier recombination current.

In the channel region under the gate electrode, holes are induced directly under the channel under reverse bias conditions, but the concentration of the carrier is very low. On the other hand, the electron which is the majority carrier on the drain side is estimated to have a carrier density of about 10 ¹⁶ / cm ³ to 10 ¹⁸ / cm ^{3 in} the range of 20 kΩ / □ to 100 kΩ / □ of sheet resistance in the n-region.

In this case, electrons, which are the majority carriers in the n-region, are diffused toward the channel side to form the diffusion potential Vd. In addition, the width of the depletion layer is represented by Wd.

Irradiation with light generates electron / hole bands in this depleted region. The generated electron / hole bands are attracted to each other by the electric field, and the electrons move in the drain direction and the holes move in the channel direction.

The electrons moved to the drain side and the holes moved to the channel side recombine and disappear in each region. The charge consumed for this recombination is supplied by the source and drain electrodes, respectively, which is observed as the photoconductive current.

When the OFF current is increased (degradation of the OFF characteristic) by the above photoconductive current, the following problem occurs.

Image quality deterioration caused by deterioration of the off characteristic is a luminance gradient and crosstalk. The luminance inclination is caused by the difference in the current / luminance characteristics of the liquid crystals in the upper and lower portions of the screen, as shown in Fig. 38A, and the difference in luminance occurs in the upper and lower portions of the screen.

On the other hand, crosstalk is a phenomenon in which a black image pulls its tail up and down or left and right in the case where a black box pattern is displayed at the center of white as shown in FIG. 38B.

In addition, the deterioration of the off characteristic has a great influence on the image quality such as increase in flicker and occurrence of luminance unevenness.

(Second background)

In addition, since p-SiTFT has high mobility, it is possible to simultaneously form part or all of the active matrix element and the signal driver circuit in the screen on the glass substrate.

However, p-SiTFT has a problem that the OFF current is larger than that of a-SiTFT or MOS type field effect transistor.

Thus, as disclosed in Japanese Patent Laid-Open No. 5 (1993) -136417 for reducing the OFF current, a low concentration impurity region (LDD region) is formed adjacent to at least one of the source region and the drain region of the TFT. The formation method is performed (1st conventional method).

As another method of forming the LDD region, a method (Euro Display'96 pp547) for controlling the LDD region in accordance with the presence or absence of TaOx is disclosed (second conventional method).

Mechanisms in which the LDD region is effective for reducing OFF current are described in Japanese Patent Laid-Open No. 5 (1993) -136417. Since the LDD region has a high resistance to the drain region, the junction portion of the channel / LDD region It is considered that the applied electric field becomes smaller with respect to the case where the LDD region is not formed.

In the above two methods, either method controls the presence or absence of TaOx by mask-aligning the LDD region or controls the presence or absence of a resist film to form portions having different doping concentrations.

In this method, in order to secure the LDD area reliably, the length of the LDD area must be secured to a length equal to or greater than the dimensional accuracy of the mask fitting.

On the other hand, as shown in Japanese Patent Laid-Open No. Hei 7 (1995) -140485, there is a third conventional method of self-aligning the LDD region with respect to the gate electrode.

In this method, an oxide layer of Al is formed on the side surface by anodizing Al serving as a gate electrode, and an N-type or P-type impurity element is introduced as a mask, and the source layer, the drain region and the oxide layer on the side surface are introduced. It is possible to create a low concentration impurity layer having a thickness almost equal to.

By using this method, it is possible to form LDD regions in a self-aligned manner with respect to the gate electrode, to reduce the mask for forming the LDD regions, and at the same time to anodicize the length of the region with high impurity concentration. It is possible to form very small about 0.1 micrometer-0.5 micrometer corresponded to the film thickness of the oxide which exists in the process.

The LDD structure is effective in reducing OFF current. However, in the ON state in which the channel under the gate electrode of the TFT is inverted, the LDD region, which is a relatively high resistance layer, is inserted in the channel region in series, thereby reducing the ON current. Have.

originally. The LDD region has a high resistance to the portions of the source and drain regions, and the influence of the resistance tends to be remarkable as the characteristics of the TFT become higher.

Therefore, the length of the LDD region, which is a high resistance region, should be sufficient to reduce the OFF current and have a resistance value sufficiently low to secure a high ON current.

However, in the present situation, there is no method of determining the guide of the length of the LDD region, and it is necessary to secure the LDD region more than necessary to reduce the OFF current.

In general, it is necessary to secure an LDD region longer than 1.5 mu m, which causes a decrease in the ON current of the TFT.

In addition, according to the method shown in the third conventional example, it is possible to form the LDD region very small, about 0.1 µm to 0.5 µm, but in general, when using it as a driver of a liquid crystal panel or a TFT of a pixel, the driving voltage is 5 It is about -15V and is very high compared with general IC.

Therefore, when the LDD region is 0.1 µm to 0.5 µm, the effect is insufficient, and the OFF current cannot be sufficiently lowered in this process.

Therefore, in view of the above point, the present invention has a configuration of suppressing OFF current (photoconductive current) at the time of light irradiation, thereby suppressing deterioration of image quality such as luminance gradient and crosstalk, thereby realizing high performance and high reliability. It is a first object to provide a thin film transistor.

In addition, the second object of the present invention is to provide a thin film transistor which realizes high performance and high reliability by suppressing OFF current and minimizing the length of the LDD region to a minimum and reducing the ON current. .

1A and 1B are graphs showing the relationship between the channel width W of the channel region constituting the TFT and the photoconductive current (OFF current: I _OFF ) and the backlight luminance and the photoconductive current.

2A and 2B are graphs showing simulation results of an electric field when the TFT is turned OFF.

3 is a graph showing the relationship between the sheet resistance and the depletion layer width obtained by the simulation.

Fig. 4 is a graph showing the result of measuring the relationship between the depletion layer width obtained by simulation (when W = 4 mu m) and the photoconductive current at the sheet resistance corresponding to the depletion layer width.

5 is a diagram showing an equivalent circuit of an active matrix.

6 is a graph showing a simulation result of the pixel voltage loss.

7 is a schematic cross-sectional view of a liquid crystal display device using the thin film transistor according to Embodiment 1-1 of the present invention as a pixel switching element.

8 is a schematic cross-sectional view of the thin film transistor according to Embodiment 1-1 of the present invention.

9 is a schematic plan view of FIG. 8.

10A to 10H are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-1 of the present invention.

11I to 11M are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-1 of the present invention.

12 is a flowchart showing a method for manufacturing a thin film transistor according to Embodiment 1-1 of the present invention.

13 is a graph showing voltage / current characteristics of a thin film transistor.

14 is a graph showing the nonuniformity in the substrate surface of the OFF current.

Fig. 15 is a graph showing simulation results of Vg-Id characteristics of a thin film transistor with the concentration of the n-type region as a parameter.

16A and 16B are graphs showing the results of simulating the electric field when the TFT is turned off.

17A to 17G are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-2 of the present invention.

18H to 18J are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-2 of the present invention.

Fig. 19 is a plan view showing a wiring pattern of a C-MOS inverter using the thin film transistor according to Embodiment 1-3 of the present invention.

20 is an equivalent circuit diagram thereof.

FIG. 21 is a cross-sectional view taken along line XX 'of FIG. 19.

Fig. 22 is a graph showing an operation point in the bias state of the n-ch transistor at ON / OFF time in the C-MOS inverter.

23A to 23D are graphs showing simulation results of Vg-Id characteristics when the LDD region is changed from 0.5 µm to 3 µm using sheet resistance as a parameter.

24A and 24B show the results of simulating an electric field when the TFT is turned OFF (in the Vg =-10V and Vd = 6V) in the channel region and the LDD region.

25A and 25B are graphs showing the relationship between the length (ΔL), the OFF current, the length of the LDD region (ΔL), and the ON current of a TFT having an actual LDD region.

26 is a simplified cross-sectional view of the thin film transistor according to the embodiment 2-1.

FIG. 27 is a schematic plan view of FIG. 26.

28A to 28H are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 2-1 of the present invention.

29A to 29E are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 2-1 of the present invention.

30 is a flowchart showing a method for manufacturing a thin film transistor according to Embodiment 2-1 of the present invention.

31A to 31D are schematic cross-sectional process diagrams for describing the steps for forming an LDD region.

32 is a perspective view of a photomask and a substrate.

33A and 33B are plan views of a photomask and a substrate.

34A and 34B are schematic cross-sectional views of a thin film transistor after LDD region formation.

35 is a graph showing the voltage / current characteristics of the thin film transistor according to the embodiment 2-1.

36 is a graph showing non-uniformity in the substrate surface of the OFF current of the thin film transistor according to the embodiment 2-1.

Fig. 37 is a graph showing the results of simulating the Vg-Id characteristics of the TFT using the density of the LDD region as a parameter.

38A and 38B are schematic diagrams for explaining the luminance gradient and crosstalk.

(Initiation of invention)

That is, in order to solve the above problem, the invention described in claim 1 includes a polycrystalline silicon semiconductor layer having a channel region and a source region and a drain region disposed on both sides of the channel region, wherein the channel region and the A depletion layer is formed between the drain region, and has a proportional relationship with the width of the depletion layer and the photoconductive current generated when light is irradiated to the channel region. The width of the depletion layer is set to be equal to or less than the value obtained based on the above proportional relationship so as to fall within the allowable value.

As described above, the depletion layer width is newly found to have a proportional relationship with the photoconductive current. Thus, by controlling the depletion layer width, it is achieved to make the photoconductive current below a predetermined allowable value, and thus the image quality such as luminance inclination or crosstalk is achieved. It is possible to provide a thin film transistor without deterioration.

The invention described in claim 2 is the thin film transistor according to claim 1, wherein the sheet resistance of the drain region is R (kΩ / □) and the channel width of the channel region is W (μm). It is characterized by satisfying the relationship of 1.

A is a constant determined by the photoconductive current and the light intensity.

(R + 30) W <A

The invention described in claim 3 is the thin film transistor according to claim 2, wherein the sheet resistance of the drain region is R (k? /?) And the channel width of the channel region is W (µm). It is characterized by satisfying the relationship of 2.

(R + 30) W <1 x 10 ³

As shown in Equations 1 and 2, the range of suppressing the OFF current (photoconductive current) during light irradiation is defined by the relationship between the newly controllable factor (sheet resistance in the drain region) and the channel width in the channel region. can do.

In addition, since the thin film transistor that satisfies the relationship of Equations 1 and 2 can suppress an increase in OFF current during light irradiation, it is possible to prevent crosstalk and luminance gradient, thereby realizing high performance and high reliability. have.

The invention described in claim 4 is the thin film transistor according to claim 3, wherein the channel width W of the channel region is 2 µm or less.

In the relation of Equation 2 above, even when the channel width W of the channel region is set to 2 μm or less, the increase in the OFF current during light irradiation can be suppressed by the sheet resistance R and the channel width W. .

The invention according to claim 5 or 6 is the thin film transistor according to claim 3 or 4, wherein the sheet resistance of the drain region is 20 kΩ / □ or more and 100 kΩ / □ or less.

This is because when the sheet resistance is 20 kΩ / □ or less, the OFF current increases rapidly, and when the sheet resistance is 100 kΩ / □ or more, the ON current of the transistor decreases and the operation of the panel becomes unstable.

By setting the sheet resistance of the drain region to 20 kΩ / □ or more and 100 kΩ / □ or less, it is possible to provide a thin film transistor which can reduce the OFF current and does not reduce the ON current.

The invention described in claim 7 has a channel region and a polycrystalline silicon semiconductor layer having source and drain regions disposed on both sides of the channel region, wherein the liquid crystal display is a thin film transistor provided as a switching element. When the luminance of the backlight constituting the device is set to 2000 (cd / m ² ) or more, the impurity concentration is at least either between the source region and the channel region or between the drain region and the channel region. A low concentration impurity region is formed which is lower than the source region and the drain region, and the length (ΔL) of the low concentration impurity region is 1.0 mu m or less.

In this way, by forming the low concentration impurity region, diffusion of the depletion layer can be made within the range of the low concentration impurity region whose length DELTA L is 1.0 mu m or less, so that the photoconductive current (OFF current) does not increase. Thin film transistor can be used.

In addition, in the invention described in claim 8, a channel region and a source region and a drain region disposed on both sides of the channel region are formed, and between the source region and the channel region or between the drain region and the channel region. A thin film transistor having at least one of a polycrystalline silicon semiconductor layer having a low concentration impurity region having a lower impurity concentration than a source region and a drain region, wherein the length of the low concentration impurity region is? (V) In the case where the channel width of the channel region is set to W (占 퐉), the relation of expression (3) is satisfied.

ΔL> (WVlc) / 36

By satisfying such a relationship, when the thin film transistor is turned off, the low concentration impurity region becomes a high resistance layer in which carriers are depleted, so that the OFF current can be reduced.

In addition, it is possible to determine the guideline of the length of the LDD region in Equation 1, and it is unnecessary to secure the LDD region more than necessary because of the OFF current reduction.

The invention described in claim 9 is characterized in that the thin film transistor according to claim 8 satisfies the relationship of equation (4) when the channel length of the channel region is L (µm).

△ L <1.5 ㆍ (W / L)

By further satisfying such a relationship, when the thin film transistor is turned on, the low-concentration impurity region under the gate electrode becomes a low-resistance region due to the action of an electric field from the gate electrode, and becomes a low resistance region. No reduction occurs. Therefore, the thin film transistor can sufficiently secure the ON current and at the same time reduce the OFF current.

The invention described in claim 10 is the thin film transistor according to claim 9, wherein the channel width W of the channel region is 2 µm or less.

As described above, by regulating the length DELTA L of the low concentration impurity region, the OFF current can be reduced and the ON current does not decrease.

The invention according to claim 11 or 12 is the thin film transistor according to claim 9 or 10, wherein the sheet resistance of the low concentration impurity region is 20 kΩ / □ or more and 100 kΩ / □ or less.

The invention described in claim 13 is the thin film transistor according to claim 11, wherein the low concentration impurity region is formed only between the drain region and the channel region.

The formation of the low concentration impurity region is intended to naturally reduce the electric field acting on the drain region. From this point of view, it is not necessary to form the low concentration impurity region in both the drain region and the channel region.

Therefore, if a low concentration impurity concentration is formed between at least one of the drain region and the channel region or between the drain region and the channel region, the area of the thin film transistor can be reduced.

The invention described in claim 14 is a liquid crystal display device comprising a liquid crystal panel portion including the thin film transistor according to claim 1 as a switching element, and a backlight portion for supplying light from the back side of the liquid crystal panel portion. When the sheet resistance of the drain region is R (kΩ / □), the brightness of the backlight portion is B (cd / m ² ), and the channel width of the channel region is W (μm), the relation of Equation 5 is satisfied. It features. C is a constant determined by the photoconductive current.

(R + 30) B W W C

The invention described in claim 15 is the liquid crystal display device according to claim 14, wherein the sheet resistance of the drain region is R (kΩ / □), the brightness of the backlight portion is B (cd / m ² ), and the channel region. When the channel width of is set to W (µm), the relationship of the expression (6) is satisfied.

(R + 30) B W <1 × 10 ⁶

In addition, the invention described in claim 16 is an EL device comprising: an EL device having a light emitting layer on an upper layer of a pixel electrode formed on a substrate having a thin film transistor, and having an opposing electrode formed on the light emitting layer, wherein the thin film transistor is a thin film according to claim 1 In the case of a transistor, when the light intensity irradiated to the channel region of the thin film transistor is set to B (cd / m ² ), the relation of Equation 5 is satisfied. C is determined by the photoconductive current. Is a constant.

(R + 30) B W W C

The invention described in claim 17 is the EL display device according to claim 16, wherein the sheet resistance of the drain region is R (kΩ / □), and the light intensity irradiated to the channel region is B (cd / m ² ). In the case where the channel width of the channel region is W (µm), the relation of Equation 6 is satisfied.

(R + 30) B W <1 × 10 ⁶

In addition, the invention described in claim 18 includes a polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate, a gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon semiconductor layer, and the gate insulating film image. A gate electrode forming step of forming a gate electrode in a pattern form, an anode oxidation step of oxidizing the side surface of the gate electrode to form a metal oxide film covering the side surface of the gate electrode, and the polycrystalline silicon semiconductor layer. A method of manufacturing a thin film transistor having an impurity doping step of doping an impurity with the gate electrode as a mask, the method comprising: controlling a film thickness of a metal oxide film formed in the anodization step to form a length of a low concentration impurity region formed in the impurity doping step (ΔL) is characterized in that 1.0 µm or less.

In addition, the invention as set forth in claim 19 is a manufacturing method of a thin film transistor, comprising: a polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate, and a gate insulating film forming a gate insulating film on the polycrystalline silicon semiconductor layer A gate electrode forming step of forming a gate electrode in a pattern form on the gate insulating film, a first impurity doping step of doping impurities with the gate electrode as a mask on the polycrystalline silicon semiconductor layer, and the first A shielding film forming step of forming a shielding film on a semiconductor region doped with an impurity by an impurity doping step, and forming the shielding film into a pattern by anisotropic etching; and doping impurities using the shielding film as a mask on the polycrystalline silicon semiconductor layer. , Even if the impurity concentration difference exists in the lower region of the shielding film and other regions Thus, a low concentration impurity region having an impurity concentration lower than that of the source region and the drain region is formed in at least one of the source region and the channel region or between the drain region and the channel region, and the length of the low concentration impurity region is 1.0 μm or less. And a second impurity doping step.

The invention as set forth in claim 20 is a manufacturing method of the thin film transistor as set forth in claim 19, wherein the low-concentration impurity region has a length of? I am doing it.

[1st invention group]

(Concept of the first invention group)

First, after explaining the concept of the first invention group, specific embodiments will be described with reference to the drawings.

In the first invention group, the object is to suppress the photoconductive current during light irradiation to the TFT.

Therefore, in order to achieve the above object, the present inventors searched for a parameter having a correlation with the photoconductive current, and as a result, newly discovered that the depletion layer width has a proportional relation with the photoconductive current.

By controlling (smalling) the depletion layer width in accordance with this proportional relationship, it is possible to achieve a photoconductive current below an allowable value, and to provide a thin film transistor without deterioration in image quality such as luminance gradient or crosstalk.

The "depletion layer width" is defined as the distance between the tangents of two points at which the electric field strength rises, as shown in FIG. 2A to be described later.

It is also known that the brightness B of the backlight and the channel width W of the channel region have a correlation with the photoconductive current, and the TFT is designed according to these two control parameters.

However, the two control parameters alone are not sufficient for suppressing the photoconductive current, so that an error may occur in designing the TFT.

Therefore, the present inventors further examined the above "proportional relationship between the depletion layer width and the photoconductive current" and newly discovered that the sheet resistance of the drain region was also correlated with the photoconductive current.

As a result, the new parameter of the sheet resistance (R) is used as an evaluation criterion, resulting in three control parameters. The design accuracy of the thin film transistor can be improved and the photoconductive current can be remarkably suppressed compared to two conventional control parameters. Can be.

Next, the relationship between the depletion layer width and the photoconductive current will be described first, and then the relationship between the luminance B of the backlight, the sheet resistance R of the drain region, and the channel width W of the channel region. It demonstrates.

Next, the principle of the specific manufacturing method of TFT for suppressing photoconductive current is demonstrated.

First, the present inventors measured the relationship between the channel width and the photoconductive current of the channel region constituting the TFT, and measured the relationship between the sheet resistance and the photoconductive current of the drain region.

Operational analysis was also performed by simulation to find the range of the depletion layer width.

FIG. 1A is a graph showing the relationship between the channel width W and the photoconductive current (OFF current: I _OFF ) of the channel region of the TFT constituting the TFT. Further, the solid line shows the relationship between the 6000cd / cm ^2, a broken line 4000 cd / cm ^2, 1-dot chain line is a channel width (W) and the photoconductive current (I _OFF) when irradiated with light of 2000cd / cm ^2.

In Fig. 1A, it is apparent that the OFF current I _OFF during light irradiation is proportional to the channel width W. In addition, although FIG. 1B is a graph showing the relationship between the backlight luminance and the photoconductive current, it was confirmed that the OFF current I _OFF is proportional to the backlight brightness B. FIG.

2A is a graph showing a result of simulating an electric field when the TFT is turned OFF.

According to the simulation results shown in FIG. 2A, the electric field is almost concentrated only at the junction of the channel / drain region. When the sheet resistance of the LDD region is 20 k? / □ (solid line), the depletion layer width is about 0.5 µm, It was found that the pip layer region mainly extended to the channel side.

In contrast, when the sheet resistance is 100 k? / □ (broken line), the depletion layer width is about 0.9 μm, and it is confirmed that it is diffused into the LDD region.

As a result, it has been newly discovered that the width of the depletion layer also changes as the sheet resistance changes. Thus, the present inventors investigated the relationship between the sheet resistance and the depletion layer width. The result is shown in FIG.

3 shows the relationship between the sheet resistance and the depletion layer width obtained by the simulation. It was confirmed that the depletion layer width Wd is proportional to the sheet resistance R. FIG. This is considered to be because the depletion layer extends to a region having a low carrier concentration, similar to the diffusion of the depletion layer in the case of p / n junction. The relationship between the sheet resistance and the depletion layer width of FIG. 3 is shown in the following equation.

Wd = 8 × 10 ^-3 R + 0.24

Fig. 4 shows the result of measuring the relationship between the depletion layer width obtained by simulation (when W = 4 mu m) and the photoconductive current at the sheet resistance corresponding to the depletion layer width.

When the depletion layer width and the photoconductive current were plotted in logarithms, a straight line having an approximately inclination of 1 was obtained. This suggests that the photoconductive current is generated by the depletion region.

The relationship between the depletion layer width Wd and the photoconductive current may be expressed as in Equation 8 below.

I _photo = 5 x 10 ^-15 Wd

In Equation 8, I _photo is a value of light intensity per 1 (cd / m ² ) at a channel width of 4 μm.

As described above, it is found that the depletion layer width Wd has a proportional relationship with the photoconductive current I _photo in Equation 8, and thus the photoconductive current can be made below the allowable value by controlling the depletion layer width (smaller). It is possible to provide a thin film transistor which realizes high performance and high reliability without deterioration of image quality such as luminance gradient or crosstalk.

In addition, although the said "permissible value" is mentioned later, for example, it is a value of 10 pA or less.

In addition, since I _OFF in FIG. 1A is proportional to the channel width W and the light intensity B, I _OFF and I _photo satisfy the following equation (9).

I _OFF = I _photo ㆍ (W / 4) ・ B

Therefore, if I _photo is erased in Equations 9 and 8, the following Equation 10 is obtained.

I _OFF (4 / (WB)) = 5 × 10 ^-15 Wd

Then, when the depletion layer width Wd is erased in Equation 7, 10, the following Equation 11 is obtained. Here, in FIG. 1A, I _OFF is proportional to the channel width (W).

R = I _OFF ㆍ 10 ¹⁷ / (B ㆍ W)-30

In general, in order to maintain high quality image quality, I _OFF requires a value of 10 pA or less. The reason for this is as follows. 5 shows an equivalent circuit of the active matrix.

When the OFF resistance R _OFF of the TFT becomes small, the electric charge cannot be held until the next writing, resulting in a voltage loss. The pixel voltage V after the time T is described in equation (12).

V = V _O ｛1-exp (T / (R _OFF × Ctot))｝

Where Ctot = Cs + Clc

6 shows the simulation results of time and voltage loss when the TFT OFF current (R _OFF = V _sd / I _OFF ) is used as a parameter. In Fig. 6, it is confirmed that the OFF current needs to be 10 pA or less in the backlight irradiation state in order to suppress the voltage loss to 0.02 V or less with the holding time of 16 msec (1/60 Hz).

Therefore, if I _OFF of the above formula (11) is 10 pA or less, the following equation is obtained.

(R + 30) and B and W <10 and ^10-12 and 10 ¹⁷ = 1 × 10 ⁶

Becomes

In addition, depending on the conditions under which the thin film transistor is used, the value of suppressing the OFF current changes, so that it can be expressed as in Equation 5 below.

(R + 30) B W W C

C is a constant determined by the photoconductive current.

In this way, the thin film transistor that satisfies the above formula (6) can suppress the photoconductive current, and thus can prevent crosstalk and luminance gradient. Excellent image quality enables high performance and high reliability.

In addition, although Equation 6 is a formula including a backlight luminance as a liquid crystal panel, in general, the thin film transistor is not limited to only a transmission type having a backlight at all times. Therefore, assuming that the backlight luminance B is at most 5000 cd / m ² , Equation 6

(R + 30), W <2 x 10 ²

The thin film transistor satisfying Equation 2 'may be a thin film transistor irrespective of the luminance (B) of the backlight, that is, a transparent or reflective type.

In addition, it is possible to satisfy the following Equation 2 as Equation 2 'as the thin film transistor having better performance.

(R + 30) W <1 x 10 ³

Equation 11 may be expressed as Equation 11 'below. In other words

(R + 30) W <(I _OFF ㆍ 10 ¹⁷ ) / B

If the right side of Equation 11 'is replaced with a constant A determined by I _OFF and B, it can be expressed by Equation 1 below.

(R + 30) W <A

(A is a constant determined by photoconductive current and light intensity)

Further, in the structure of the TFT, by forming the LDD region, the depletion layer does not diffuse beyond the LDD region, and as described above, the photoconductive current which is proportional to the width of the depletion layer can be suppressed.

16A and 16B show the results of simulating the electric field when the TFT is turned OFF (in the Vg =-10V and Vd = 6V) in the channel region and the LDD region.

In the simulation results, the area applied to the electric field depends on the sheet resistance, and when the sheet resistance of the LDD region was 20 kΩ / □, it was confirmed that it was about 0.4 μm, and when the sheet resistance was 100 kΩ / □, it was 1.0 μm.

In addition, although the said channel width is 4 micrometers, when the channel width W of a channel area | region is made small and it is 2 micrometers or less, the said formula (1) and (2) are guide | indication which are effective in manufacturing a thin film transistor especially.

In addition, in the following embodiment, what manufactures TFT based on the said simulation is demonstrated concretely.

Embodiment 1-1

7 is a schematic cross-sectional view of a liquid crystal display device using the thin film transistor according to Embodiment 1 of the present invention as a pixel switching element, FIG. 8 is a schematic cross-sectional view of the thin film transistor according to Embodiment 1 of the present invention, and FIG. 9 is a schematic view of FIG. Top view.

As shown in FIG. 7, the liquid crystal display device 50 is a transmissive liquid crystal display device including a liquid crystal panel unit 51 and a backlight unit 52 disposed on the back side of the liquid crystal panel unit 51. The liquid crystal panel part 51 includes polarizing plates 53 and 53, glass substrates 2 and 54b, a thin film transistor 1 arranged in a matrix, a pixel electrode 55, an alignment film 56, and a liquid crystal. The layer 57, the common electrode 58, and the like.

The thin film transistor 1 (hereinafter referred to as TFT) and the pixel electrode 55 are formed on the glass substrate 2, and the common electrode 58 is formed on the substrate 54b. Further, alignment films 56 and 56 made of polyimide resin and the like are formed on the substrates 2 and 54b, respectively, and the alignment films 56 and 56 are previously arranged in directions perpendicular to each other. The rubbing process is performed, and the board | substrates 2 and 54b are opposingly arranged through the spacer which is not shown in figure.

In addition, the liquid crystal layer 57 is sandwiched between the substrates 2 and 54b, and the liquid crystal in the liquid crystal layer 57 is aligned by 90 ° torsion. Further, the outer surfaces of (2) and 54b are arranged so that the vibration directions of light regulated by the polarizing plates 53 and 53 are parallel to each other.

Moreover, the backlight part 52 is arrange | positioned at the back surface (lower side) side of the said liquid crystal panel part 51. As shown in FIG. The backlight unit 52 is composed of a light emitting element such as a cold cathode tube and a light distribution plate for equalizing light.

Next, the thin film transistor will be described with reference to FIGS. 8 and 9.

The thin film transistor 1 includes a polysilicon layer 3 having a film thickness of 500 GPa on the glass substrate 2, a gate insulating layer 4 made of SiO ₂ (silicon dioxide) having a film thickness of 1000 GPa, and a gate electrode made of aluminum. The interlayer insulating layer 6 made of (5a) and SiO ₂ is laminated in this order.

In addition, the polysilicon layer 3 includes a channel region 3c located directly below the gate electrode 5a, a source region 3a (n + layer) having a high concentration, and a drain region (n +) having a high impurity concentration. Layer) 3b).

In the present embodiment, the length DELTA L of the LDD regions (n-layers) 3d and 3e is set to 0.4 µm. The channel width W of the channel region 3c is set to 5 mu m.

Here, the sheet resistance of the drain region is R (kΩ / □), the luminance of the backlight 52 of the liquid crystal display device 50 in which the active matrix TFT is used is B (cd / cm ² ), and the channel region (3c). In the case where the channel width of?) Is W (µm), it is designed to satisfy the following expression (6).

(R + 30) B W = I _off <1 × 10 ⁶

Further, the TFT 1 is further provided with a source electrode 7 and a drain electrode 8 made of aluminum, for example, and the source electrode 7 is provided on the gate insulating layer 4 and the interlayer insulating layer 6. It is connected to the source region 3a through the contact hole 9b formed, and the drain electrode 8 is connected through the contact hole 9b formed in the gate insulating layer 4 and the interlayer insulating layer 6. It is connected to the drain region 3b.

Next, the manufacturing method of a thin film transistor is demonstrated. 10A to 10H are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-1 of the present invention, and FIGS. 11I to 11M are schematic sectional views showing the manufacturing method of the thin film transistor, and FIG. 12 is similarly a manufacturing method of the thin film transistor. This is a flowchart.

(1) First, a-Si layer 15 having a film thickness of 500 GPa is deposited on the glass substrate 2 by plasma CVD, and then dehydrogenated at 400 占 폚 (Fig. 10A). This dehydrogenation treatment aims at preventing generation of ablation of the Si film due to desorption of hydrogen during crystallization.

In addition, the process of forming a-Si can use processes, such as reduced pressure CVD and sputter | spatter, in addition to plasma CVD. In addition, polysilicon films may be directly deposited using plasma CVD or other methods. In this case, the annealing process by the laser mentioned later becomes unnecessary.

(2) Next, melt recrystallization (p-Si) of the a-Si layer 15 is performed by laser annealing using an excimer laser having a wavelength of 308 nm to form the polycrystalline silicon layer 16 (FIG. 10B). .

(3) Next, the polysilicon layer 16 is islanded into a predetermined shape to form the polysilicon layer 3 (FIG. 10C).

(4) Subsequently, the polysilicon layer 16 is covered on the glass substrate 2 to form a SiO ₂ (silicon dioxide) layer having a thickness of 1000 占 to become the gate insulating layer 4 (FIG. 10D).

(5) Next, the metal layer 17 which consists of aluminum used as the gate electrode 5a is formed into a film (FIG. 10E).

(6) Next, the metal layer 17 is patterned into a predetermined shape to form the gate electrode 5a (FIG. 10F).

(7) Then, the doping of the impurity is performed using the gate electrode 5a as a mask (Fig. 10G). Specifically, phosphorus ions are doped as impurities by the ion doping method.

As a result, the channel region 3c located directly below the gate electrode 5a becomes a region where impurities are not doped. The region excluding the channel region 3c of the polysilicon layer 3 is a layer doped with impurities.

In this case, the doping acceleration voltage is 80 kV, the beam current density is 1 mA / cm ² , and the n-type region is created at high acceleration.

(8) Next, the gate electrode 5a is covered to form a photoresist 18 (FIG. 10H).

(9) Next, the photoresist 18 is formed into a pattern by anisotropic etching to form a resist film 5b (Fig. 11I).

At this time, an accurate pattern of the resist film 5b can be formed by anisotropic etching.

(10) Next, as shown in Fig. 11J, the second impurity is doped using the resist film 5b as a mask. Specifically, phosphorus ions are doped as impurities by the ion doping method.

In this case, the doping acceleration voltage is 12 kV, the beam current density is 0.5 mA / cm ² , and a high concentration n-type region is created at low speed.

(11) Next, an interlayer insulating layer (SiOx) 6 is formed (FIG. 11K).

(12) Then, contact holes 9a and 9b are opened in the interlayer insulating layer 6 and the gate insulating layer 4 (Fig. 11L).

(13) Then, by the sputtering method, for example, a metal layer such as Al is filled into the contact holes 9a and 9b, and the upper part of the metal layer is patterned into a predetermined shape so that the source electrode 7 and the drain electrode 8 ) (FIG. 11m). In this way, the TFT 1 is produced.

In the above example, the n-channel TFT has been described, but the p-channel TFT can also be manufactured by the same manufacturing process.

On the back surface of the thin film transistor produced by the above manufacturing method, when 5000 cd / m ² of light is irradiated, the OFF current is almost 5 pA.

As described above, since the OFF current needs to be 10 pA or less in the backlight irradiation state, the thin film transistor according to the present embodiment can ensure good display characteristics.

FIG. 13 shows the voltage / current characteristics of the thin film transistor and FIG. 14 shows the nonuniformity in the substrate surface of the OFF current.

As shown in FIG. 13, the TFT 1 (graph of L3) which concerns on this embodiment was able to ensure stable large ON current and small OFF current.

In addition, the TFT 1 produced in this way in FIG. 14 can reduce the nonuniformity on the inside of the substrate surface.

15 shows the result of simulating the Vg-Id characteristics of the thin film transistor using the concentration of the n-type region as a parameter.

When the sheet resistance of the LDD region is 20 kΩ / □ or less, the OFF current increases rapidly. Therefore, the sheet resistance of the LDD region needs to be at least 20 kΩ / □ or more. On the other hand, when the sheet resistance of the LDD region is set to 100 k? / □ or more, the ON current of the transistor decreases and the operation of the panel becomes unstable.

Therefore, the range of sheet resistance in the LDD region is preferably 20 kΩ / □ or more and 100 kΩ / □ or less.

In general, the backlight luminance is about 5000 cd / m ² at maximum, and in this case, the depletion layer width Wd for suppressing the photoconductive current to 10 pA or less is obtained as follows.

That is, the width of the depletion layer can be obtained by substituting W = 4, B = 5000 and Ioff = 10 × 10 ⁻¹² in the above equation, and Wd = 0.4 μm.

Since the width of the depletion layer does not exceed the length of the LDD region, the effective depletion layer region becomes 0.4 µm or less, and the photoconductive current is suppressed (to 10 pA or less) by setting the length (ΔL) of the LDD region to 0.4 µm or less. One configuration can be done.

In addition, when the LDD region is smaller than 0.1 mu m, the electric field relaxation effect is lost. As shown in FIG. 2B, the OFF current increases, so that the LDD region is larger than 0.1 mu m.

In the equation (10), when the backlight luminance B is 2000 cd / m ² , the depletion layer width Wd is 1 μm.

Therefore, since the depletion layer width does not exceed the length of the LDD region, the effective depletion layer region becomes 1.0 µm or less, so that the photoconductive current can be suppressed by setting the length ΔL of the LDD region to 1.0 µm or less. More preferably, it is good to set it as 0.4 micrometer or less.

In the inspection process, the device whose LDD area is larger than 1.0 mu m cannot satisfy the OFF characteristic. Therefore, by performing the inspection process for the good quality of the LDD region having a length DELTA L of 1.0 µm or less, it is possible to sort the good and defective products, and the material loss in the panel process can be reduced.

As shown in Table 1, Experimental Examples 1 to 3 (that is, satisfying Equation 2) can suppress the OFF current during light irradiation, but Experimental Examples 4 and 5 (ie, the above equations). 6), it was confirmed that the OFF current at the time of light irradiation could not be suppressed.

  B (cd / m2)      W (μm)   R (kΩ / □)    OFF current   Experimental Example 1     3000       4      50      O   Experimental Example 2     5000       2      50      O   Experimental Example 3     5000       3      30      O   Experimental Example 4     3000       4      80      ×   Experimental Example 5     5000       4      50      ×

In this manner, the OFF current (photoconductive current) at the time of light irradiation is suppressed by the relationship between the newly controllable factor (sheet resistance of the drain region) and the channel width of the channel region by the above equation (6). Can be specified.

Therefore, by fabricating a thin film transistor that satisfies the relationship of Equation 6 above, the increase in OFF current can be suppressed, so that crosstalk and luminance inclination can be prevented, thereby providing a thin film transistor having high performance and high reliability. Can be.

(Embodiment 1-2)

The manufacturing method of the thin film transistor which concerns on Embodiment 1-2 of this invention is demonstrated.

In the thin film transistor of the present embodiment 1-2, the LDD region has a small length of 0.2 µm to 0.5 µm by anodization.

As a result, since the region on the drain side becomes a high concentration impurity region, the width of the depletion layer does not diffuse beyond the length of the LDD region, so that the photoconductive current can be suppressed.

A description of the specific manufacturing method is given below. 17A to 17G are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 1-2 of the present invention, and FIGS. 18H to 18J are schematic sectional views showing the manufacturing method of the thin film transistor as well.

The a-Si layer 15 was deposited on the glass substrate 2 in the same manner as in the above-described embodiment 1-1, and then melt recrystallization of the a-Si layer 15 in laser annealing using an excimer laser having a wavelength of 308 nm. (p-Si) is carried out to form the polysilicon layer 16.

Subsequently, the polysilicon layer 16 is islanded into a predetermined shape to form the polysilicon layer 3.

Subsequently, the gate insulator 4 is formed by covering the polysilicon layer 3 on the glass substrate 2 (Figs. 17A to 17D).

Subsequently, the metal layer 17 is formed into a film, and the photoresist 17a is formed in a pattern form on this metal layer 17, and the metal film 17 is patterned by the etching technique to form the gate electrode 5a. .

Next, the oxide insulating layer 5b is formed by anodizing the side surface of the gate electrode 5a (FIG. 17F).

Next, as shown in FIG. 17G, the doping of the impurity is performed using the gate electrode 5a as a mask. Specifically, phosphorus ions are doped as impurities by the ion doping method.

As a result, the channel region 3c immediately below the gate electrode 5a becomes a region where impurities are not doped.

Then, LDD regions 3d and 3e are formed in the region immediately below the oxide insulating layers 5b and 5b, and channel regions 3a and drain regions 3b are formed outside these.

Subsequently, an interlayer insulating layer (SiO ₂ ) 6 is formed as shown in FIGS. 18H to 18J, and then contact holes 9a and 9b are formed in the interlayer insulating layer 6 and the gate insulating layer 4. Opening and sputtering method, for example, fill a contact layer 9a and 9b with a metal layer such as Al, and pattern the upper portion of the metal layer into a predetermined shape so that the source electrode 7 and the drain electrode 8 To form. In this way, a TFT is produced.

According to the anodic oxidation of this embodiment, it is possible to reduce the length of the LDD region to 0.2 µm to 0.5 µm.

As a result, the region on the drain side becomes a high concentration impurity region, so that the width of the depletion layer does not spread beyond this length. Therefore, the photoconductive current can be suppressed small.

As a result, when the thin film transistor is turned off, the low concentration impurity region becomes a high resistance layer from which the carrier is depleted, so that the OFF current can be reduced. In addition, in Equation 2, a guide of the length of the LDD region can be determined, and it is not necessary to secure the LDD region more than necessary to reduce the OFF current.

In addition, Equation (2) satisfies Equation (6). When the thin film transistor is turned on, a low concentration impurity region under the gate electrode accumulates electrons that are carriers, thereby causing low resistance due to the action of an electric field from the gate electrode. It becomes the area and there is no decrease in ON current.

Therefore, the thin film transistor that satisfies the equations (2) and (6) can sufficiently secure the ON current and reduce the OFF current.

In addition, the ball impurity doping by an acceleration voltage of the ion doping method using the at least 10kV 30kV or less and a beam current density of 0.05㎂ / cm ² or more 1㎂ / cm ² or less of a low speed, the ion acceleration voltage during the ion doping Since this is low, damage at the time of doping can be reduced.

In addition, even when the resist is used as a mask at the time of impurity doping, the resist can be removed without being deteriorated.

(Embodiment 1-3)

Embodiment 3 of this invention is demonstrated, referring FIGS. 19-22.

FIG. 19 is a plan view showing a wiring pattern of a C-MOS inverter using the thin film transistor according to Embodiments 1-3 of the present invention, FIG. 20 is an equivalent circuit diagram thereof, and FIG. 21 is a cross-sectional view taken along line X-X 'of FIG. to be.

The C-MOS inverter 50 constitutes a driving circuit of the liquid crystal display device, for example. The C-MOS inverter 50 is composed of an n-channel TFT 22 and a p-channel TFT 23.

The n-channel TFT 22 has the same configuration as the n-channel TFT 1 of the first embodiment, and the corresponding parts are assigned the same reference numerals.

The p-channel TFT 23 is not a LDD structure but a normal type TFT. That is, the TFT 23 is formed of a polysilicon layer 24, a gate insulating layer 4 made of SiO ₂ (silicon dioxide), a gate electrode 25 made of aluminum, and SiO ₂ on the glass substrate ₂ . The interlayer insulating layer 6 is laminated in order.

The polysilicon layer 24 includes a channel region 24c located directly below the gate electrode 25, a source region 24a (p + layer) and a drain region 24b disposed on both sides of the channel region 24c ( p + layer).

In this TFT 23, a source electrode 26 and a drain electrode 27 made of aluminum, for example, are formed.

The source electrode 26 is connected to the source region 24a through the contact hole 28a formed in the gate insulating layer 4 and the interlayer insulating layer 6.

The drain electrode 27 is connected to the drain region 24b through the contact hole 28b formed in the gate insulating layer 4 and the interlayer insulating layer 6.

The gate electrode 5 of the n-channel TFT 22 and the gate electrode 25 of the p-channel TFT 23 are commonly connected to the input terminal 30 as shown in FIG. The drain electrode 8 of the n-channel TFT 22 and the drain electrode 27 of the p-channel TFT 23 are commonly connected to the output terminal 31 as shown in FIG.

In the present embodiment 1-3, only the drain side of the n-channel TFT has the LDD structure described in the above embodiment 1-1, the TFT can be reduced in size, and the source-drain distance can be reduced to about 6 mu m. In addition, compared with the case where the LDD region is formed on both the source and the drain, the size can be about 50% or less, and the TFT can be miniaturized.

Incidentally, both the n-channel TFT and the p-channel TFT may have an LDD structure. In order to reduce the circuit area occupied by the array substrate, however, when only one of the n-channel TFT and the p-channel TFT is used as the LDD structure, the n-channel TFT side is preferable.

This is because the electrons are significantly larger when the respective mobility of holes, which are carriers of the p-channel TFT, and electrons, which are carriers of the n-channel TFT are compared.

Therefore, when the same electric field is applied to the p-channel TFT and the n-channel TFT, the impact of the carrier on the n-channel TFT is large, and therefore the n-channel TFT tends to deteriorate.

Therefore, from the viewpoint of preventing deterioration of the TFT and improving the reliability, it is preferable to make the n-channel TFT the LDD structure.

Fig. 22 shows the operating point in the bias state of the n-ch transistor at ON / OFF time in the C-MOS inverter.

In this way, in the n-ch TFT in the inverter, the polarity of the gate electrode always operates at a voltage higher than 0 V with respect to the negative power supply.

Therefore, the negative power source always acts as the n-ch TFT source electrode, and the output side always acts as the drain electrode.

Therefore, using a circuit in which this portion has only the output side portion as described above contributes to the reduction of the area occupied by the circuit portion in the array substrate. It also contributes to the reduction of parasitic capacity in this part.

(Other matter)

In Embodiments 1-1 to 1-3, the LDD regions having one type of concentration have been described. However, the present invention is not limited thereto, and a plurality of LDD regions having different concentration differences may be formed.

That is, since the impurity concentration can be changed in multiple stages by constructing a plurality of junction regions where the impurity concentration gradually decreases as the LDD region is directed toward the channel region, concentration of the electric field in the semiconductor layer can be further alleviated. have.

In addition, the LDD region may be formed only between the drain region and the channel region. By configuring in this way, it is possible to obtain the effect of reducing the OFF current and to reduce the area of the thin film transistor.

In addition, in Embodiment 1-1 to 1-3, although it demonstrated using the top gate type TFT, this invention can also be applied to a bottom gate type TFT.

The thin film transistors described in Embodiments 1-1 to 1-3 can be applied to EL devices in addition to liquid crystal display devices.

That is, a plurality of thin film transistors described in Embodiments 1-1 to 1-3 can be formed on a substrate as a switching element, and the EL device provided with the substrate can be configured to suppress the photoconductive current.

[2nd invention group]

(Concept of the second invention group)

According to the present invention, high performance and high reliability are achieved by suppressing the OFF current of the thin film transistor (hereinafter referred to as &quot; TFT &quot;) and suppressing the reduction of the ON current by minimizing the length of the LDD region to the minimum necessary. It is an object to realize a TFT having.

Therefore, in order to find the length of the LDD region which is really necessary, the inventors conducted motion analysis on the LDD region portion by simulation to find out how much the region is applied to the electric field.

23A to 23D are graphs showing simulation results of Vg-Id characteristics when the LDD region is changed from 0.5 µm to 3 µm using sheet resistance as a parameter.

As a result, it was confirmed that the Vg-Id characteristic has a large dependence on the concentration of the LDD region, but has no dependence on the length of the LDD region. Next, consider the cause.

24A and 24B show the results of simulating the electric field when the TFTs are turned OFF in the channel region and the LDD region (when Vg = -10V and Vd = 6V).

In the simulation results, the area in which the electric field is applied depends on the sheet resistance, and when the sheet resistance is 20 kΩ / □, the area is about 0.4 μm, and when the sheet resistance is 100 kΩ / □, it is confirmed that the area is 1.0 μm.

Therefore, it has been found that even if the LDD region is made larger than the region in which the electric field is applied, the effect of mitigating the electric field is not effective, and only the resistor is inserted in series in the channel region of the transistor.

25A and 25B are graphs showing the relationship between the length LD of the LDD region, the OFF current and the length LD of the LDD region, and the ON current of the TFT having the actual LDD region. The sheet resistance of the LDD region is 100 k? / Sq.

As shown in Fig. 25A, even if the LDD region is longer than 1 mu m, there is no effect of reducing the OFF current, and the above-described simulation effect is reflected.

As shown in Fig. 25B, when the LDD region is longer than 1.5 mu m, the ON current cannot be sufficiently secured, and the ON current is reduced.

As a result, by setting the range of the LDD region to 1 µm or more and 1.5 µm or less, the ON current can be sufficiently secured and the OFF current can be suppressed small.

In the next embodiment, a description will be given of the production of TFTs based on the above simulation.

Incidentally, in the actual TFT manufacturing process, in order to ensure the above-mentioned LDD region reliably, it will be described later, but can be determined by the alignment mark at the time of mask registration.

(Embodiment 2-1)

FIG. 26 is a simplified cross-sectional view of the thin film transistor according to Embodiment 2-1, and FIG. 27 is a schematic plan view of FIG.

In Embodiment 2-1, an example in which an n-channel thin film transistor is applied to the present invention is shown. The thin film transistor (hereinafter referred to as TFT) 101 is formed of a polysilicon layer 103 having a film thickness of 500 GPa on the glass substrate 102, and a gate insulating layer (SiO ₂ (silicon dioxide) having a film thickness of 1000 GPa). 104, the gate electrode 105 made of aluminum, and the interlayer insulating layer 106 made of SiO ₂ are laminated in this order.

The gate electrode 105a is formed covered with a resist film 105b. Instead of the resist film 105b, a metal film may be used.

In addition, the polysilicon layer 103 includes a channel region 103c positioned directly below the gate electrode 105a, a source region 103a (n + layer) having a high impurity concentration, and a drain region having a high impurity concentration ( n + layer) 103b, and low concentration impurity regions (LDD regions: n-layers) 103d and 103e having low impurity concentrations.

The low concentration impurity region 103d is interposed between the source region 103a and the channel region 103c, and the low concentration impurity region 103e is interposed between the drain region 103b and the channel region 103c. .

These low concentration impurity regions 103d and 103e are located directly below the portions 105b1 and 105b2 protruding from the gate electrode 105a of the resist film 105b. Therefore, the junction surface of the low concentration impurity region 103d and the source region 103a substantially coincides with the end surface (left end surface of FIG. 1) of the resist film 105b, and the low concentration impurity region 103d and the channel region 103c. ) And the junction surface of the gate electrode 105a substantially coincide with the end surface of the gate electrode 105a (left end surface in Fig. 1).

The junction surface between the low concentration impurity region 103e and the drain region 103b substantially coincides with the end surface (right end surface of FIG. 1) of the resist film 105b, and the low concentration impurity region 103d and the channel region 103c. ) And the junction surface of the gate electrode 105a substantially coincide with the end surface (right end surface in FIG. 1) of the gate electrode 105a.

In the present invention, the length DELTA L of the low concentration impurity region is set to 1 µm or more, 1.5 µm or less, and the channel width W is set to 5 µm.

The TFT 101 is further provided with a source electrode 107 and a drain electrode 108 made of aluminum, for example, and the source electrode 107 is formed of the gate insulating layer 104 and the interlayer insulating layer 106. Is connected to the source region 103a through a contact hole 109a formed in the drain electrode 108, and the drain electrode 108 forms a contact hole 109b formed in the gate insulating layer 104 and the interlayer insulating layer 106. It is connected to the drain region 103b through.

Next, the manufacturing method of the thin film transistor which concerns on Embodiment 2-1 of this invention is demonstrated. 28A to 28H and 29 are schematic sectional views showing the manufacturing method of the thin film transistor according to Embodiment 2-1 of the present invention, and FIG. 30 is a flowchart showing the manufacturing method of the thin film transistor according to Embodiment 2-1 of the present invention.

(1) First, a-Si layer 105 having a film thickness of 500 GPa is deposited on the glass substrate 102 by plasma CVD, and then dehydrogenated at 400 占 폚 (FIG. 28A). This dehydrogenation treatment is intended to prevent generation of ablation of the Si film due to desorption of hydrogen during crystallization.

In addition, the process of forming a-Si can use processes, such as reduced pressure CVD and sputter | spatter, in addition to plasma CVD. In addition, polysilicon films may be directly deposited using plasma CVD or other methods. In this case, the annealing process by the laser mentioned later becomes unnecessary.

(2) Next, melt recrystallization (p-Si) of the a-Si layer 115 is performed by laser annealing using an excimer laser having a wavelength of 308 nm to form the polycrystalline silicon layer 116 (FIG. 28B). .

(3) Next, the polysilicon layer 116 is islanded into a predetermined shape to form the polysilicon layer 103 (FIG. 28C).

(4) Subsequently, the polysilicon layer 103 is covered on the glass substrate 102 to form a SiO ₂ (silicon dioxide) layer having a thickness of 1000 占 to become the gate insulating layer 104 (FIG. 28D).

(5) Next, a metal layer 117 made of aluminum serving as the gate electrode 105a is formed (FIG. 28E).

(6) Next, the metal layer 117 is patterned into a predetermined shape to form the gate electrode 105a (FIG. 28F).

(7) Then, the first impurity is doped using the gate electrode 105a as a mask (Fig. 28G). Specifically, phosphorus ions are doped as impurities by the ion doping method.

As a result, the channel region 103c positioned directly below the gate electrode 105a becomes a region where impurities are not doped.

The regions A and B except for the channel region 103c of the polysilicon layer 103 become n-layers doped with impurities.

In this case, the doping acceleration voltage is 80 kV, the beam current density is 1 mA / cm ² , and a low concentration n-type region is created at high acceleration.

(8) Next, the gate electrode 105a is covered to form a photoresist 118 (FIG. 28H).

(9) Next, the photoresist 118 is patterned to form a resist film 105b (FIG. 29A).

Here, the process of (9) is explained in full detail using FIGS. 31A, 31B, 31C, 31D-34A, 34B.

31A to 31D are schematic cross-sectional process diagrams illustrating a process for forming an LDD region, FIG. 32 is a perspective view of a photomask and a substrate, FIGS. 33A and 33B are plan views of a photomask and a substrate, and FIGS. 34A and 34B are after an LDD region is formed. It is a schematic sectional drawing of a thin film transistor.

As shown in FIG. 7, the photomask 140 and the substrate 102 are disposed to face each other, and an alignment light source (not shown) is disposed at an upper position of the photomask 140. The laser beam is incident on the alignment marks 141 and 142 formed on the photomask 140 and the substrate 102 by the light source, and the alignment is performed by reading the position signals of the alignment marks.

An almost square alignment mark 141 is formed at a predetermined position of the photomask 140 (102 locations of the photomask corner). In addition, a pattern (not shown) of a shielding film to be transferred to the substrate 102 is formed at the central position of the photomask 140.

On the glass substrate 102, alignment marks 142 are formed at positions corresponding to the alignment marks 141. As shown in FIG. The alignment mark 142 is an almost square transparent area surrounded by a black area around it.

In addition, although not shown, the shape of the alignment marks 141 and 142 is not limited to a square shape, but may be, for example, circular.

And as shown in FIG. 33A, when the position of the photomask 140 and the board | substrate 102 does not shift, the alignment mark 141 formed in the photomask 140 is the position formed in the board | substrate 102. As shown in FIG. When the LDD region is formed in the center of the transparent region of the alignment mark 142, the length? L of the LDD regions 103d and 103e is set to be 1.25 mu m.

In addition, it was found that the position of the substrate 102 and the photomask 140 are shifted, and the alignment mark 141 is not included in the alignment mark 142 so that the length of the LDD region to be formed is larger than 1.5 µm. Therefore, in such a case, the position of the substrate and the photomask is to be aligned so that the alignment mark 141 enters the alignment mark 142.

And even if the alignment mark 141 is aligned with the center of the alignment mark 142, as shown in FIG. 33B, in some cases, the alignment mark 141 may deviate from the left and right on the paper surface.

However, in the case of the present invention, since the accuracy of the alignment device is ± 0.25 占 퐉, the alignment mark 41 can be positioned within the alignment mark 42. In this manner, as shown in Figs. 34A and 34B, the lengths of the formed LDD regions 3d and 3e can be within 1 to 1.5 mu m.

In addition, although the accuracy of the alignment device is ± 0.25 µm, the nonuniformity of the LDD region can be further reduced by using a more accurate alignment device.

Next, the process of alignment of the said substrate and a photomask is demonstrated.

As shown in FIG. 31A, a photoresist serving as a shielding film is formed on the gate electrode 105a.

Next, as shown in Figs. 31B and 31C, the photoresist is exposed to light through a photomask 140, and developed to form a shielding film 105b of a predetermined pattern type.

In this case, as described above, after confirming that the alignment mark 141 is contained in the transparent portion of the alignment mark 142, exposure is performed.

(10) Then, as shown in FIG. 29B, the second impurity is doped using the resist film 105b as a mask. Specifically, phosphorus ions are doped as impurities by the ion doping method.

In this case, the doping acceleration voltage is 12 kV, the beam current density is 0.5 mA / cm ² , and a high concentration n-type region is created at low speed.

As a result, ions are doped in a region of the polysilicon 103 except for the region located immediately below the resist film 105b.

Therefore, it corresponds to the region (source region 103a and drain region 103b) which is not covered with the resist film 105b among the regions A and B where impurities are already doped by the first ion doping. Impurity is further doped to form an impurity high concentration region (n + layer).

On the other hand, in the regions A and B, which are covered with the resist film 105b (corresponding to the low concentration impurity regions 103d and 103e), the impurities are doped by the second ion doping. To form a low concentration impurity region (n-layer).

In this way, a low concentration impurity region 103e (n-layer) is formed between the source region 103a (n + layer) and the channel region 103c, and the drain region 103b (n + layer) and the channel region 103c. Can be formed between the low concentration impurity regions (n-layers), and the low concentration impurity regions 103e (n-layers) can be formed between the drain regions 103b (n + layers) and the channel regions 103c. have.

Further, since the first ion doping is performed using the gate electrode 105a as a mask and the second ion doping is performed using the resist film 105b as a mask, the source region 103a, the low concentration impurity region 103d, The region 103e and the drain region 103b can be formed in a self-aligning manner, and the portion where the gate electrode 105 and the source region 103a overlap and the portion where the gate electrode 105 and the drain region 103b overlap are considered. It can be suppressed so small that it is not.

Therefore, a thin film transistor having an LDD region having a length of 1 to 1.5 mu m can be formed, and the OFF current can be made low, and the fall of the ON current can be suppressed as much as possible.

(11) Next, an interlayer insulating layer (SiOx) 6 is formed (FIG. 29C).

(12) Then, contact holes 109a and 109b are opened in the interlayer insulating layer 106 and the gate insulating layer 104 (FIG. 29D).

(13) Then, a metal layer such as Al is filled into the contact holes 109a and 109b by the sputtering method, and the upper portion of the metal layer is patterned into a predetermined shape, so that the source electrode 107 and the drain electrode 108 are formed. To form (Fig. 29E). In this way, the TFT 101 is produced.

In the above example, the n-channel TFT has been described, but the p-channel TFT can also be manufactured by the same manufacturing process.

35 shows the voltage / current characteristics of the thin film transistor prepared by the above manufacturing method. 36 shows the nonuniformity in the substrate surface of the OFF current.

As shown in Fig. 35, in the TFT 101 (graph of L3) according to the second embodiment, the LDD region, which is a high resistance region, is small at 1 to 1.5 mu m, thereby ensuring a stable large ON current and a small OFF current. Could.

In addition, if the alignment accuracy of the aligner is improved, it is of course possible to further reduce the length of the LDD region.

In addition, by increasing the carrier concentration in the n-region, the area in which the electric field is applied becomes small, while the peak value of the electric field is high, so the OFF current increases.

37 shows the results of simulating the Vg-Id characteristics of the thin film transistor using the density of the LDD region as a parameter.

The OFF current rapidly increases when the sheet resistance of the LDD region is 20 k? / S or less. Therefore, the sheet resistance of the n-region needs a value of at least 20 k? / □ or more. On the other hand, when the sheet resistance of the LDD region is set to 100 k? / □ or more, the ON current of the transistor decreases and the operation of the panel becomes unstable.

Therefore, the range of sheet resistance in the LDD region is preferably 20 kΩ / □ or more and 100 kΩ / □ or less.

In addition, the first impurity doping, acceleration voltage of ion accelerator of the time, an ion doping by using the ion doping method at least 10kV 30kV or less and a beam current density of 0.05㎂ / cm ² or more 1㎂ / cm ² or less low speed Since the voltage is low, damage at the time of doping can be reduced.

In addition, even when the resist is used as a mask during the first impurity doping, the resist can be removed without being deteriorated.

Alternatively, the second impurity doping can be implanted with sufficient ions into the polysilicon even at the second ion doping by using the ion doping method at an acceleration voltage of 30 kV or more and a beam current density of 1 mA / cm ² or higher. Do.

In the embodiment 2-1, the length ΔL of the LDD region constituting the TFT 101 is set to 1 µm or more and 1.5 µm or less, and the source-drain voltage Vlc is 6V and the channel width W is set. It is made on the conditions of 6 micrometers.

By the way, in general, the OFF current is determined by the electric field between the source and the drain, and Vlc is applied only to the channel region / LDD region, so the strength of the electric field is represented by Vlc / ΔL (Solid State Electron, 38, 2075 (1995)). ).

The electric field strength is represented by the following equation.

4 × 10 ⁶ <Vlc / ΔL <6 × 10 ⁶

Since the OFF current is proportional to the channel width W, the relation between the length DELTA L of the LDD region, the source-drain voltage Vlc, and the channel width W is expressed by the following equation (3). can do.

ΔL> (WVlc) / 36

The meaning of said formula (3) is demonstrated. When the miniaturization of the TFT proceeds, the values of DELTA L and W decrease, and thus the source-drain voltage Vlc decreases.

Therefore, Table 2 shows the characteristics of the TFTs in which the length DELTA L of the LDD region, the source-drain voltage Vlc, and the channel width W are changed.

  Vlc (V)  ΔL (μm) Vlc ／ △ L  W (μm) W · Vlc ／ 36 3 (W / L)   Current  Off current   Experimental Example 1    6    One 6, 10 ⁶    5    0.83   1.25   O   O   Experimental Example 2    6   1.5 4, 10 ⁶    5    0.83   1.25    ×   O   Experimental Example 3    3   0.5 6, 10 ⁶    5    0.41   1.25   O   O   Experimental Example 4    3   0.75 4, 10 ⁶    3    0.25   0.75   O   O   Experimental Example 5    6    2 3 · 10 ⁶    5    0.83   1.25    ×   O   Experimental Example 6    6   0.5 12, 10 ⁶    5    0.83   1.25   O   ×   Experimental Example 7    3    One 3 · 10 ⁶    3    0.25   0.75    ×   O

    (L = 12 μm, On current O: On current secured, Off current O: Off current suppressed)

As shown in Table 2, Experimental Examples 1 to 5 and 7 (that is, satisfying Equation 1) can suppress OFF current, but Experimental Example 6 (i.e., not satisfying Equation 3 above). ) Cannot suppress OFF current.

In the case where the channel width of the channel region is W, the relationship between the length L D of the LDD region, the channel width L of the channel region, and the channel width W can be expressed by the following equation (4). have.

△ L <3 ㆍ (W / L)

Equation 4 shows the limitation of the ON current, the ON current is a condition to be introduced in proportion to W / L, the condition of the ON current in the experimental results of the decrease in △ L less than 1.5㎛ at W / L = 0.5 It was introduced.

As shown in Table 1, Experimental Examples 1, 3, 4, and 6 satisfying Equation 4 could secure ON currents.

In addition, as the preferable condition for further securing the ON current from Equation 4 ', the ON current can be ensured by Equation 4 above.

△ L <1.5 ㆍ (W / L)

In this manner, when the thin film transistor is turned off, the low concentration impurity region becomes a high resistance layer in which carriers are depleted, so that the OFF current can be reduced.

In addition, since the guideline of the length of the LDD region can be determined by Equation 3, it is not necessary to secure the LDD region more than necessary to reduce the OFF current.

In addition, Equation 3 satisfies Equation 4, so that when the thin film transistor is turned on, the low-concentration impurity region under the gate electrode is accumulated in the low-resistance region under the gate electrode due to the action of an electric field from the gate electrode. The ON current does not occur.

Therefore, the thin film transistor satisfying the above Equations 3 and 4 can sufficiently secure the ON current and at the same time reduce the OFF current.

In addition, although the channel width is performed at 5 占 퐉, in the case where the channel width W of the channel region is reduced to 2 占 퐉 or less, equations (3) and (4) are effective guidelines for fabricating the thin film transistor.

Embodiment 2-2

In this Embodiment 2-2, when forming the resist film 105b in the manufacturing process of the said Embodiment 2-1, the length of LDD area | region is not made into 1 micrometer or more and 1.5 micrometer or less using the said alignment mark. In the inspection step in which the LDD region has a length of 1 µm or more and 1.5 µm or less, a thin film transistor having the LDD region within the above range can be obtained.

Therefore, it is possible to sufficiently secure the ON current and to suppress the OFF current less.

Incidentally, in the above Embodiment 2-2, the length of the LDD region is not limited to 1 µm or more and 1.5 µm or less, and may be in the ranges of the equations (3) and (4) described in the above Embodiment 2-1.

(Other matter)

In the above Embodiments 2-1 and 2-2, the low concentration impurity region having one type of concentration has been described. However, the present invention is not limited thereto, and a plurality of low concentration impurity regions having different concentration differences may be formed.

That is, by constructing a plurality of junction regions where the impurity concentration gradually decreases as the low concentration impurity region is directed toward the channel region, the impurity concentration can be changed in multiple steps, thereby further reducing the concentration of the electric field in the semiconductor layer. Can be.

In addition, the low concentration impurity region may be formed only between the drain region and the channel region. With this configuration, it is possible to obtain the effect of reducing the OFF current and to reduce the area of the thin film transistor. In addition, the thin film transistor can be applied to other than the liquid crystal display device.

As the C-MOS inverter circuit, at least n-channel thin film transistors among the p-channel thin film transistors and the n-channel thin film transistors may be constituted by the thin film transistors according to the embodiments 2-1 and 2-2.

As explained above, according to the structure of this invention, the subject of this invention can fully be achieved.

That is, in the first invention group, the ON current can be sufficiently secured and the photoconductive current during light irradiation can be suppressed to be small, and the power consumption is small, so that the effect is very large for the improvement of reliability and the improvement of characteristics.

Further, in the second invention group, the ON current can be sufficiently secured and the OFF current can be suppressed to be small, so that the power consumption is small, thereby providing a thin film transistor which is very effective in improving reliability and improving characteristics. can do.

Claims (20)

A channel region, and a polycrystalline silicon semiconductor layer having source and drain regions disposed on both sides of the channel region, A depletion layer is formed between the channel region and the drain region, The width of the depletion layer is proportional to the photoconductive current generated when light is irradiated to the channel region, and the width of the depletion layer is obtained based on the proportional relationship in order to keep the photoconductive current within a predetermined allowable value. A thin film transistor, characterized in that the configuration below the value. The thin film transistor according to claim 1, wherein the relationship of the formula (1) is satisfied when the sheet resistance of the drain region is R (k? / □) and the channel width of the channel region is W (µm). (R + 30) W <A (1) 3. The thin film transistor according to claim 2, wherein the relation of the formula (2) is satisfied when the sheet resistance of the drain region is R (k? /?) And the channel width of the channel region is W (µm). (R + 30) W <1 x 10 ³ (2) The thin film transistor according to claim 3, wherein the channel width (W) of the channel region is 2 mu m or less. 4. The thin film transistor according to claim 3, wherein the sheet resistance of said drain region is 20 k? /? Or more and 100 k? /? Or less. The thin film transistor according to claim 4, wherein the sheet resistance of the drain region is 20 k? /? Or more and 100 k? /? Or less. A thin film transistor having a channel region and a polycrystalline silicon semiconductor layer having source and drain regions disposed on both sides of the channel region, and provided as a switching element in a liquid crystal display device. When the luminance of the backlight constituting the liquid crystal display device is 2000 (cd / m ² ) or more, at least one of the space between the source region and the channel region or between the drain region and the channel region, A low concentration impurity region having an impurity concentration lower than the source region and the drain region is formed, and the length (ΔL) of the low concentration impurity region is 1.0 μm or less, The sheet resistance of the low concentration impurity region is a thin film transistor, characterized in that 20kΩ / □ or more and 100kΩ / □ or less. A channel region and source and drain regions disposed on both sides of the channel region are formed, and at least one of the source region and the channel region or between the drain region and the channel region has an impurity concentration in the source region and A thin film transistor having a polycrystalline silicon semiconductor layer having a lower concentration impurity region than a drain region, When the length of the low concentration impurity region is ΔL (µm), the source-drain voltage is Vlc (V), and the channel width of the channel region is W (µm), the relation of Equation 3 is satisfied. Thin film transistor. ΔL> (WVlc) / 36 (3) The thin film transistor according to claim 8, wherein the relationship of the equation (4) is satisfied when the channel length of the channel region is L (µm). △ L <1.5 ㆍ (W / L) (4) The thin film transistor according to claim 9, wherein a channel width (W) of the channel region is 2 mu m or less. 10. The thin film transistor according to claim 9, wherein the sheet resistance of the low concentration impurity region is 20 kΩ / □ or more and 100 kΩ / □ or less. The thin film transistor according to claim 10, wherein the sheet resistance of the low concentration impurity region is 20 kΩ / □ or more and 100 kΩ / □ or less. 12. The thin film transistor according to claim 11, wherein the low concentration impurity region is formed only between the drain region and the channel region. A liquid crystal panel unit comprising the thin film transistor according to claim 1 as a switching element; A liquid crystal display device comprising a backlight unit for supplying light from the rear surface side of the liquid crystal panel unit. When the sheet resistance of the drain region is R (kΩ / □), the brightness of the backlight portion is B (cd / m ² ), and the channel width of the channel region is W (μm), the relation of Equation 5 is satisfied. Liquid crystal display device characterized in that. (R + 30) BW W <C (5) 15. The equation of claim 14, wherein the sheet resistance of the drain region is R (kΩ / □), the brightness of the backlight portion is B (cd / m ² ), and the channel width of the channel region is W (μm). A liquid crystal display device which satisfies the relationship of 6. (R + 30) B W <1 × 10 ⁶ (6) An EL device having a light emitting layer on an upper layer of a pixel electrode formed on a substrate having a thin film transistor, and an counter electrode formed on the light emitting layer, The thin film transistor is the thin film transistor according to claim 1, and when the light intensity irradiated to the channel region of the thin film transistor is set to B (cd / m ² ), the relation of the expression (5) is satisfied. Device. (R + 30) BW W <C (5) 17. The method of claim 16, wherein the sheet resistance of the drain region is R (kΩ / □), the light intensity irradiated to the channel region is B (cd / m ² ), and the channel width of the channel region is W (μm). In this case, the EL display device characterized by satisfying the relation of expression (6). (R + 30) B W <1 × 10 ⁶ (6) A polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on the insulating substrate, A gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon semiconductor layer; A gate electrode forming step of forming a gate electrode in a pattern form on the gate insulating film; An anode oxidation step of oxidizing a side surface of the gate electrode to form a metal oxide film covering the side surface of the gate electrode; A method of manufacturing a thin film transistor having an impurity doping step of doping an impurity with the gate electrode as a mask on the polycrystalline silicon semiconductor layer, By controlling the film thickness of the metal oxide film formed in the anodic oxidation process, the length (ΔL) of the low concentration impurity region formed in the impurity doping process is 1.0 μm or less, Method of manufacturing a thin film transistor wherein the doping of said impurity is carried out acceleration voltage of 10kV or more is less than 30kV and a beam current density from 0.05㎂ / cm ² or more 1㎂ / cm ² or less. A polycrystalline silicon semiconductor layer forming step of forming a polycrystalline silicon semiconductor layer on an insulating substrate, A gate insulating film forming step of forming a gate insulating film on the polycrystalline silicon semiconductor layer; A gate electrode forming step of forming a gate electrode in a pattern form on the gate insulating film; A first impurity doping step of doping an impurity with the gate electrode as a mask on the polycrystalline silicon semiconductor layer; A shielding film forming step of forming a shielding film on the semiconductor region doped with impurities by the first impurity doping step, and forming the shielding film in a pattern by anisotropic etching; The polycrystalline silicon semiconductor layer is doped with impurities using the shielding film as a mask, and an impurity concentration difference exists between the lower region and the other region of the shielding film so that the source region and the channel region or between the drain region and the channel region. And a second impurity doping step of forming a low concentration impurity region having an impurity concentration lower than the source region and the drain region in at least one of them, and having a length of the low concentration impurity region of 1.0 m or less. . 20. The method of manufacturing a thin film transistor according to claim 19, further comprising an inspection process for producing a good product wherein the low concentration impurity region has a length? L of 1.0 mu m or less.