KR100464397B1 - Word Line Precharge Control Circuit of Semiconductor Memory Device - Google Patents

Abstract

The present invention discloses a word line precharge control circuit of a semiconductor memory device for keeping the speed of disabling word lines in normal precharge and automatic precharge commands by adding delay means. It is input together with the normal precharge command that inputs from the outside after the data read / write operation is completed and disables the word line or the data read / write command, and then automatically after the data read / write operation is completed. In a word line precharge control circuit of a semiconductor memory device which inputs an auto-precharge command for disabling a word line, an operation is performed when the normal precharge command is input. And a first circuit portion including a first signal delay means, a second circuit portion operating when the Auto-Precharge command is input and including a second signal delay means, and the first circuit portion or the second circuit portion. And a third circuit section for outputting a row master signal? R for disabling the word line by inputting the signal output from the circuit section.

Description

Word Line Precharge Control Circuit of Semiconductor Memory Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to word line precharge control circuits in semiconductor memory devices for maintaining a constant speed of disabling word lines in normal precharge and automatic precharge commands.

In the DRAM, there are a low active command for enabling a specific word line and a normal precharge command for disabling the enabled word line. In particular, in the synchronous DRAM, there is an auto precharge command in addition to the normal precharge command. The normal precharge command is input and executed from the outside after the read / write operation of data is completed. When the read / write command of the data is input, the automatic precharge command is input together by setting a specific address to logic high to automatically disable the word line at the next clock cycle after the burst read / write is completed.

1 is a word line precharge control circuit of a conventional semiconductor memory device.

Referring to FIG. 1, the word line precharge control circuit includes a first circuit unit 1 and an auto-precharge operating when a normal precharge command is input to a semiconductor memory device. A second circuit portion 2 operating when a command is input, and a third circuit portion 3 operating when the low precharge command or the automatic precharge command is input.

The first circuit unit 1 includes an internal column address strobe signal ΦCAS and an internal write enable signal ΦWE buffered with the column address strobe bar signal CASB and the write enable bar signal WEB, respectively, and the normal free signal. A charge signal ΦRP is input.

In this case, the normal precharge signal ΦRP is a pulse signal generated in synchronization with the internal clock when the internal row address strobe signal ΦRAS buffered with the row address strobe bar signal RASB is logic low.

Referring to the configuration of the first circuit unit 1, the inverter 3 to input and invert the internal write enable signal (ΦWE), the internal column address strobe signal (ΦCAS), the internal write enable signal (ΦWE) ) And a first NAND gate 11 inputting the normal precharge signal? RP, a signal output from the inverter 3, the internal column address strobe signal? CAS, and the normal precharge signal. A second NAND gate 12 having ΦRP as an input, an inverter 14 connected to an output terminal of the second NAND gate 12, and a first NMOS transistor 15 connected to an output terminal of the inverter 14. Include.

The second circuit unit 12 includes a second NMOS transistor 16 having an automatic precharge signal ΦAP input to a gate thereof and a drain thereof connected to a drain of the first NMOS transistor 15.

In this case, the first node N1 represents a common output terminal of the first and second circuit units 1 and 2.

The third circuit unit 3 is supplied with a power supply voltage Vcc to a drain, a gate is connected to an output terminal of the first NAND gate 15, and a source is connected to the first node N1. A latch means comprising inverters 22 and 23 at a source of the PMOS transistor 21 and a low master connected to an output terminal of the inverter 22 to enable / disable a word line W / L. An inverter 24 for outputting a signal? R, and signal delay means 25 for delaying the row master signal? R at the output terminal of the inverter 24 and then transmitting it to the word line W / L. It includes.

When the low-active command is input to the semiconductor memory device, the internal column address strobe signal Φ CAS and the internal write enable signal ΦWE are logic high and the normal precharge signal ΦRP is generated. As a result, the PMOS transistor 21 is turned on so that the first node N1 is latched to a logic high, so that the low master signal Φ R is logic high to enable the word line W / L.

When the normal precharge command is input to the semiconductor memory device, the internal column address strobe signal Φ CAS is logic high and the internal write enable signal Φ WE is logic low and the normal precharge signal ΦRP is generated. do. As a result, the first NMOS transistor 15 is turned on so that the first node N1 is latched to a logic low so that the row master signal Φ R is logic low and the word line W / L is disabled. .

In addition, when an automatic precharge command is input to the semiconductor memory device, the automatic precharge signal ΦAP is generated so that the second NMOS transistor 16 is turned on so that the first node N1 is latched to a logic low. As a result, the row master signal Φ R is logic low so that the word line W / L is disabled.

FIG. 2 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 1 when a normal precharge command is input to a semiconductor memory device.

Referring to FIG. 2, when a normal precharge command is input at the rising edge of the clock CLOCK, the internal column address strobe signal Φ CAS is logic high and the internal write enable signal ΦWE and the internal low address strobe are generated. Signal Φ RAS is logic low to generate a normal precharge signal Φ RP.

First, when the normal precharge signal Φ RP is logic high, the first N-P transistor 15 (FIG. 1) is turned on so that the first node (N1 in FIG. 1) is logic low, and as a result, the low master signal Φ R is Is logic low.

Thereafter, even when the normal precharge signal ΦRP is logic low and the first NP transistor 15 of FIG. 1 is turned off, the first node N1 is latched to a logic low state. ΦR) remains logic low.

3 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 1 when an automatic precharge command is input to a semiconductor memory device.

Referring to FIG. 3, the automatic precharge command is input together when a read / write command of data is input, and is automatically executed at the rising edge of the next clock CLOCK after the read / write command is completed.

Therefore, after a predetermined time at the start point of the automatic precharge, an automatic precharge signal ΦAP in a pulse form is generated.

First, when the automatic precharge signal ΦAP is logic high, the second NP transistor 16 of FIG. 1 is turned on so that the first node N1 of FIG. 1 is logic low, and as a result, the low master signal ΦR is Is logic low.

Since the automatic precharge signal ΦAP is logic low and the second NP transistor 16 of FIG. 1 is turned off, since the first node N1 is latched to a logic low state, the row master signal ( ΦR) remains logic low.

2 and 3, it can be seen that the time points at which the low master signal Φ R is logic low based on the start point of the normal precharge command and the automatic precharge command are different from each other.

In other words, the speed at which the low master signal? R is logic low after the automatic precharge is started is delayed by a predetermined time? Pre after the normal precharge command. This causes a problem of increasing an ash parameter (AC parameter) such as a first time tRDL, which is a time until the precharge after the last data is input, and a second time, tRP, which is a precharge time.

For example, when the speed at which the low master signal ΦR is logic low after the normal precharge command is higher than the speed at which the low master signal ΦR is logic low after the automatic precharge starts, the first time. (tRDL) is greater in the normal precharge and the second time (tRP) is greater in the automatic precharge.

Such speed differences may be larger due to various factors in the layout, such as differences in bus line lengths and differences in load.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a word line precharge control circuit of a semiconductor memory device for maintaining a constant speed for disabling word lines in a normal precharge and automatic precharge command.

In order to achieve the above object, the present invention, after the read / write operation of the data is completed is input from the outside with a normal precharge (Normal Precharge) command or a data read / write command to disable the word line of the data In a word line precharge control circuit of a semiconductor memory device which inputs an auto-precharge command that automatically disables a word line after a read / write operation is completed,

A first circuit portion operating when the normal precharge command is input and including a first signal delay means, operating when the auto precharge command is input and a second signal delay means A second circuit unit including a third circuit unit configured to output a row master signal? R for disabling a word line by inputting a signal output from the first circuit unit or the second circuit unit;

By adjusting the delay time of the first and second signal delay means and the speed until the low master signal (ΦR) is disabled through the first and the third circuit unit after the normal precharge command is input; And at a time point at which the automatic precharge starts, the speed until the row master signal? R is disabled through the second and third circuit units is constant. Aji control circuit is provided.

After the normal precharge command is input, the speed until the low master signal Φ R is disabled until the low master signal Φ R is disabled at the time when the automatic precharge starts. If it is faster than the speed, the delay time of the first signal delay means is increased by the time corresponding to the speed difference, and the speed until the low master signal Φ R is disabled at the time when the automatic precharge starts. Is larger than the speed until the row master signal Φ R is disabled after the normal precharge command is input, increasing the delay time of the second signal delay means by a time corresponding to the speed difference. desirable.

The first circuit part includes a first NAND gate inputting an internal column address strobe signal Φ CAS, an internal write enable signal ΦWE, and a normal precharge signal ΦRP, and the internal write enable signal ΦWE. Is a first inverter for inverting the input, a signal output from the inverter, a second NAND gate inputting the internal column address strobe signal Φ CAS, and the normal precharge signal ΦRP, and the second A second inverter connected to an output terminal of the NAND gate, first signal delay means connected to an output terminal of the second inverter to delay a signal output from the second inverter by a predetermined time, and a gate is connected to an output terminal of the first signal delay means. And a first NMOS transistor connected, wherein the second circuit unit receives an automatic precharge signal? AP as an input and delays the predetermined time. And a second NMOS transistor connected to an output terminal of the second signal delay means, wherein the third circuit portion is supplied with a power supply voltage Vcc to a drain and a gate of the first NAND gate. PMOS transistor coupled to the output terminal and the source connected to the drains of the first and second NMOS transistors, a low master signal (ΦR) for latching a signal shown in the source of the PMOS transistor to enable / disable word lines. ) And a third signal delay means for delaying the signal output from the latch means for a predetermined time and transmitting the signal to the word line.

By adjusting the delay time of the first to third signal delay means, the word line is decoded at a time until the word line is disabled after the normal precharge command is input and at the time when the automatic precharge starts. It is desirable to keep the speed until enabled.

The normal precharge signal ΦRP is a pulse signal generated in synchronization with an internal clock when a normal precharge command is input to the semiconductor memory device, and the automatic precharge signal ΦAP is automatically pre-loaded to the semiconductor memory device. It is preferable that the pulse signal is generated in synchronization with the internal clock when the charge command is input.

The internal column address strobe signal Φ CAS and the internal write enable signal ΦWE are preferably a signal in which the column address strobe bar signal CASB and the write enable bar signal WEB are respectively buffered in the semiconductor memory device. Do.

The internal column address strobe signal Φ CAS and the internal write enable signal ΦWE are logic high and the word line is enabled when the normal precharge signal ΦRP occurs, and the internal column address strobe signal ΦCAS ) Is logic high and the internal write enable signal ΦWE is logic low and the word line is disabled when the normal precharge signal ΦRP occurs or when the automatic precharge signal ΦAP occurs. It is preferable.

Accordingly, the word line precharge control circuit of the semiconductor memory device according to the present invention is associated with precharge by adding delay means to make the rate of disabling word lines in normal precharge and automatic precharge commands constant. The AC parameter can be minimized.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a word line precharge control circuit of the semiconductor memory device according to the present invention.

Referring to FIG. 4, the word line precharge control circuit includes a first circuit unit 41 and an auto-precharge operating when a normal precharge command is input to a semiconductor memory device. A second circuit portion 42 operating when a command is input, and a third circuit portion 43 operating when the low precharge command or the automatic precharge command is input.

The first circuit part 41 includes an internal column address strobe signal ΦCAS and an internal write enable signal ΦWE buffered with the column address strobe bar signal CASB and the write enable bar signal WEB, respectively, and the normal free signal. A charge signal ΦRP is input.

In this case, the normal precharge signal ΦRP is a pulse signal generated in synchronization with a clock when the internal row address strobe signal ΦRAS buffered with the row address strobe bar signal RASB is logic low.

Looking at the configuration of the first circuit section 41, the first inverter 53, the internal column address strobe signal (ΦCAS), the internal write enable signal to invert it by inputting the internal write enable signal (ΦWE) as an input A first NAND gate 51 for inputting ΦWE and the normal precharge signal ΦRP, a signal output from the first inverter 53, the internal column address strobe signal ΦCAS, and the normal A second NAND gate 52 that receives a precharge signal ΦRP, a second inverter 54 connected to an output terminal of the second NAND gate 52, and an output terminal of the second inverter 54. A first signal delay means 55 for delaying the signal output from the second inverter 54 and a first NMOS transistor 56 whose gate is connected to an output terminal of the first signal delay means 55. .

The second circuit section 42 has a second signal delay means 61 for inputting an automatic precharge signal? AP and delaying it for a predetermined time, and a gate connected to an output terminal of the second signal delay means 61. The second NMOS transistor 62 is included.

The automatic precharge signal ΦAP is a pulse signal that is automatically generated in synchronization with a clock after an automatic precharge command is input and data read / write operations are completed.

The first node N1 is a point at which the drain of the second NMOS transistor 62 is connected to the drain of the first NMOS transistor 56.

The third circuit part 43 is supplied with a power supply voltage Vcc to a drain, a gate is connected to an output terminal of the first NAND gate 51, and a source is connected to the first and second NMOS transistors 56 and 62. A PMOS transistor 71 connected to the drain and a source formed at the source of the PMOS transistor 71 to latch and enable the signal of the first node N1 to enable / disable the word line W / L. Inverters 72, 73 and 74, which are latch means for outputting a master signal Φ R, are connected to an output terminal of the inverter 74 and a third signal delay for transmitting the output signal to the word line W / L. Means 75.

In this case, the inverters 72 and 74 are connected in series and the inverter 73 is connected in parallel with the inverter 72.

The first and second signal delay means (55, 61), the low master signal (ΦR) is logic low after the normal precharge signal (ΦRP) and the automatic precharge signal (ΦAP) is generated The time point, that is, the time point at which the word line W / L is disabled, is added to be the same.

When the low-active command is input to the semiconductor memory device, the internal column address strobe signal Φ CAS and the internal write enable signal ΦWE are logic high and the normal precharge signal ΦRP is generated. As a result, the PMOS transistor 71 is turned on so that the first node N1 is latched to a logic high, so that the low master signal Φ R is logic high to enable the word line W / L.

When the normal precharge command is input to the semiconductor memory device, the internal column address strobe signal Φ CAS is logic high and the internal write enable signal Φ WE is logic low and the normal precharge signal ΦRP is generated. do. As a result, the first NMOS transistor 56 is turned on so that the first node N1 is latched to a logic low so that the row master signal Φ R is logic low and the word line W / L is disabled. .

In addition, when an automatic precharge command is input to the semiconductor memory device, the automatic precharge signal ΦAP is generated so that the second NMOS transistor 62 is turned on so that the first node N1 is latched to a logic low. As a result, the row master signal Φ R is logic low so that the word line W / L is disabled.

5 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 4 when a normal precharge command is input to a semiconductor memory device.

Referring to FIG. 5, when the normal precharge command is input at the rising edge of the clock CLOCK, the internal column address strobe signal Φ CAS is logic high and the internal write enable signal ΦWE and the internal low address strobe are generated. Signal Φ RAS is logic low to generate a normal precharge signal Φ RP.

First, when the normal precharge signal ΦRP is logic high, the second NAND gate 52 (52 in FIG. 4) outputs a logic low to turn on the first NP transistor 56 in FIG. 1, and as a result, the first node ( N1 of FIG. 4 is logic low, and the row master signal Φ R is logic low.

Thereafter, even when the normal precharge signal ΦRP is logic low and the first NP transistor 56 is turned off, since the first node N1 is latched to a logic low state, the row master signal ( ΦR) remains logic low.

6 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 4 when an automatic precharge command is input to a semiconductor memory device.

Referring to FIG. 6, the automatic precharge command is input together when a read / write command of data is input and is automatically executed at the rising edge of the next clock CLOCK after the read / write command is completed.

Therefore, after a predetermined time at the start point of the automatic precharge, an automatic precharge signal ΦAP in the form of a pulse is generated.

First, when the automatic precharge signal ΦAP is logic high, the second NP transistor 62 of FIG. 4 is turned on so that the first node N1 of FIG. 4 is logic low, and as a result, the low master signal ΦR is Is logic low.

Since the automatic precharge signal ΦAP is logic low and the second NP transistor 62 of FIG. 4 is turned off, since the first node N1 is latched to a logic low state, the row master signal ( ΦR) remains logic low.

At this time, by adjusting the delay times of the first and second signal delay means (55, 61 of FIG. 4) it is possible to match the time when the row master signal (Φ R) in the logic low in FIGS.

For example, the speed from when the normal precharge command is input until the row master signal Φ R is logic low is greater than the speed from the start of the automatic precharge to the logic low of the low master signal Φ R. If the predetermined time Δpre is early, the delay time of the first signal delay means 55 is increased by the predetermined time Δpre.

Also, the speed from the automatic precharge start point until the low master signal ΦR is logic low is higher than the speed from the normal precharge command after the normal precharge command is input until the low master signal ΦR is logic low. When the predetermined time Δpre is early, the delay time of the second signal delay means 61 is increased by the predetermined time Δpre.

The present invention is not limited to this, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, the word line precharge control circuit of the semiconductor memory device according to the present invention adds delay means to make the rate of disabling word lines constant in normal precharge and automatic precharge commands. It is possible to minimize the AC parameter associated with the precharge.

1 is a word line precharge control circuit of a conventional semiconductor memory device.

FIG. 2 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 1 when a normal precharge command is input to a semiconductor memory device.

3 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 1 when an automatic precharge command is input to a semiconductor memory device.

4 is a word line precharge control circuit of the semiconductor memory device according to the present invention.

5 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 4 when a normal precharge command is input to a semiconductor memory device.

6 is a timing diagram illustrating an operation state of various signals illustrated in FIG. 4 when an automatic precharge command is input to a semiconductor memory device.

Claims (11)

After the read / write operation of the data is completed, it is input together with the normal precharge command that is input from the outside to disable the word line or the read / write command of the data, and then automatically after the read / write operation of the data is completed. In a word line precharge control circuit of a semiconductor memory device which inputs an auto-precharge command for disabling a word line, A first circuit section operating when the normal precharge command is input and including a first signal delay means; A second circuit portion operating when the Auto-Precharge command is input and including a second signal delay means; And A third circuit portion configured to output a row master signal? R for disabling a word line by inputting a signal output from the first circuit portion or the second circuit portion, By adjusting the delay time of the first and second signal delay means and the speed until the low master signal (ΦR) is disabled through the first and the third circuit unit after the normal precharge command is input; And at a time point at which the automatic precharge starts, the speed until the row master signal? R is disabled through the second and third circuit units is constant. Aji control circuit. 2. The method of claim 1, wherein the speed from the time when the automatic precharge is started until the low master signal Φ R is disabled after the normal precharge command is input is generated. And a delay time of the first signal delay means is increased by a time corresponding to the speed difference when it is faster than the speed until disabled. 2. The method of claim 1, wherein the speed from when the automatic precharge is started until the low master signal Φ R is disabled is determined after the normal precharge command is input. And a delay time of the second signal delay means is increased by a time corresponding to the speed difference when it is faster than the speed until disabled. The method of claim 1, wherein the first circuit portion A first NAND gate that receives an internal column address strobe signal Φ CAS, an internal write enable signal ΦWE, and a normal precharge signal ΦRP, and the internal write enable signal ΦWE are inputted thereto. On the output terminal of the first inverter to invert, the signal output from the inverter, the internal column address strobe signal (ΦCAS), and the normal precharge signal (ΦRP) as an input, the output terminal of the second NAND gate A second connected inverter, a first signal delay means connected to an output terminal of the second inverter to delay a signal output from the second inverter by a predetermined time, and a first NMOS connected to a gate of an output terminal of the first signal delay means. Including a transistor, The second circuit portion includes second signal delay means for inputting an automatic precharge signal? AP and delaying the predetermined time, and a second NMOS transistor whose gate is connected to an output terminal of the second signal delay means; The third circuit part is supplied with a power supply voltage Vcc to a drain, a gate is connected to an output terminal of the first NAND gate, and a source is connected to drains of the first and second NMOS transistors. A latch means for outputting a row master signal? R for enabling / disabling a word line by latching a signal shown in the source of the signal source, and a third delaying a signal output from the latch means for a predetermined time to transmit the word line to the word line. And a signal delay means. The word line precharge control circuit of a semiconductor memory device. 5. The method according to claim 4, wherein the speed until the word line is disabled after the normal precharge command is input by adjusting the delay time of the first to third signal delay means and the time point at which the automatic precharge starts And maintaining a constant speed until the word line is disabled in the word line precharge control circuit of the semiconductor memory device. The method of claim 4, wherein the normal precharge signal (ΦRP) is And a pulse signal generated in synchronization with an internal clock when a normal precharge command is input to the semiconductor memory device. The method of claim 4, wherein the automatic precharge signal ΦAP And a pulse signal generated in synchronization with an internal clock when an automatic precharge command is input to the semiconductor memory device. The internal column address strobe signal (ΦCAS) and the internal write enable signal (ΦWE) have a column address strobe bar signal (CASB) and a write enable bar signal (WEB), respectively. A word line precharge control circuit of a semiconductor memory device, characterized in that it is a buffered signal. The word line of claim 4, wherein the internal column address strobe signal Φ CAS and the internal write enable signal Φ WE are logic high and the word line is enabled when the normal precharge signal ΦRP occurs. A word line precharge control circuit of a semiconductor memory device. The word line is disabled when the internal column address strobe signal Φ CAS is logic high and the internal write enable signal ΦWE is logic low and the normal precharge signal ΦRP occurs. And a word line precharge control circuit of a semiconductor memory device. The word line precharge control circuit of claim 4, wherein the word line is disabled when the automatic precharge signal is generated. 6.

Images