KR100462368B1 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR100462368B1 KR100462368B1 KR1019960075436A KR19960075436A KR100462368B1 KR 100462368 B1 KR100462368 B1 KR 100462368B1 KR 1019960075436 A KR1019960075436 A KR 1019960075436A KR 19960075436 A KR19960075436 A KR 19960075436A KR 100462368 B1 KR100462368 B1 KR 100462368B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title abstract description 14
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 47
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000010521 absorption reaction Methods 0.000 claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 20
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 14
- 230000000903 blocking effect Effects 0.000 claims abstract description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 7
- SYHGEUNFJIGTRX-UHFFFAOYSA-N methylenedioxypyrovalerone Chemical compound C=1C=C2OCOC2=CC=1C(=O)C(CCC)N1CCCC1 SYHGEUNFJIGTRX-UHFFFAOYSA-N 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract description 6
- 239000007789 gas Substances 0.000 abstract description 3
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 93
- 239000010410 layer Substances 0.000 description 16
- 150000002500 ions Chemical class 0.000 description 11
- 239000012535 impurity Substances 0.000 description 7
- 125000006850 spacer group Chemical group 0.000 description 7
- 238000009413 insulation Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 125000004433 nitrogen atom Chemical group N* 0.000 description 2
- 125000004437 phosphorous atom Chemical group 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910000149 boron phosphate Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 평탄화막인 TEOS-O3 BPSG막 상에 소정의 수분흡수 저지층을 형성하여 대기중의 수분을 흡수하지 못하도록 차단함과 더불어 리플로우시 발생되는 결정결함 등을 방지할 수 있는 반도체 소자의 제조방법을 제공하는 것으로, 트랜지스터가 구비된 반도체 기판 상에 절연막을 형성하는 단계; 절연막 상에 평탄화막으로서 플로우 산화막을 형성하는 단계; 및, 플로우 산화막을 리플로우시켜 평탄화를 이룩함과 더불어 평탄화막 상에 소정의 수분흡수 저지층을 형성하는 단계를 포함하고, 플로우 산화막은 TEOS-O3 BPSG막이고, 수분흡수 저지층을 형성하는 단계는 TEOS-O3 BPSG막의 리플로우 공정시 H2+O2 분위기에서 질소가 함유된 개스를 첨가하여 TEOS-O3 BPSG막 상에 소정의 질소 댕글링 본드막을 형성하는 것을 특징으로 한다.The present invention forms a predetermined moisture absorption blocking layer on the TEOS-O 3 BPSG film, which is a planarization film, to block the absorption of moisture in the air and to prevent crystal defects generated during reflow. A method of manufacturing a semiconductor device, the method comprising: forming an insulating film on a semiconductor substrate provided with a transistor; Forming a flow oxide film as a planarization film on the insulating film; And reflowing the flow oxide film to achieve planarization and forming a predetermined water absorption blocking layer on the planarization film, wherein the flow oxide film is a TEOS-O 3 BPSG film and forms a water absorption blocking layer. In the step of reflowing the TEOS-O 3 BPSG film, a nitrogen-containing gas may be added in an H 2 + O 2 atmosphere to form a predetermined nitrogen dangling bond film on the TEOS-O 3 BPSG film.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 TEOS-O3 BPSG막의 수분 흡수를 방지함과 더불어 리플로우시 발생되는 결정 결함을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing moisture absorption of a TEOS-O 3 BPSG film and preventing crystal defects generated during reflow.
최근 반도체 소자의 제조 기술이 향상되면서 고집적화와 고속화가 급속히 진행되고 있으며, 이에 따라 배선 설계가 자유롭고 배선 저항 및 전류 용량 등의 설정을 여유롭게 할 수 있는 다층 배선 기술에 관한 연구가 활발히 진행되고 있다. 따라서, 이러한 다층 배선의 형성시 발생되는 토플로지를 감소시키기 위한 평탄화 방법이 중요한 과제로 제시되고 있다.Recently, as the manufacturing technology of semiconductor devices has been improved, high integration and high speed have been rapidly progressed. Accordingly, studies on multilayer wiring technologies that can freely design wiring and allow setting of wiring resistance and current capacity, etc., have been actively conducted. Therefore, the planarization method for reducing the topologies generated during the formation of such multi-layered wiring has been proposed as an important problem.
일반적으로 TEOS(Tetra-Ethyl-Ortho-Silicate)와 O3를 사용한 상압 CVD(Chemical Vapor Deposition)방법은 400℃ 이하의 저농에서의 높은 이동도(mobility)를 갖으면서 보이드(void)가 없는 간격 매립(gap filling) 특성이 우수할 뿐만 아니라, 불순물 발생이 적은 TEOS로 인하여 다층 배선의 0.35㎛ 이하급 반도체 소자의 평탄화에 아주 우수하기 때문에 최근 많이 연구되고 있다.In general, atmospheric pressure chemical vapor deposition (CVD) using TEOS (Tetra-Ethyl-Ortho-Silicate) and O 3 has a high mobility at low concentrations of 400 ° C or less, and void-free gap filling. Recently, many researches have been conducted because of the excellent filling properties and the excellent planarization of the semiconductor devices of 0.35 μm or less in the multilayer wiring due to TEOS having less impurities.
반면, TEOS-O3 BPSG막은 증착 후의 수분 흡수에 의한 박막 안정성이 저하되는 단점이 있다.On the other hand, TEOS-O 3 BPSG film has a disadvantage in that the thin film stability due to moisture absorption after deposition is reduced.
상기한 TEOS-O3 BPSG막을 평탄화막으로 이용한 종래의 반도체 소자의 제조방법을 도 1A 및 도 1B를 참조하여 설명한다.A method of manufacturing a conventional semiconductor device using the TEOS-O 3 BPSG film as a planarization film will be described with reference to FIGS. 1A and 1B.
먼저, 도 1A에 도시된 바와 같이, 반도체 기판(1) 상에 공지된 방법으로 소자간 분리를 위한 필드 산화막(2)을 형성하고, 필드 산화막(2) 사이의 기판(1) 상에 게이트 절연막(3) 및 게이트(4)를 형성한다. 이어서, 게이트(4) 양 측의 기판(1)에 저농도 불순물 이온을 주입하고, 게이트(4) 양 측벽에 산화막 스페이서(5)를 형성한 다음, 스페이서(5) 양 측의 기판(1)에 고농도 불순물 이온을 주입하여 LDD(Lightly Doped Drain) 구조의 접합영역(6)을 형성한다.First, as shown in FIG. 1A, a field oxide film 2 for inter-element separation is formed on a semiconductor substrate 1 by a known method, and a gate insulating film is formed on the substrate 1 between the field oxide films 2. (3) and gate 4 are formed. Subsequently, low concentration impurity ions are implanted into the substrate 1 on both sides of the gate 4, oxide film spacers 5 are formed on both sidewalls of the gate 4, and then the substrate 1 on both sides of the spacer 5 is formed. High concentration impurity ions are implanted to form the junction region 6 of the LDD (Lightly Doped Drain) structure.
그리고 나서, 기판 전면에 층간 절연을 위한 절연용 산화막(7)을 형성하고, 절연용 산화막(7) 상에 평탄화막으로서 소정 두께의 TEOS-O3 BPSG막(8)을 증착하고 리플로우시킨다.Then, an insulating oxide film 7 for interlayer insulation is formed over the entire substrate, and a TEOS-O 3 BPSG film 8 having a predetermined thickness is deposited and reflowed on the insulating oxide film 7 as a planarization film.
도 1B에 도시된 바와 같이, 게이트(4) 상의 TEOS-O3 BPSG막(8) 및 절연용 산화막(7)을 식각하여 게이트(4)를 소정 부분 노출시켜 콘택홀(11)을 형성한다.As shown in FIG. 1B, the TEOS-O 3 BPSG film 8 and the insulating oxide film 7 on the gate 4 are etched to expose a predetermined portion of the gate 4 to form a contact hole 11.
그러나, 상기한 바와 같이 평탄화막으로서 TEOS-O3 BPSG막(8)을 사용하는 경우 다음과 같은 문제가 발생한다.However, when the TEOS-O 3 BPSG film 8 is used as the planarization film as described above, the following problem occurs.
예컨대, TEOS-O3 BPSG막(8)을 증착한 후 대기중에 방치하였을 경우, TEOS-O3 BPSG막(8)이 수분을 쉽게 흡수하여 웨이퍼 표면에 헤이즈(haze) 형태의 결함을 발생시킬 뿐만 아니라, 장시간 방지하였을 경우에는 도 1A에 도시된 바와 같이, H3BO3와 같은 이물질(A)을 형성하게 된다. 따라서, 도 1B에 도시된 바와 같이, 이물질(A)이 소정의 식각 마스크로 작용하여, 콘택홀(11) 내에 TEOS-O3 BPSG 막(8) 및 절연용 산화막(7)의 잔류물(B)이 잔재하여 콘택저항을 증가시킨다. 또한, 이물질(A)을 발생하지 않더라도 상기 리플로우와 같은 열처리 공정에 의해 TEOS-O3 BPSG막(8)에 BPO4와 같은 소정의 결정결함이 발생된다.For example, when the TEOS-O 3 BPSG film 8 is deposited and left in the air, the TEOS-O 3 BPSG film 8 easily absorbs moisture to cause haze defects on the wafer surface. However, in the case of preventing for a long time, as shown in FIG. 1A, foreign substances A such as H 3 BO 3 are formed. Therefore, as shown in FIG. 1B, the foreign substance A acts as a predetermined etching mask, and thus, the residue B of the TEOS-O 3 BPSG film 8 and the insulating oxide film 7 in the contact hole 11. ) Remains to increase the contact resistance. In addition, even if the foreign substance A is not generated, a predetermined crystal defect such as BPO4 is generated in the TEOS-O 3 BPSG film 8 by the heat treatment process such as the reflow.
한편, 이러한 이물질 및 결정결함 등으로 인하여 심할 경우에는 금속 배선시 배선의 단락을 유발하여 소자의 수율 및 신뢰성을 저하시킨다.On the other hand, due to such foreign matters and crystal defects, in severe cases cause a short circuit of the wiring during metal wiring to reduce the yield and reliability of the device.
이에, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 플로우 산화막인 TEOS-O3 BPSG막 상에 소정의 수분흡수 저지층을 형성하여 대기중의 수분을 흡수하지 못하도록 차단함과 더불어 리플로우시 발생되는 결정결함 등을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention was created in view of the above-mentioned problems, and formed a predetermined water absorption blocking layer on the TEOS-O 3 BPSG film, which is a flow oxide film, to prevent moisture from being absorbed in the air and to reflow. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing crystal defects and the like.
상기 목적을 달성하기 위한 본 발명의 제 1 관점에 따른 반도체 소자의 제조 방법은 트랜지스터가 구비된 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막 상에 평탄화막으로서 플로우 산화막을 형성하는 단계; 및, 상기 플로우 산화막을 리플로우시켜 평탄화를 이룩함과 더불어 상기 평탄화막 상에 소정의 수분흡수 저지층을 형성하는 단계를 포함하는 것을 특징으로 한다.A semiconductor device manufacturing method according to the first aspect of the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate provided with a transistor; Forming a flow oxide film as a planarization film on the insulating film; And reflowing the flow oxide film to achieve planarization and forming a predetermined moisture absorption blocking layer on the planarization film.
또한, 상기 플로우 산화막은 TEOS-O3 BPSG막인 것을 특징으로 하고, 상기 수분흡수 저지층을 형성하는 단계는 상기 TEOS-O3 BPSG막의 상기 리플로우 공정시 H2+O2 분위기에서 질소가 함유된 개스를 첨가하여 상기 TEOS-O3 BPSG막 상에 소정의 질소 댕글링 본드막을 형성하는 것을 특징으로 한다.In addition, the flow oxide film is characterized in that the TEOS-O 3 BPSG film, the step of forming the water absorption blocking layer is nitrogen containing in the H 2 + O 2 atmosphere during the reflow process of the TEOS-O 3 BPSG film A gas is added to form a predetermined nitrogen dangling bond film on the TEOS-O 3 BPSG film.
또한, 상기 목적을 달성하기 위한 본 발명의 제 2 관점에 따른 반도체 소자의 제조방법은 트랜지스터가 구비된 반도체 기판 상에 절연막을 형성하는 단계; 상기 절연막 상에 평탄화막으로서 플로우 산화막을 형성하는 단계; 상기 플로우 산화막 상에 수분흡수 저지층을 형성하는 단계; 및, 상기 이온 주입층이 형성된 상기 플로우 산화막을 리플로우시켜 평탄화를 이룩하는 단계를 포함하는 것을 특징으로 한다.In addition, a method of manufacturing a semiconductor device according to a second aspect of the present invention for achieving the above object comprises the steps of forming an insulating film on a semiconductor substrate with a transistor; Forming a flow oxide film as a planarization film on the insulating film; Forming a water absorption blocking layer on the flow oxide film; And reflowing the flow oxide film on which the ion implantation layer is formed to achieve planarization.
또한, 상기 플로우 산화막은 TEOS-O3 BPSG막인 것을 특징으로 하고, 상기 수분흡수 저지층은 상기 TEOS-O3 BPSG막 표면에 형성된 소정의 이온을 이온 주입하여 소정의 이온 주입층을 형성하는 것을 특징으로 한다.In addition, the flow oxide film is characterized in that the TEOS-O 3 BPSG film, the moisture absorption blocking layer is characterized in that by implanting a predetermined ion formed on the surface of the TEOS-O 3 BPSG film to form a predetermined ion implantation layer. It is done.
또한, 상기 이온은 질소인 것을 특징으로 하는 반도체 소자의 제조방법.In addition, the ion is a method of manufacturing a semiconductor device, characterized in that the nitrogen.
상기 구성으로 된 본 발명에 의하면, 플로우 산화막인 TEOS-O3 BPSG막 상에 소정의 수분흡수 저지층을 형성하여 대기중의 수분을 흡수하지 못하도록 차단할 수 있다.According to the present invention having the above structure, a predetermined moisture absorption blocking layer can be formed on the TEOS-O 3 BPSG film, which is a flow oxide film, to prevent water from being absorbed in the air.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2A 및 도 2B는 본 발명의 일 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
먼저, 도 2A에 도시된 바와 같이, 반도체 기판(21) 상에 공지된 방법으로 소자간 분리를 위한 필드 산화막(22)을 형성하고, 필드 산화막(22) 사이의 기판(21) 상에 게이트 절연막(23) 및 게이트(24)를 형성한다. 이어서, 게이트(24) 양 측의 기판(21)에 저농도 불순물 이온을 주입하고, 게이트(24) 양 측벽에 산화막 스페이서(25)를 형성한 다음, 스페이서(25) 양 측의 기판(21)에 고농도 불순물 이온을 주입하여 LDD(Lightly Doped Drain) 구조의 접합영역(26)을 형성한다.First, as shown in FIG. 2A, a field oxide film 22 for element-to-element separation is formed on a semiconductor substrate 21, and a gate insulating film is formed on a substrate 21 between the field oxide films 22. FIG. 23 and the gate 24 are formed. Subsequently, low concentration impurity ions are implanted into the substrates 21 on both sides of the gate 24, and oxide film spacers 25 are formed on both sidewalls of the gate 24, and then on the substrates 21 on both sides of the spacer 25. A high concentration of impurity ions are implanted to form a junction region 26 having a lightly doped drain (LDD) structure.
그리고 나서, 기판 전면에 층간 절연을 위한 절연용 산화막(27)을 형성하고, 절연용 산화막(27) 상에 평탄화막으로서 소정 두께의 TEOS-O3 BPSG막(28)을 증착한다. 이어서, TEOS-O3 BPSG막(28)의 리플로우 공정을 진행하여 평탄화를 이룩함과 더불어 TEOS-O3 BPSG막(28) 상에 TEOS-O3 BPSG막(28)의 P 또는 B원자가 대기중의 수분을 흡수하지 못하도록 소정의 수분흡수 저지층으로서 약 5 내지 30Å의 두께로 질소 댕글링 본드막(29)을 형성한다. 즉, 질소 댕글링 본드막(29)은 상기 리플로우 공정을 약 800 내지 1,000℃의 온도에서 H2+O2 분위기로 N2O 또는 NH3 개스를 첨가하여 진행함으로써 형성한다.Then, an insulating oxide film 27 for interlayer insulation is formed over the entire substrate, and a TEOS-O 3 BPSG film 28 having a predetermined thickness is deposited on the insulating oxide film 27 as a planarization film. Then, TEOS-O 3 BPSG film 28 reflow proceeds the process, with also achieve planarization TEOS-O 3 BPSG film 28 onto the TEOS-O 3 BPSG P or B atoms atmosphere in the film 28 of the The nitrogen dangling bond film 29 is formed to a thickness of about 5 to 30 kPa as a predetermined water absorption blocking layer so as not to absorb water therein. That is, the nitrogen dangling bond film 29 is formed by adding the N 2 O or NH 3 gas to the H 2 + O 2 atmosphere at a temperature of about 800 to 1,000 ° C. in the reflow process.
도 2B에 도시된 바와 같이, 게이트(24) 상의 리플로우된 TEOS-O3 BPSG막(28) 및 절연용 산화막(27)을 식각하여 게이트(24)를 소정 부분 노출시켜 콘택홀(30)을 형성한다.As shown in FIG. 2B, the reflowed TEOS-O 3 BPSG film 28 and the insulating oxide film 27 on the gate 24 are etched to expose the gate 24 to expose a portion of the contact hole 30. Form.
즉, TEOS-O3 BPSG막(28) 상부에 형성된 질소 댕글링 본드막(29)이 TEOS-O3 BPSG막(28)의 B 또는 P원자가 대기중의 수분을 흡수하지 못하도록 차단함과 더불어 리플로우시 TEOS-O3 BPSG막(28) 재결정화를 방지한다.That is, the ripple with the nitrogen dangling bonds film 29 blocked to prevent absorbs the water in the B or P atoms atmosphere of TEOS-O 3 BPSG film 28 formed on TEOS-O 3 BPSG film 28 Low TEOS-O 3 BPSG film 28 prevents recrystallization.
한편, TEOS-O3 BPSG막(28)의 수분 흡수를 방지하기 위하여 질소 댕글링 본드막(29) 대신에 TEOS-O3 BPSG막(28) 표면에 소정의 이온 주입층(40)을 형성할 수도 있다.On the other hand, to form the desired ion-implanted layer 40 to the surface of TEOS-O 3 BPSG film 28 in place of nitrogen dangling bonds film 29 to prevent water absorption TEOS-O 3 BPSG film 28 It may be.
즉, 도 3A 및 도 3B는 상기한 이온 주입층(40)을 이용한 본 발명의 다른 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention using the ion implantation layer 40 described above.
먼저, 도 3A에 도시된 바와 같이, 반도체 기판(21) 상에 공지된 방법으로 소자간 분리를 위한 필드 산화막(22)을 형성하고, 필드 산화막(22) 사이의 기판(21) 상에 게이트 절연막(23) 및 게이트(24)를 형성한다. 이어서, 게이트(24) 양 측의 기판(21)에 저농도 불순물 이온을 주입하고, 게이트(24) 양 측벽에 산화막 스페이서(25)를 형성한 다음, 스페이서(25) 양 측의 기판(21)에 고농도 불순물 이온을 주입하여 LDD(htly Doped Drain) 구조의 접합영역(26)을 형성한다.First, as shown in FIG. 3A, a field oxide film 22 for element-to-element separation is formed on a semiconductor substrate 21, and a gate insulating film is formed on a substrate 21 between the field oxide films 22. FIG. 23 and the gate 24 are formed. Subsequently, low concentration impurity ions are implanted into the substrates 21 on both sides of the gate 24, and oxide film spacers 25 are formed on both sidewalls of the gate 24, and then on the substrates 21 on both sides of the spacer 25. A high concentration of impurity ions are implanted to form a junction region 26 having an LDD (htly doped drain) structure.
그리고 나서, 기판 전면에 층간 절연을 위한 절연용 산화막(27)을 형성하고, 절연용 산화막(27) 상에 평탄화막으로서 소정 두께의 TEOS-O3 BPSG막(28)을 증착한다. 이어서, TEOS-O3 BPSG막(28) 표면에 소정의 이온, 바람직하게는 질소 원자를 소정 깊이로 이온 주입하여 TEOS-O3 BPSG막(28) 표면에 이온 주입층(40)을 형성함으로써 수분흡수 저지층으로 작용하도록 한다. 이때, 상기 질소의 이온 주입공정은 20 내지 40KeV의 에너지에서 1×1014 내지 1×1016 원자/㎤ 의 농도로 진행한다. 그리고 나서, 이온 주입된 TEOS-O3 BPSG막(28)을 고온에서 리플로우 시켜 평탄화를 이룩한다.Then, an insulating oxide film 27 for interlayer insulation is formed over the entire substrate, and a TEOS-O 3 BPSG film 28 having a predetermined thickness is deposited on the insulating oxide film 27 as a planarization film. Then, TEOS-O 3 BPSG film 28 a predetermined ion to the surface, preferably water, by forming the ion implanted layer 40 to the surface of TEOS-O 3 BPSG film 28 by predetermined ion implantation to a depth a nitrogen atom It acts as an absorption barrier layer. At this time, the ion implantation process of nitrogen proceeds at a concentration of 1 × 10 14 to 1 × 10 16 atoms / cm 3 at an energy of 20 to 40 KeV. Then, the ion implanted TEOS-O 3 BPSG film 28 is reflowed at a high temperature to achieve planarization.
도 3B에 도시된 바와 같이, 게이트(24) 상의 TEOS-O3 BPSG막(28) 및 절연용 산화막(27)을 식각하여 게이트(24)를 소정 부분 노출시켜 콘택홀(30)을 형성한다.As shown in FIG. 3B, the TEOS-O 3 BPSG film 28 and the insulating oxide film 27 on the gate 24 are etched to expose a predetermined portion of the gate 24 to form a contact hole 30.
즉, 이온 주입층(40)은 고농도의 질소 원자가 TEOS-O3 BPSG막(28)의 표면에 분포하여 TEOS-O3 BPSG막(28)의 B 또는 P원자에 의한 수분 흡수를 차단함과 더불어 이후 진행되는 리플로우시 TEOS-O3 BPSG막(28) 재결정화를 방지한다.That is, the ion-implanted layer 40, with also the distribution on the surface of the high concentration of nitrogen atoms TEOS-O 3 BPSG film 28 blocks the moisture absorption by the B or P atom of the TEOS-O 3 BPSG film 28 In the subsequent reflow, TEOS-O 3 BPSG film 28 is prevented from recrystallization.
상기 실시예에 의하면, 평탄화막으로서 TEOS-O3 BPSG막을 사용하는 경우 TEOS-O3 BPSG막 상에 소정의 수분흡수 저지층을 형성하여 TEOS-O3 BPSG막의 P 또는 B원자가 대기중의 수분을 흡수하지 못하도록 차단할 수 있다.According to the embodiment, as a flattening film to water in the TEOS-O 3 BPSG if the film is used TEOS-O 3 BPSG film to the phase forming the desired moisture absorption blocking layer TEOS-O 3 BPSG film P or B atoms air Can be blocked from absorption.
이에 따라, 리플로우시 발생하는 결정결함을 방지할 수 있을 뿐만 아니라, TEOS-O3 BPSG막을 대기중에 방치하더라도 이물질이 발생하지 않게 되어 배선의 형성시 단락을 방지할 수 있고, 결국 소자의 신뢰성 및 수율을 향상시킬 수 있다.As a result, not only the crystal defects generated during reflow can be prevented, but even when the TEOS-O 3 BPSG film is left in the air, foreign matters are not generated, and thus short circuits can be prevented during the formation of the wiring. Yield can be improved.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
도 1A 및 도 1B는 종래의 반도체 소자의 제조방법 및 문제점을 설명하기 위한 공정 단면도.1A and 1B are cross-sectional views for describing a method and a problem of a conventional semiconductor device.
도 2A 및 도 2B는 본 발명의 일 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A and 2B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3A 및 도 3B는 본 발명의 다른 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
21 : 반도체 기판 22 : 필드 산화막21 semiconductor substrate 22 field oxide film
23 : 게이트 산화막 24 : 게이트23: gate oxide film 24: gate
25 : 스페이서 26 : 접합영역25 spacer 26 junction area
27 : 절연용 산화막 28 : TEOS-O3 BPSG막27: oxide film for insulation 28: TEOS-O 3 BPSG film
29 : 질소 댕글링 본드막 40 : 이온 주입층29: nitrogen dangling bond film 40: ion implantation layer
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0342834A (en) * | 1989-07-11 | 1991-02-25 | Seiko Epson Corp | Semiconductor device |
| KR930008971A (en) * | 1991-10-30 | 1993-05-22 | 김광호 | Method of forming interlayer insulating film of semiconductor device |
| KR950034582A (en) * | 1994-05-07 | 1995-12-28 | 김주용 | Method of forming insulating film of semiconductor device |
| KR960002520A (en) * | 1994-06-20 | 1996-01-26 | 김주용 | Method of forming interlayer insulating film of semiconductor device |
| KR960019570A (en) * | 1994-11-02 | 1996-06-17 | 김주용 | Method for preventing moisture absorption of an impurity-containing insulating film |
| JPH08203893A (en) * | 1995-01-27 | 1996-08-09 | Nec Corp | Method for manufacturing semiconductor device |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0342834A (en) * | 1989-07-11 | 1991-02-25 | Seiko Epson Corp | Semiconductor device |
| KR930008971A (en) * | 1991-10-30 | 1993-05-22 | 김광호 | Method of forming interlayer insulating film of semiconductor device |
| KR950034582A (en) * | 1994-05-07 | 1995-12-28 | 김주용 | Method of forming insulating film of semiconductor device |
| KR960002520A (en) * | 1994-06-20 | 1996-01-26 | 김주용 | Method of forming interlayer insulating film of semiconductor device |
| KR960019570A (en) * | 1994-11-02 | 1996-06-17 | 김주용 | Method for preventing moisture absorption of an impurity-containing insulating film |
| JPH08203893A (en) * | 1995-01-27 | 1996-08-09 | Nec Corp | Method for manufacturing semiconductor device |
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