KR100461974B1 - Method for fabricating partial silicide in cmos image sensor - Google Patents

Abstract

The present invention relates to a method of manufacturing a CMOS image sensor, and more particularly, to a method of selectively forming a silicide while reducing loss of a gate spacer and a gate electrode in a method of forming a selective silicide of a CMOS image sensor. The present invention for this purpose is to form a gate electrode having a nitride film spacer on the active region of the substrate; Forming an oxide film only on sidewalls of the spacer and on active regions of the pixel array region and the logic circuit region; Forming a silicide mask blocking the pixel array region and exposing only the logic circuit region; Etching the oxide film so that an oxide film formed on an active region of the logic circuit region remains at a predetermined thickness; Removing the silicide mask and etching an oxide layer on the pixel array region and the logic circuit region by a wet etching method, wherein the oxide layer remains on the active region of the pixel array region and removes the oxide layer remaining on the active region of the logic circuit region. ; And selectively forming silicide only on the gate electrode of the pixel array region, the active region of the logic circuit region, and the gate electrode.

Description

Selective silicide formation method of CMOS image sensor {Method for fabricating partial silicide in cmos image sensor}

The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method of selectively forming a silicide while reducing a loss of a spacer or a loss of a gate electrode.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal. Among them, a charge coupled device (CCD) includes individual metal-oxide-silicon (MOS) capacitors. A device in which charge carriers are stored and transported in a capacitor while being in close proximity to each other. Complementary MOS image sensors use CMOS technology that uses a control circuit and a signal processing circuit as peripheral circuits. A device employing a switching scheme that creates MOS transistors as many as pixels and sequentially detects outputs using the MOS transistors.

CCD (charge coupled device) has many disadvantages such as complicated driving method, high power consumption, high number of mask process steps, complicated process, and difficult to implement signal processing circuit in CCD chip. In order to overcome such drawbacks, the development of a CMOS image sensor using a sub-micron CMOS manufacturing technology has been studied in recent years. The CMOS image sensor forms an image by forming a photodiode and a MOS transistor in a unit pixel and sequentially detects signals in a switching method, and implements an image by using a CMOS manufacturing technology, which consumes less power and uses 30 to 40 masks as many as 20 masks. Compared to CCD process that requires two masks, the process is very simple, and it is possible to make various signal processing circuits and one chip, which is attracting attention as the next generation image sensor.

The CMOS image sensor can be broadly divided into a pixel array region including tens or millions of unit pixels, and a logic circuit region for reproducing an image by signal processing signals generated in the pixel array region.

In the structure of the pixel array region, since a light receiving element such as a photodiode is formed on the active region of the pixel array region, when the silicide process is performed to reduce electrical resistance, the pixel array region is activated. Silicide should not be formed on the region.

If the silicide is formed on the active region of the pixel array region, the image quality is reduced by reducing the amount of light incident on the light receiving element. Therefore, when the silicide process is performed in the pixel array region, silicide must be selectively formed only on the gate electrode of the pixel array region. Of course, silicides formed in the logic circuit region are typically formed on both the active region and the gate electrode.

1A to 1E illustrate a process cross-sectional view illustrating a selective silicide forming process according to the prior art, which is a diagram illustrating a silicide forming process performed in a pixel array region and a logic circuit region.

First, as shown in FIG. 1A, after forming the gate insulating film 11 and the gate electrode 12 on the substrate 10, the nitride film spacers 13 are formed on both sidewalls of the gate electrode. As the material constituting the gate electrode, polysilicon is usually used.

Subsequently, an oxide film (for example, USG film: Undoped Silicate Glass) 14 is formed along the step on the entire structure including the gate electrode 12 and the antireflection film 15 is coated on the oxide film 14 ( coating). At this time, the antireflection film 15 coated on the gate electrode 12 and the antireflection film 15 coated on the active region are coated to have a large thickness difference due to the step by the gate electrode 12. 1A, an organic material anti reflection coating is used as the antireflection film 15.

Next, as shown in FIG. 1B, the anti-reflection film 15 and the oxide film 14 on the gate electrode 12 are removed to expose the upper surface of the gate electrode 12. The antireflection film 15 is dry etched using a plasma activated with N ₂ + O ₂ gas, and the oxide film 14 is etched using a plasma activated with CHF ₃ + CF ₄ + Ar gas. When performing such an etching process has a structure as shown in Figure 1b, after removing the anti-reflection film 15 remaining on the oxide film 14, the cleaning process is performed.

Next, as shown in FIG. 1C, a silicide mask 16 is formed which blocks the pixel array region and exposes the logic circuit region.

Subsequently, as shown in FIG. 1D, the oxide film 14 existing on the active region of the logic circuit region is removed by dry etching. Dry etching is performed using a plasma activated with CHF ₃ + CF ₄ + Ar gas.

In the dry etching process of removing the oxide film 14 present on the active region of the logic circuit region, the loss 12 of the spacer 13 and the gate electrode occurs (indicated by A in Fig. 1D). In other words, in order to expose the substrate 10 by removing all of the oxide film 14 present in the active region of the logic circuit region, the etching target must be set large, so that the spacer 13 and the gate electrode 12 are also damaged. do. Referring to FIG. 1D, it can be seen that the spacer 13 and the gate electrode 12 are damaged and their height is lowered. (D> d ')

Next, as shown in FIG. 1E, after the silicide mask 16 is removed, the silicide layer is formed on the gate electrode 12 of the pixel array region, the active region of the logic circuit region, and the gate electrode 12. 17). At this time, since the oxide film 14 remains on the active region of the pixel array region, no silicide is formed on the active region of the pixel array region.

In such a selective silicide formation method according to the prior art, since the loss of the spacer 13 and the gate electrode 12 occurs, the silicide formed on the gate electrode of the logic circuit region and the silicide formed on the active region of the logic circuit region. There was a problem that caused a bridge phenomenon between the liver (indicated by B in Fig. 1e), there was a disadvantage such as a change in device characteristics due to the loss of the gate electrode.

In addition, since the etching process of exposing the substrate by removing the oxide film formed on the active region of the logic circuit region shown in FIG. 1C is performed by using dry etching, the substrate 10 is damaged.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a selective silicide formation method in which the loss of the gate electrode and the loss of the spacer are reduced in the selective silicide formation method of the CMOS image sensor.

1A to 1E are selective silicide forming methods of CMOS image sensor according to the prior art

2a to 2f are selective silicide forming method of the CMOS image sensor according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

20: substrate

21: gate insulating film

22: gate electrode

23: spacer

24: oxide film

24a: oxide film formed on active region of logic circuit area

24b: oxide film formed on active area of pixel array region

25: antireflection film

26: silicide mask

27: silicide

According to an aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor including a pixel array region and a logic circuit region, the method comprising: forming a gate electrode having a nitride film spacer on an active region of a substrate; Forming an oxide film only on sidewalls of the spacer and on active regions of the pixel array region and the logic circuit region; Forming a silicide mask blocking the pixel array region and exposing only the logic circuit region; Etching the oxide film so that an oxide film formed on an active region of the logic circuit region remains at a predetermined thickness; Removing the silicide mask and etching an oxide layer on the pixel array region and the logic circuit region by a wet etching method, wherein the oxide layer remains on the active region of the pixel array region and removes the oxide layer remaining on the active region of the logic circuit region. ; And selectively forming silicide only on the gate electrode of the pixel array region, the active region of the logic circuit region, and the gate electrode.

The present invention relates to a method of forming a selective silicide of a CMOS image sensor, and more particularly, to a method of forming a selective silicide preventing loss of a spacer and a gate electrode.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A through 2F are cross-sectional views illustrating a method of forming a selective silicide of a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, the gate insulating film 21 and the gate electrode 22 are patterned and formed on the substrate 20, and then the nitride film spacers 23 are formed on both sidewalls of the gate electrode 22. do. As the gate electrode material, polysilicon is usually used.

Subsequently, an oxide film (eg, USG film or HLD film: High temperature Low pressure Dielectrics) 24 is formed along the step on the entire structure including the gate electrode 22 and the antireflection film 25 is formed on the oxide film 24. ) Is coated. The oxide film 24 is formed to have a thickness of 700 to 1000 GPa.

At this time, the antireflection film 25 coated on the gate electrode 22 and the antireflection film 25 coated on the active region are coated to have a large thickness difference due to the step by the gate electrode 22. As the anti-reflection film 25, an organic anti-reflection film is used.

Next, as shown in FIG. 2B, the anti-reflection film 25 and the oxide film 24 on the gate electrode 22 are removed to expose the upper surface of the gate electrode 22. The antireflection film 25 is dry etched using a plasma activated with N ₂ + O ₂ gas, and the oxide film 24 is etched using a plasma activated with CHF ₃ + CF ₄ + Ar gas. When performing such an etching process has a structure as shown in Figure 2b, after removing the anti-reflection film 25 remaining on the oxide film 24 as shown in Figure 2c, and then performing a cleaning process The oxide film 24 remains only on the active region on the substrate and on the sidewalls of the spacer 23.

Next, as shown in FIG. 2D, after forming the silicide mask 26 which blocks the pixel array region and exposes the logic circuit region, the logic circuit is activated by using a plasma activated with CHF ₃ + CF ₄ + Ar gas. The oxide film 24a formed on the active region of the region is etched. At this time, the etching process is performed so that the oxide film 24a formed on the active region of the logic circuit region is etched without leaving all of the oxide film 24a.

Hereinafter, the oxide film formed on the active region of the logic circuit region is denoted by '24a' and the oxide film formed on the active region of the pixel array region is denoted by '24b'.

As such, since only the oxide film 24a formed on the active region of the logic circuit region is etched to a predetermined thickness, a difference is obtained when comparing the thickness of the oxide film 24b remaining on the active region of the pixel array region with the thickness thereof. The dry etching process is performed such that the difference is about 300 to 500 kPa.

In the exemplary embodiment of the present invention, since the oxide film 24a formed on the active region of the logic circuit region is not etched, the etching target is reduced by that amount, so that the loss of the spacer and the loss of the gate electrode can be reduced. have.

Next, as shown in FIG. 2E, after the silicide mask 26 is removed, the oxide film 24b formed on the active region of the pixel array region and the oxide film 24a formed on the active region of the logic circuit region are wet-etched.

As described above, the oxide film 24b formed in the active region of the pixel array region and the oxide film 24a remaining on the active region of the logic circuit region have a thickness difference of about 300 to 500 kV, and the active region of the logic circuit region. Since the oxide film 24a remaining on the film has only a thickness of about 100 to 200 microns, the oxide film 24a is removed on the active area of the logic circuit area and the oxide film 24 formed on the active area of the pixel array area is removed. 24b) can easily proceed the wet etching process to remain a certain thickness.

That is, after the wet etching process is performed, the oxide film 24b for preventing silicide formation remains in the active region of the pixel array region, and the oxide film 24a is removed from the active region of the logic circuit region, thereby removing the substrate ( 20) is exposed.

In addition, the wet etching method used in the embodiment of the present invention uses an etchant having a large etching selectivity between the nitride film spacer 23 and the oxide film 24 (USG film or HLD film). Few. In addition, since an etchant having a large etching selectivity between the gate electrode (polysilicon) and the oxide film 24 is used, the loss of the gate electrode is also minimal. In one embodiment of the present invention as the etchant was used HF solution or buffered oxide etchant (Buffered Oxide Etchant).

In the exemplary embodiment of the present invention, the etching target of the wet etching method is overetched to further etch 30% of the thickness of the oxide film 24a remaining in the active region of the logic circuit region. By performing such transient etching, all of the oxide film 24a remaining in the active region of the logic circuit region can be removed.

Next, as shown in FIG. 2F, tungsten silicide or cobalt silicide 27 is formed on the gate electrode 22 of the pixel array region, on the active region of the logic circuit region, and on the gate electrode 22. At this time, since the oxide film 24b remains on the active region of the pixel array region, no silicide is formed on the active region of the pixel array region.

According to an embodiment of the present invention, when forming the silicide of the CMOS image sensor, silicide may be selectively formed while preventing loss of the spacer and the gate electrode.

In addition, conventionally, a substrate is exposed by removing an oxide film existing on an active region of a logic circuit region by using a dry etching method, whereas in the exemplary embodiment of the present invention, a wet etching method is used on an active region of a logic circuit region. Since the oxide film present in the substrate is removed to expose the substrate, the substrate damage according to the prior art is also reduced.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in the art.

When the present invention is applied, the loss of the gate spacer and the loss of the gate electrode can be prevented, so that the reliability of the device operation can be ensured and the damage to the substrate can be prevented.

Claims (8)

In the method for manufacturing a CMOS image sensor comprising a pixel array region and a logic circuit region, Forming a gate electrode having a nitride film spacer on an active region of the substrate; Forming an oxide film only on sidewalls of the spacer and on active regions of the pixel array region and the logic circuit region; Forming a silicide mask blocking the pixel array region and exposing only the logic circuit region; Etching the oxide film so that an oxide film formed on an active region of the logic circuit region remains at a predetermined thickness; Removing the silicide mask and etching an oxide layer on the pixel array region and the logic circuit region by a wet etching method, wherein the oxide layer remains on the active region of the pixel array region and removes the oxide layer remaining on the active region of the logic circuit region. ; And Selectively forming silicide only on the gate electrode of the pixel array region, the active region of the logic circuit region, and the gate electrode; Method for manufacturing a CMOS image sensor comprising a. The method of claim 1, Etching the oxide film so that an oxide film formed on an active region of the logic circuit region remains at a predetermined thickness; The oxide film remaining on the active region of the logic circuit region and the oxide film formed on the active region of the pixel array region are etched to form an oxide film formed on the active region of the logic circuit region so that the thickness difference is 300 to 500Å. Method of manufacturing the CMOS image sensor. The method of claim 1, Etching the oxide film so that an oxide film formed on an active region of the logic circuit region remains at a predetermined thickness; And etching the oxide film formed on the active region of the logic circuit region so that the oxide film remaining on the logic circuit region has a thickness of 100 to 200 Å. The method of claim 1, The wet etching method is a method of manufacturing a CMOS image sensor, characterized in that using the etching selectivity between the oxide film and the nitride film spacer. The method of claim 4, wherein The wet etching method uses a etch selectivity between an oxide film and a gate electrode. The method of claim 1, The oxide film is a method of manufacturing a CMOS image sensor, characterized in that the USG film or HLD film. The method of claim 1, Forming an oxide film only on the sidewalls of the spacer and the active regions of the pixel array region and the logic circuit region, Depositing an oxide film along a step on a semiconductor substrate including the active region and the gate electrode and coating an anti-reflection film on the oxide film; Etching a predetermined portion of the anti-reflection film and the oxide film to expose an upper portion of the gate electrode; And Removing the anti-reflection film to expose a surface of the oxide film Method of manufacturing a CMOS image sensor further comprises. The method of claim 1, Selectively forming silicide only on the gate electrode of the pixel array region, the active region of the logic circuit region, and the gate electrode; A method of manufacturing a CMOS image sensor, characterized in that to form tungsten or cobalt silicide.