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KR100458295B1 - Contact plug formation method of semiconductor device - Google Patents

Contact plug formation method of semiconductor device Download PDF

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KR100458295B1
KR100458295B1 KR1019970079329A KR19970079329A KR100458295B1 KR 100458295 B1 KR100458295 B1 KR 100458295B1 KR 1019970079329 A KR1019970079329 A KR 1019970079329A KR 19970079329 A KR19970079329 A KR 19970079329A KR 100458295 B1 KR100458295 B1 KR 100458295B1
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contact
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semiconductor device
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KR19990059132A (en
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윤경렬
노재선
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562—Selective deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

본 발명은 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 금속 배선 형성 공정 중 콘택 플러그 형성시 콘택의 하부면 뿐만 아니라 콘택의 외부 및 콘택의 측벽에까지 증착되는 플러그용 금속을 NF3 플라즈마 식각을 이용하여 제거하면서 플러그를 형성시키는 방법에 관한 것임.The present invention relates to a method for forming a contact plug of a semiconductor device. In particular, during the formation of a metal wiring, a plug metal deposited not only on the bottom surface of the contact but also on the outside of the contact and the sidewall of the contact is formed using NF 3 plasma etching. To form a plug while removing the same.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

선택적 화학기상증착법을 이용한 콘택 플러그 형성 공정은 일정 증착 시간이 경과하면 증착의 선택성이 소실되어 콘택의 외부 및 콘택 측벽의 층간 절연막에도 플러그용 금속이 증착되는 문제점이 발생함.The process of forming a contact plug using a selective chemical vapor deposition method causes a problem that the selectivity of the deposition is lost after a certain deposition time, so that the metal for the plug is deposited on the outer layer of the contact and the interlayer insulating film on the contact sidewall.

3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention

선택적 화학기상증착법을 이용한 콘택 플러그 증착시 동일 반응기 내에서 NF3 플라즈마를 이용한 식각을 실시하여 불필요하게 증착된 플러그용 금속을 제거한 후, 다시 콘택 플러그 증착 공정을 진행하는 과정을 반복함.In the case of contact plug deposition using selective chemical vapor deposition, an etching process using NF 3 plasma was performed in the same reactor to remove unnecessary deposited plug metal, and then the contact plug deposition process was repeated.

4. 발명의 중요한 용도4. Important uses of the invention

반도체 소자의 금속 배선 형성 공정Metal wiring formation process of semiconductor device

Description

반도체 소자의 콘택 플러그 형성 방법Method of forming contact plug of semiconductor device

본 발명은 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 특히 금속 배선 형성 공정 중 콘택 플러그 형성시 콘택의 하부면 뿐만 아니라 콘택의 외부 및 콘택의 측벽에까지 증착되는 플러그용 금속을 NF3 플라즈마 식각을 이용하여 제거하면서 플러그를 형성시키는 방법에 관한 것이다.The present invention relates to a method for forming a contact plug of a semiconductor device. In particular, during the formation of a metal wiring, a plug metal deposited not only on the bottom surface of the contact but also on the outside of the contact and the sidewall of the contact is formed using NF 3 plasma etching. The present invention relates to a method of forming a plug while removing.

반도체 소자의 금속 배선 형성 공정 중 선택적 화학기상증착법을 이용한 콘택 플러그 공정은 블랭킷(blanket) 플러그 공정에 비하여 플러그용 금속층 증착 동안에 발생하는 콘택 내부의 키 홀(key hole)의 발생이 없고 에치 백(etchback) 공정이 요구되지 않기 때문에 공정 단순화가 가능한 장점을 가지고 있다. 일반적인 선택적 화학기상증착법을 이용한 콘택 플러그 증착 공정의 기본 원리는 층간 절연막 위에서 플러그용 금속층의 핵 생성에 요구되는 활성화 에너지가 실리콘층 위에서의 핵 생성에 요구되는 활성화 에너지에 비하여 크기 때문에, 동일 증착 조건 하에서 플러그용 금속층 핵 생성층이 형성되기까지 필요한 시간이 상태적으로 길어져 실리콘층에서는 플러그용 금속층 박막이 형성되어도 층간 절연막에서는 층이 형성되지 않는 증착 선택성이 발생하는 것으로 알려져 있다.The contact plug process using selective chemical vapor deposition (CVD) during the metallization process of semiconductor devices has no key hole inside the contact and does not generate etchback during the deposition of the metal layer for the plug as compared to the blanket plug process. Since the process is not required, the process can be simplified. The basic principle of the contact plug deposition process using the general selective chemical vapor deposition method is that the activation energy required for nucleation of the plug metal layer on the interlayer insulating film is larger than the activation energy required for nucleation on the silicon layer. It is known that the time required for the formation of the plug metal layer nucleation layer is long, so that the deposition selectivity in which the layer is not formed in the interlayer insulating film occurs even when the plug metal layer thin film is formed in the silicon layer.

선택적 화학기상증착법을 이용한 콘택 플러그 공정은 층간절연막 내로 형성된 콘택 홀에 대하여 플러그용 금속층, 예를 들어 텅스텐(W)층 증착 반응 가스인 WF5 가스를 환원가스 없이 콘택 바닥에 노출된 실리콘층과 함께 환원 반응시켜 텅스텐의 핵 생성층을 형성시키는 단계와, 이후 WF6/H2 반응계에 의한 H2 환원 공정 또는 WF6/SiH4 반응계를 이용한 SiH4 환원 공정을 적용하여 벌크(bulk) 텅스텐을 증착하는 단계로 구성되어 있다. 즉, 초기의 핵 생성 반응은 2WF6 + 3Si → 2W + 3SiF4의 실리콘 환원 반응으로 이루어진다. 그리고, 벌크 텅스텐 증착 반응으로는 WF6 + 6H2 → W + 12HF의 WF6/H2 반응계에 의한 H2 환원 반응 및 2WF6 + 3SiH4 → 2W + 3SiF4 + 6H2의 WF6/SiH4 반응계를 이용한 SiH4 환원 반응으로 이루어진다.Contact plug process using a selective chemical vapor deposition process is for the plug with respect to the contact hole formed into the interlayer insulating film metal layer, such as tungsten (W) layer deposition reaction gas, with a silicon layer exposed to contact the floor, WF 5 gas without reduction gas Forming a nucleation layer of tungsten by reduction reaction, and then depositing bulk tungsten by applying a H 2 reduction process using a WF 6 / H 2 reaction system or a SiH 4 reduction process using a WF 6 / SiH 4 reaction system. It is composed of steps. That is, the initial nucleation reaction consists of a silicon reduction reaction of 2WF 6 + 3Si → 2W + 3SiF 4 . In addition, as a bulk tungsten deposition reaction, H 2 reduction reaction by WF 6 / H 2 reaction system of WF 6 + 6H 2 → W + 12HF and WF 6 / SiH 4 of 2WF 6 + 3SiH 4 → 2W + 3SiF 4 + 6H 2 SiH 4 reduction reaction using a reaction system.

그러나 이러한 종래의 선택적 화학기상증착법을 이용한 콘택 플러그 공정은 초기 핵 생성 단계 이후의 H2 환원 공정 또는 SiH4 환원 공정 단계에서 증착 공정이 어느 정도 진행되어 층간절연막 위에서의 핵 생성층이 형성될때까지 요구되는 시간 이상이 지나면 콘택 바닥의 실리콘층에서 뿐만 아니라 콘택 측벽과 콘택 외부의 층간 절연막 위에서도 핵 생성이 가능하게 된다. 그러므로 콘택 바닥의 실리콘층에서 뿐만 아니라 층간 절연막 내에서도 증착이 일어나게 되는 문제점을 가지고 있다. 이러한 선택적 손실(selectivity loss) 발생에 의한 층간 절연막 위에서의 플러그용 금속층의 증착은 최종의 증착 공정 후 콘택 내에 증착된 플러그에 보이드가 존재하게 되는 구조로 형성되며, 층간 절연막에 대한 불량한 접착력 특성으로 인하여 층간 절연막에서의 리프팅(lifting) 현상을 발생시킬 수 있으며, 무엇보다도 선택적 화학기상증착법을 이용한 콘택 플러그 공정의 정점인 에치 백 공정의 생략이 불가능하게 된다.However, the contact plug process using the conventional selective chemical vapor deposition method is required until the deposition process is somewhat progressed in the H 2 reduction process or the SiH 4 reduction process after the initial nucleation step until the nucleation layer is formed on the interlayer insulating film. After this time has elapsed, nucleation is possible not only on the silicon layer at the bottom of the contact but also on the contact sidewall and the interlayer insulating film outside the contact. Therefore, there is a problem that deposition occurs not only in the silicon layer of the contact bottom but also in the interlayer insulating film. The deposition of the metal layer for the plug on the interlayer insulating layer caused by the selective loss is formed in a structure in which voids are present in the plug deposited in the contact after the final deposition process, and due to the poor adhesion property to the interlayer insulating layer. Lifting phenomenon in the interlayer insulating film may occur, and above all, the etch back process, which is the vertex of the contact plug process using selective chemical vapor deposition, cannot be omitted.

도면을 통하여 상세히 설명하자면, 도 1(a)은 선택적 화학기상증착법을 이용한 텅스텐 플러그 공정의 초기 핵 생성 단계를 도시한 단면도이다. 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11) 상부에 층간 절연막(12)을 증착하고 선택된 영역에 콘택 홀을 형성한다. 이후 공정으로 금속 배선을 형성하기 위한 선택적 화학기상증착법을 이용한 텅스텐 플러그 공정을 실시한다. 이 공정은 위에서 설명한 것과 같이 콘택 바닥에 노출된 기판(11)에 의한 실리콘 환원 반응에 의하여 텅스텐 핵 생성층(13A)을 50 Å 내지 800 Å의 두께로 형성시키는 것이다. 이 때 조건으로는 250 ℃ 내지 500 ℃의 온도 및 0.1 Torr 내지 10 Torr의 압력 조건하에서 WF6 반응 가스의 유량을 65 sccm 내지 100 sccm로 제어한다.1 (a) is a cross-sectional view showing the initial nucleation step of the tungsten plug process using a selective chemical vapor deposition method. An interlayer insulating layer 12 is deposited on the substrate 11 on which various elements for forming a semiconductor device are formed, and contact holes are formed in a selected region. Thereafter, a tungsten plug process using a selective chemical vapor deposition method for forming a metal wiring is performed. As described above, the tungsten nucleation layer 13A is formed to a thickness of 50 kPa to 800 kPa by the silicon reduction reaction by the substrate 11 exposed on the contact bottom as described above. At this time, the flow rate of the WF 6 reaction gas was controlled to 65 sccm to 100 sccm under a temperature of 250 ° C to 500 ° C and a pressure condition of 0.1 Torr to 10 Torr.

도 1(b)는 WF6/H2 반응계 또는 WF6/SiH4 반응계에 의한 H2 환원 반응 또는 SiH4 환원 반응에 의한 벌크 텅스텐의 증착 단계를 도시한 단면도로써, 콘택 내부의 바닥에 텅스텐층(13B)이 3,000 Å 내지 7,000 Å의 두께로 증착된다. 이 때 250 ℃ 내지 500 ℃의 온도, 0.1 Torr 내지 100 Torr의 압력 조건 하에서, WF6/H2 반응계의 경우에는 WF6의 유량이 5 sccm 내지 500 sccm, H2의 유량이 10 sccm 내지 8,000 sccm이 되도록 제어하고, WF6/SiH4 반응계의 경우에는 SiH4의 유량이 10 sccm 내지 2,000 sccm이 되도록 제어한다.Figure 1 (b) is a cross-sectional view showing the deposition of bulk tungsten by the H 2 reduction reaction or SiH 4 reduction reaction by the WF 6 / H 2 reaction system or WF 6 / SiH 4 reaction system, a tungsten layer on the bottom inside the contact 13B is deposited to a thickness of 3,000 kPa to 7,000 kPa. Under the pressure conditions are 250 ℃ to a temperature of 500 ℃, 0.1 Torr to about 100 Torr, WF 6 / for H 2 reaction system, the flow rate of the WF 6 5 sccm to about 500 sccm, the flow rate of H 2 is 10 sccm to about 8,000 sccm In the case of the WF 6 / SiH 4 reaction system, the flow rate of SiH 4 is controlled to be 10 sccm to 2,000 sccm.

도 1(c)는 층간 절연막(12) 상부에서 텅스텐의 핵 생성층이 형성되기까지 요구되는 시간 이후의 단계로써, 층간 절연막(12) 상부에서 텅스텐 증착 선택적 손실이 발생하여 콘택 내부 뿐만 아니라 콘택의 측벽 및 층간 절연막(12) 위에서도 어느정도 텅스텐층(13C)이 형성된 단면도이다.FIG. 1C is a step after a time required for the formation of a tungsten nucleation layer on the interlayer insulating film 12, and a selective loss of tungsten deposition occurs on the interlayer insulating film 12 to prevent the inside of the contact and the contact. It is sectional drawing in which the tungsten layer 13C was formed to some extent also on the side wall and the interlayer insulation film 12. As shown in FIG.

선택적 손실을 발생시키는 원인은, 증착 공정 이전 표면의 청결(cleanliness) 정도와, 증착 반응에서 발생하는 반응 부산물, 플러그용 텅스텐의 콘택 측벽에서의 국부적 증착에 의한 영향 그리고 유전체막의 종류에 따른 영향등이 있다. 이러한 인자 중에서도 증착 공정 이전의 표면의 청결 정도에 따른 선택적 손실 현상을 막기 위하여 반도체 기판 표면을 전처리(pre-treatment)하므로써 선택적 증착이 가능한 증착 시간을 증가시킬 수 있다. 그러나, 증착 반응 동안에 생성되는 반응 부산물에 의한 영향은 다른 영향에 비하여 제어하기 어렵다. 선택적 손실을 발생시키는 반응 부산물로서는 WF6/H2 반응계의 경우 HF, WFx 등이 있으며, WF6/SiH4 반응계의 경우에는 SiFx, WFx 등이 있다. 특히, SiFx 와 같은 반응 부산물은 텅스텐 증착 반응이 진행되는 동안 생성된 후, 층간 절연막 위로의 흡착 정도가 매우 높아 WF6 + 3SiF → W + 3SiF4와 같은 반응을 통하여 층간 절연막 위에서 텅스텐 증착 선택적 손실에 의한 텅스텐의 핵 생성층을 형성시킨다. 형성된 텅스텐 핵 생성층 위로는 이후의 추가적인 텅스텐의 증착 및 성장이 급격히 일어나게 된다.The causes of selective losses include the degree of cleanliness of the surface prior to the deposition process, reaction by-products from the deposition reaction, the effects of local deposition on the contact sidewalls of tungsten plugs, and the type of dielectric film. have. Among these factors, the deposition time capable of selective deposition may be increased by pre-treating the surface of the semiconductor substrate to prevent selective loss due to the cleanliness of the surface before the deposition process. However, the effects of reaction by-products generated during the deposition reaction are difficult to control compared to other effects. Reaction by-products that cause selective loss include HF and WF x in the WF 6 / H 2 reaction system, and SiF x and WF x in the WF 6 / SiH 4 reaction system. In particular, reaction by-products such as SiF x are produced during the tungsten deposition reaction, and then the adsorption onto the interlayer insulating film is very high, thus the selective loss of tungsten deposition on the interlayer insulating film through a reaction such as WF 6 + 3SiF → W + 3SiF 4. By forming a tungsten nucleation layer. Above the formed tungsten nucleation layer, further deposition and growth of further tungsten occurs.

따라서 도 1(d)에 도시된 것과 같이, 콘택 내부 뿐만 아니라 콘택의 측벽 및 층간 절연막(12) 상부에 과도한 텅스텐층 증착되어 콘택 내부에 보이드(A)를 형성시키게 된다. 이렇게 형성된 텅스텐층(13C)은 불량한 접착력에 의해서 이후의 공정에서 텅스텐 리프팅 현상을 유발시킬 수 있다.Therefore, as shown in FIG. 1D, excessive tungsten layers are deposited not only inside the contact but also on the sidewalls of the contact and the interlayer insulating layer 12 to form the void A in the contact. The tungsten layer 13C thus formed may cause tungsten lifting in a subsequent process due to poor adhesion.

본 발명은 위와 같은 문제점을 해결하여 반도체 소자의 콘택 플러그를 형성하는데 그 목적이 있다.An object of the present invention is to form a contact plug of a semiconductor device to solve the above problems.

상술한 목적을 달성하기 위한 반도체 소자의 반도체 소자의 콘택 플러그 형성 방법은, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상부에 층간 절연막을 형성하고 선택된 영역에 콘택 홀을 형성하는 단계와, 선택적 화학기상증착법을 이용하여 콘택 플러그를 형성하되, 콘택 홀 하부에 노출된 기판의 실리콘 성분과 제 1 반응 가스의 환원 반응으로 콘택 홀 하부면에 플러그를 형성시킬 초기 핵이 생성되도록 한 후, 제 2 반응 가스의 환원 공정을 적용하여 상기 초기 핵 상부에 플러그용 벌크 금속층이 형성되도록 하는 단계와, 상기 층간 절연막 상부에 플러그용 금속이 증착될 수 있는 핵 생성이 이루어지면 공정을 중지하고, NF3 플라즈마 건식 식각 방법으로 상기 층간 절연막 상부에 핵 생성으로 인해 형성된 플러그용 금속을 제거하는 단계와, 상기 선택적 화학기상증착법을 이용한 콘택 플러그의 증착 및 상기 건식 식각 공정을 반복하여 상기 콘택 홀 내부에만 플러그가 채워지도록 하는 단계를 포함하여 이루어 지는 것을 특징으로 한다.A method of forming a contact plug of a semiconductor device of a semiconductor device for achieving the above object includes forming an interlayer insulating film on a substrate on which various elements for forming the semiconductor device are formed and forming a contact hole in a selected region; The contact plug is formed by vapor deposition, and the second reaction is performed after the initial nucleus for forming the plug is formed on the bottom surface of the contact hole by a reduction reaction between the silicon component of the substrate exposed under the contact hole and the first reaction gas. Applying a gas reduction process to form a bulk metal layer for the plug on the initial nucleus; and stopping the process when nucleation is formed in which the plug metal may be deposited on the interlayer insulating layer, and stopping the NF 3 plasma dry Removing the plug metal formed by nucleation on the interlayer insulating layer by an etching method; And repeating the deposition of the contact plug using the selective chemical vapor deposition method and the dry etching process so that the plug is filled only inside the contact hole.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2(a) 내지 도 2(d)는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위해 도시한 단면도이다.2 (a) to 2 (d) are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to an exemplary embodiment of the present invention.

도 2(a)는 종래의 기술에서와 같이, 반도체 소자를 형성하기 위한 기판(21) 상부에 층간 절연막(22)을 증착하고 콘택 홀을 형성한 후, 선택적 화학기상증착법으로 콘택 플러그를 형성하는 단계를 도시한 단면도이다. 콘택 플러그 형성공정은 초기 핵 생성단계와 벌크 금속층 증착단계로 이루어진다. 먼저 초기 핵 생성단계에서는 콘택 바닥에 노출된 기판(21)에 의한 실리콘 환원 반응에 의하여 텅스텐 핵 생성층을 50 Å 내지 800 Å의 두께로 형성시킨다. 이때, 공정조건으로는 250 ℃ 내지 500 ℃의 온도 및 0.1 Torr 내지 10 Torr의 압력 조건하에서 WF6 반응 가스의 유량을 65 sccm 내지 100 sccm로 제어한다. 벌크 금속층 증착단계는 초기 텅스텐 핵 생성층 상부에 WF6/H2 반응계 또는 WF6/SiH4 반응계에 의한 H2 환원 반응 또는 SiH4 환원 반응에 의한 플러그용 벌크 텅스텐을 증착하는 공정으로 이루어지며, 벌크 텅스텐층이 3,000 Å 내지 7,000 Å의 두께로 증착된다. 이 때 250 ℃ 내지 500 ℃의 온도, 0.1 Torr 내지 100 Torr의 압력 조건 하에서, WF6/H2 반응계의 경우에는 WF6의 유량이 5 sccm 내지 500 sccm, H2의 유량이 10 sccm 내지 8,000 sccm이 되도록 제어하고, WF6/SiH4 반응계의 경우에는 SiH4의 유량이 10 sccm 내지 2,000 sccm이 되도록 제어한다. 이러한 과정을 통해, 층간 절연막(22) 상부에서 텅스텐 증착 선택적 손실이 발생하여 콘택 내부 뿐만 아니라, 콘택의 측벽 및 층간 절연막(22) 위에서도 어느 정도 텅스텐층(23A)이 형성되게 된다.2 (a) shows a method of forming a contact plug by depositing an interlayer insulating film 22 on a substrate 21 for forming a semiconductor device, forming a contact hole, and then forming a contact hole using a selective chemical vapor deposition method. It is a cross-sectional view showing the steps. The contact plug forming process consists of an initial nucleation step and a bulk metal layer deposition step. First, in the initial nucleation step, the tungsten nucleation layer is formed to a thickness of 50 kPa to 800 kPa by the silicon reduction reaction by the substrate 21 exposed on the contact bottom. At this time, as the process conditions, the flow rate of the WF 6 reaction gas is controlled to 65 sccm to 100 sccm under a temperature of 250 ° C to 500 ° C and a pressure condition of 0.1 Torr to 10 Torr. The bulk metal layer deposition step consists of depositing bulk tungsten for plugs by H 2 reduction reaction by WF 6 / H 2 reaction system or WF 6 / SiH 4 reaction system or SiH 4 reduction reaction on the initial tungsten nucleation layer, The bulk tungsten layer is deposited to a thickness of 3,000 kPa to 7,000 kPa. Under the pressure conditions are 250 ℃ to a temperature of 500 ℃, 0.1 Torr to about 100 Torr, WF 6 / for H 2 reaction system, the flow rate of the WF 6 5 sccm to about 500 sccm, the flow rate of H 2 is 10 sccm to about 8,000 sccm In the case of the WF 6 / SiH 4 reaction system, the flow rate of SiH 4 is controlled to be 10 sccm to 2,000 sccm. Through this process, tungsten deposition selective loss occurs on the interlayer insulating film 22 to form the tungsten layer 23A to some extent not only inside the contact but also on the sidewall of the contact and the interlayer insulating film 22.

이 후 공정으로 선택적 손실 발생에 의해 형성된 층간 절연막(22) 상부 텅스텐층(23A)을 동일 반응기 내에서 인-시투 공정으로 건식 식각하되, NF3 플라즈마를 사용하여 식각한다. 고주파(RF) 전력에 의해 형성된 플로린(F)기는 텅스텐을 가스 상의 WF6 형태로 성장시켜 제거하게 된다. 이 단계에서는 콘택 바닥에서부터 형성된 선택적 텅스텐(23B)도 어느 정도 식각되지만, 이러한 선택적 텅스텐의 식각 정도는 매우 미미한 양이다. 따라서 층간 절연막(22) 위에서 선택적 손실에 의해 형성된 텅스텐(23A)이 완전히 제거될때까지 NF3 플라즈마에 의한 건식 식각 공정을 적용한다. NF3 플라즈마 건식 식각은 100 W 내지 300 W의 고주파를 인가하고, 0.1 Torr 내지 10 Torr의 압력, 250 ℃ 내지 600 ℃의 온도 범위에서 NF3 가스를 10 sccm 내지 200 sccm의 유량으로 제어하여 실시한다.Subsequently, the tungsten layer 23A on the interlayer insulating layer 22 formed by selective loss in the process is dry-etched by an in-situ process in the same reactor, but is etched using NF 3 plasma. Florin (F) groups formed by high frequency (RF) power are removed by growing tungsten in the form of WF 6 in the gas phase. In this step, the selective tungsten 23B formed from the contact bottom is etched to some extent, but the etching degree of the selective tungsten is very small. Therefore, a dry etching process using NF 3 plasma is applied until the tungsten 23A formed by selective loss on the interlayer insulating film 22 is completely removed. The NF 3 plasma dry etching is performed by applying a high frequency of 100 W to 300 W, controlling the NF 3 gas at a flow rate of 10 sccm to 200 sccm at a pressure of 0.1 Torr to 10 Torr and a temperature range of 250 ° C. to 600 ° C. .

도 2(b)는 NF3 플라즈마에 의한 건식 식각 공정을 통하여 콘택의 측벽 및 층간 절연막(22) 상부에 형성된 텅스텐층(23A)을 완전히 제거한 후, WF6/H2 반응계 또는 WF6/SiH4 반응계에 의하여 벌크 텅스텐의 재 증착한 단면도이다. 이 공정은 층간 절연막(22) 위에서의 텅스텐 증착 선택적 손실이 재 발생하기 전까지 계속 진행한다.FIG. 2 (b) shows a WF 6 / H 2 reaction system or WF 6 / SiH 4 after completely removing the tungsten layer 23A formed on the sidewall of the contact and the upper part of the interlayer insulating layer 22 through a dry etching process using NF 3 plasma. It is sectional drawing which re-deposited bulk tungsten by the reaction system. This process continues until tungsten deposition selective losses on the interlayer insulating film 22 again occur.

도 2(c)는 도 2(a)와 같이 마찬가지로 층간 절연막(22) 위에 텅스텐 증착 선택적 손실이 또다시 발생하여 텅스텐 핵 생성층이 콘택의 측벽과 층간 절연막(22) 위에서 형성된 단면도이다. 이러한 형태에서는 더 이상의 증착을 진행하지 않고 NF3 플라즈마에 의한 건식 식각 공정을 반복하여 진행한다.2 (c) is a cross-sectional view in which a tungsten nucleation layer is formed on the sidewalls of the contact and the interlayer insulating film 22 again, as in FIG. In this form, the dry etching process by NF 3 plasma is repeated without further deposition.

도 2(d)는 위와 같은 선택적 플러그의 증착 및 NF3 플라즈마에 의한 건식 식각을 동일 반응기 내에서 반복적으로 진행하여 콘택 플러그(23B)를 형성한 단면도이다. 따라서, 층간 절연막(22) 위로의 텅스텐의 증착이 없고 콘택 내부로도 보이드가 형성되지 않은 구조로써, 일반적인 블랭킷 텅스텐 공정을 통한 플러그 형성 공정에서 텅스텐의 증착 이후에 진행하는 에치 백 공정이 요구되지 않으며, 콘택 내에 보이드가 형성되지 않으므로, 종래의 텅스텐 플러그 공정에 비하여 공정 단순화를 이룰 뿐만 아니라 보다 신뢰성 있는 금속 배선 구조를 형성할 수 있다.2 (d) is a cross-sectional view of forming the contact plug 23B by repeatedly performing the deposition of the selective plug and the dry etching by the NF 3 plasma in the same reactor. Therefore, since there is no deposition of tungsten on the interlayer insulating film 22 and no void is formed inside the contact, the etch back process that proceeds after the deposition of tungsten is not required in the plug forming process through a general blanket tungsten process. Since voids are not formed in the contact, the process can be simplified as compared with the conventional tungsten plug process and a more reliable metal wiring structure can be formed.

상술한 바와 같이 본 발명에 의하면, 선택적 손실에 의한 층간 절연막 위로의 플러그용 금속층 즉, 텅스텐의 증착 문제를 해결할 수 있으므로, 텅스텐의 선택적 증착 공정의 가능성을 높일 수 있다. 또한 본 발명은 종래의 플러그 형성 공정에서 요구하던 에치백 공정을 실시하지 않으므로 공정 단순화를 통한 경비 절감을 이룰 수 있을 뿐만 아니라, 콘택 내의 텅스텐에 보이드 형성이 없는 보다 신뢰성 있는 금속 배선 구조의 형성이 가능한 탁월한 효과가 있다.As described above, according to the present invention, since the problem of depositing the plug metal layer, that is, tungsten, over the interlayer insulating film due to the selective loss can be solved, the possibility of the selective deposition process of tungsten can be enhanced. In addition, since the present invention does not perform the etch back process required in the conventional plug forming process, not only can reduce the cost by simplifying the process, but also form a more reliable metal wiring structure without void formation in tungsten in the contact. Excellent effect

도 1(a) 내지 도 1(d)는 종래의 기술에 의한 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위해 도시한 단면도.1 (a) to 1 (d) are cross-sectional views for explaining a method for forming a contact plug of a semiconductor device according to the prior art.

도 2(a) 내지 도 2(d)는 본 발명의 바람직한 실시예에 따른 반도체 소자의 콘택 플러그 형성 방법을 설명하기 위해 도시한 단면도.2 (a) to 2 (d) are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11 및 21 : 반도체 기판 12 및 22 : 층간 절연막11 and 21: semiconductor substrate 12 and 22: interlayer insulating film

13A, 13B, 13C, 23A, 23B, 23C : 플러그용 텅스텐13A, 13B, 13C, 23A, 23B, 23C: Tungsten for Plug

Claims (10)

반도체 소자를 형성하기 위한 여러 요소가 형성된 기판 상부에 층간 절연막을 형성하고 선택된 영역에 콘택 홀을 형성하는 단계와,Forming an interlayer insulating film on the substrate on which various elements for forming a semiconductor device are formed and forming a contact hole in a selected region; 선택적 화학기상증착법을 이용하여 콘택 플러그를 형성하되, 콘택 홀 하부에 노출된 기판의 실리콘 성분과 제 1 반응 가스의 환원 반응으로 콘택 홀 하부면에 플러그를 형성시킬 초기 핵이 생성되도록 한 후, 제 2 반응 가스의 환원 공정을 적용하여 상기 초기 핵 상부에 플러그용 벌크 금속층이 형성되도록 하는 단계와,Forming a contact plug by using a selective chemical vapor deposition method, and by generating a first nucleus to form a plug on the bottom surface of the contact hole by a reduction reaction between the silicon component of the substrate exposed under the contact hole and the first reaction gas, Applying a reduction process of the reaction gas to form a bulk metal layer for the plug on the initial nucleus; 상기 층간 절연막 상부에 플러그용 금속이 증착될 수 있는 핵 생성이 이루어지면 공정을 중지하고, NF3 플라즈마 건식 식각 방법으로 상기 층간 절연막 상부에 핵 생성으로 인해 형성된 플러그용 금속을 제거하는 단계와,Stopping the process when nucleation is formed in which the plug metal may be deposited on the interlayer insulating film, and removing the plug metal formed by the nucleation on the interlayer insulating film by NF 3 plasma dry etching; 상기 선택적 화학기상증착법을 이용한 콘택 플러그의 증착 및 상기 건식 식각 공정을 반복하여 상기 콘택 홀 내부에만 플러그가 채워지도록 하는 단계를 포함하여 이루어 지는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.And depositing the contact plug only inside the contact hole by repeating the deposition of the contact plug and the dry etching process using the selective chemical vapor deposition method. 제 1 항에 있어서,The method of claim 1, 상기 제 1 반응 가스는 WF6인 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.And the first reaction gas is WF 6 . 제 1 항에 있어서,The method of claim 1, 상기 초기 핵은 50 Å 내지 800 Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The initial nucleus is a contact plug forming method of a semiconductor device, characterized in that formed in a thickness of 50 kPa to 800 kPa. 제 1 항에 있어서,The method of claim 1, 상기 초기 핵은 250 ℃ 내지 500 ℃의 온도, 0.1 Torr 내지 10 Torr의 압력 및 제 1 반응 가스의 유량이 65 sccm 내지 100 sccm인 조건 하에서 생성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The initial nucleus is a method of forming a contact plug of a semiconductor device, characterized in that produced under the conditions of the temperature of 250 ℃ to 500 ℃, the pressure of 0.1 Torr to 10 Torr and the flow rate of the first reaction gas is 65 sccm to 100 sccm. 제 1 항에 있어서,The method of claim 1, 상기 제 2 반응 가스는 WF6/H2 반응계 및 WF6/SiH4 반응계 중 어느 하나인 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The second reaction gas is any one of a WF 6 / H 2 reaction system and a WF 6 / SiH 4 reaction system. 제 1 항에 있어서,The method of claim 1, 상기 벌크 금속층은 3,000 Å 내지 7,000 Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The bulk metal layer is a contact plug forming method of the semiconductor device, characterized in that formed in a thickness of 3,000 Å to 7,000 Å. 제 1 항에 있어서,The method of claim 1, 상기 벌크 금속층은 250 ℃ 내지 500 ℃의 온도, 0.1 Torr 내지 100 Torr의 압력 조건 하에서 생성되는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The bulk metal layer is a method of forming a contact plug of a semiconductor device, characterized in that it is produced under a temperature of 250 ℃ to 500 ℃, pressure conditions of 0.1 Torr to 100 Torr. 제 5 항에 있어서,The method of claim 5, wherein 상기 WF6/H2 반응계는 WF6의 유량이 5 sccm 내지 500 sccm, H2의 유량이 10 sccm 내지 8,000 sccm으로 제어된 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The WF 6 / H 2 reaction system is a contact plug forming method of a semiconductor device, characterized in that the flow rate of WF 6 is controlled to 5 sccm to 500 sccm, the flow rate of H 2 is 10 sccm to 8,000 sccm. 제 5 항에 있어서,The method of claim 5, wherein 상기 WF6/SiH4 반응계는 WF6의 유량이 5 sccm 내지 500 sccm, SiH4의 유량이 10 sccm 내지 2,000 sccm으로 제어된 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The WF 6 / SiH 4 reaction system is a contact plug forming method of the semiconductor device, characterized in that the flow rate of the WF 6 is controlled to 5 sccm to 500 sccm, the flow rate of SiH 4 is 10 sccm to 2,000 sccm. 제 1 항에 있어서,The method of claim 1, 상기 NF3 플라즈마 건식 식각은 100 W 내지 300 W의 고주파를 인가하고, 0.1 Torr 내지 10 Torr의 압력, 250 ℃ 내지 600 ℃의 온도 범위에서 NF3 가스를 10 sccm 내지 200 sccm의 유량으로 제어하여 실시하는 것을 특징으로 하는 반도체 소자의 콘택 플러그 형성 방법.The NF 3 plasma dry etching is performed by applying a high frequency of 100 W to 300 W, controlling the NF 3 gas at a flow rate of 10 sccm to 200 sccm at a pressure of 0.1 Torr to 10 Torr and a temperature range of 250 ° C. to 600 ° C. A contact plug forming method of a semiconductor device, characterized in that.
KR1019970079329A 1997-12-30 1997-12-30 Contact plug formation method of semiconductor device Expired - Fee Related KR100458295B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013003676A3 (en) * 2011-06-30 2013-04-25 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials

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JPH04186827A (en) * 1990-11-21 1992-07-03 Fujitsu Ltd Manufacturing method of semiconductor device
JPH06224150A (en) * 1993-01-25 1994-08-12 Kawasaki Steel Corp Method for forming multilayer wiring structure
KR970030327A (en) * 1995-11-01 1997-06-26 김주용 Method for manufacturing metal wiring of semiconductor device
KR970030654A (en) * 1995-11-03 1997-06-26 김주용 Metal wire manufacturing method of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04186827A (en) * 1990-11-21 1992-07-03 Fujitsu Ltd Manufacturing method of semiconductor device
JPH06224150A (en) * 1993-01-25 1994-08-12 Kawasaki Steel Corp Method for forming multilayer wiring structure
KR970030327A (en) * 1995-11-01 1997-06-26 김주용 Method for manufacturing metal wiring of semiconductor device
KR970030654A (en) * 1995-11-03 1997-06-26 김주용 Metal wire manufacturing method of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013003676A3 (en) * 2011-06-30 2013-04-25 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials
US8883637B2 (en) 2011-06-30 2014-11-11 Novellus Systems, Inc. Systems and methods for controlling etch selectivity of various materials

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