KR100457161B1 - A method for forming a storage node of a semiconductor device - Google Patents
A method for forming a storage node of a semiconductor device Download PDFInfo
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- KR100457161B1 KR100457161B1 KR10-2002-0042056A KR20020042056A KR100457161B1 KR 100457161 B1 KR100457161 B1 KR 100457161B1 KR 20020042056 A KR20020042056 A KR 20020042056A KR 100457161 B1 KR100457161 B1 KR 100457161B1
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000010408 film Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 238000000206 photolithography Methods 0.000 claims description 7
- 239000010409 thin film Substances 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 9
- 230000010354 integration Effects 0.000 abstract description 7
- 230000006866 deterioration Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000002955 isolation Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000005360 phosphosilicate glass Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009271 trench method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
- H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer
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Abstract
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로,The present invention relates to a method of forming a storage electrode of a semiconductor device,
삼차원적 구조를 갖는 캐패시터를 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보하는데 있어서, 높은 에스펙트비 ( aspect ratio ) 에 따른 저장전극간의 붙음 ( leaning ) 현상을 방지하기 위하여, 저장전극용 제1도전층과 제2도전층 적층구조로 형성하되, 제1도전층과 제2도전층의 높이를 조절하여 소자의 특성 열화를 방지하고 예정된 크기의 정전용량을 가질 수 있도록 저장전극을 형성함으로써 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술이다.In order to form a capacitor having a three-dimensional structure to secure a sufficient capacitance for high integration of the semiconductor device, in order to prevent the leaning phenomenon between the storage electrodes due to a high aspect ratio, the first storage electrode A semiconductor device is formed by stacking a conductive layer and a second conductive layer, and controlling the heights of the first conductive layer and the second conductive layer to prevent deterioration of device characteristics and to form storage electrodes to have a predetermined capacitance. It is a technology to improve the yield, characteristics and reliability of the semiconductor device and thereby high integration.
Description
본 발명은 반도체소자의 저장전극 형성방법에 관한 것으로, 특히 삼차원적 구조를 갖는 캐패시터를 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보하는데 있어서, 높은 에스펙트비 ( aspect ratio ) 에 따른 저장전극간의 붙음 ( leaning ) 현상을 방지하여 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a storage electrode of a semiconductor device. In particular, in forming a capacitor having a three-dimensional structure to secure a sufficient capacitance for high integration of a semiconductor device, a storage aspect according to a high aspect ratio The present invention relates to a technology capable of improving the characteristics and reliability of devices by preventing leaning.
반도체소자가 고집적화되어 셀 크기가 감소됨에 따라 저장전극의 표면적에 비례하는 정전용량을 충분히 확보하기가 어려워지고 있다.As semiconductor devices are highly integrated and cell sizes are reduced, it is difficult to secure a capacitance that is proportional to the surface area of the storage electrode.
특히, 단위 셀이 하나의 모스 트랜지스터와 캐패시터로 구성되는 디램 소자는 칩에서 많은 면적을 차지하는 캐패시터의 정전용량을 크게 하면서, 면적을 줄이는 것이 디램 소자의 고집적화에 중요한 요인이 된다.In particular, in a DRAM device having a unit cell composed of one MOS transistor and a capacitor, it is important to reduce the area while increasing the capacitance of a capacitor, which occupies a large area on a chip, which is an important factor for high integration of the DRAM device.
그래서, ( Eo × Er × A ) / T ( 단, 상기 Eo 는 진공유전율, 상기 Er 은 유전막의 유전율, 상기 A 는 캐패시터의 면적 그리고 상기 T 는 유전막의 두께 ) 로 표시되는 캐패시터의 정전용량을 증가시키기 위하여, 하부전극인 저장전극의 표면적을 증가시켜 캐패시터를 형성하거나, 유전체막의 두께를 감소시켜 캐패시터를 형성하였다.Thus, the capacitance of the capacitor represented by (Eo × Er × A) / T (wherein Eo is the vacuum dielectric constant, Er is the dielectric constant of the dielectric film, A is the area of the capacitor and T is the thickness of the dielectric film) is increased. In order to achieve this, a capacitor is formed by increasing the surface area of the storage electrode, which is a lower electrode, or a capacitor is formed by decreasing the thickness of the dielectric film.
도 1a 내지 도 1h 는 종래기술에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.1A to 1H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(도시안됨)에 소자분리막(도시안됨)을 형성하여 활성영역(도시안됨)을 정의한다.Referring to FIG. 1A, an isolation region (not shown) is formed on a semiconductor substrate (not shown) to define an active region (not shown).
이때, 상기 소자분리막은 트렌치 방법을 이용하여 형성한다.In this case, the device isolation layer is formed using a trench method.
그 다음, 상기 반도체기판 상부에 게이트전극인 워드라인(도시안됨), 비트라인(도시안됨) 및 저장전극 콘택플러그(13)가 형성된 하부절연층(11)을 형성한다.Subsequently, a lower insulating layer 11 having a word line (not shown), a bit line (not shown), and a storage electrode contact plug 13, which are gate electrodes, is formed on the semiconductor substrate.
이때, 상기 하부절연층(11)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성이 우수한 절연물질로 형성한다.In this case, the lower insulating layer 11 is made of B.S.G. It is formed of an insulating material with excellent fluidity such as boro phospho silicate glass (hereinafter referred to as BPSG).
그 다음, 상기 하부절연층(11) 상부에 질화막(15)을 형성한다.Next, a nitride film 15 is formed on the lower insulating layer 11.
이때, 상기 질화막(15)은 후속 식각 공정시 버퍼층으로 사용된다.In this case, the nitride layer 15 is used as a buffer layer in a subsequent etching process.
그 다음, 상기 질화막(15) 상부에 희생산화막(17)을 증착한다. 이때, 상기 희생산화막(17)은 USG, PSG 또는 BPSG 와 같이 유동성이 우수한 절연 산화 물질로 형성한다.Next, a sacrificial oxide film 17 is deposited on the nitride film 15. In this case, the sacrificial oxide film 17 is formed of an insulating oxide material having excellent fluidity, such as USG, PSG, or BPSG.
도 1b를 참조하면, 저장전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 저장전극 콘택플러그가 노출되는 저장전극 영역(19)을 형성한다.Referring to FIG. 1B, a storage electrode region 19 through which the storage electrode contact plug is exposed is formed by a photolithography process using a storage electrode mask (not shown).
도 1c, 도 1d 및 도 1e를 참조하면, 상기 저장전극 영역(19)을 포함한 전체표면상부에 저장전극용 도전층(21)인 폴리실리콘막을 증착하고 상기 저장전극 영역(19)을 포함한 전체표면상부에 감광막(23)을 도포하고 이를 평탄화식각한다.1C, 1D and 1E, a polysilicon film, which is a conductive layer 21 for storage electrodes, is deposited on the entire surface including the storage electrode region 19 and the entire surface including the storage electrode region 19. The photosensitive film 23 is coated on the top and flattened and etched.
이때, 상기 감광막(23) 대신 산화막을 사용할 수도 있다.In this case, an oxide film may be used instead of the photosensitive film 23.
상기 평탄화식각공정은 CMP 공정으로 실시한 것이다.The planar etching process is performed by a CMP process.
도 1f를 참조하면, 전체표면상부에 감광막패턴(25)을 형성한다. 이때, 상기 감광막패턴(25)은 저장전극 마스크를 이용한 노광 및 현상 공정을 이용하여 형성한 것이다.Referring to FIG. 1F, a photosensitive film pattern 25 is formed on the entire surface. In this case, the photoresist layer pattern 25 is formed by an exposure and development process using a storage electrode mask.
도 1g 및 도 1h 를 참조하면, 상기 감광막패턴(25)을 마스크로 하여 상기 감광막(23)을 제거하고 상기 감광막패턴(25)을 제거한다.1G and 1H, the photoresist layer 23 is removed using the photoresist pattern 25 as a mask, and the photoresist pattern 25 is removed.
후속 공정으로, 상기 희생산화막(17)을 제거하여 저장전극을 형성하되, 상기 희생산화막(17)은 습식방법으로 제거한다.In a subsequent process, the sacrificial oxide film 17 is removed to form a storage electrode, but the sacrificial oxide film 17 is removed by a wet method.
그러나, 높은 에스펙트비로 인하여 상기 저장전극이 쓰러져 이웃하는 저장전극과 붙는 리닝 ( leaning ) 현상이 유발된다.However, the high aspect ratio causes the storage electrode to fall and cause a phenomenon in which the storage electrode adheres to a neighboring storage electrode.
상기한 바와 같이 종래기술에 따른 반도체소자의 저장전극 형성방법은, 저장전극의 높은 에스펙트비로 인하여 희생산화막의 제거 공정시 이웃하는 저장전극과 붙는 리닝 ( leaning ) 현상이 유발되어 소자의 수율, 특성 및 신뢰성을 저하시키고 그에 따른 반도체소자의 고집적화를 어렵게 하는 문제점이 있다.As described above, in the method of forming a storage electrode of a semiconductor device according to the related art, a high phenomenon ratio of the storage electrode causes a leaning phenomenon in which a storage electrode adheres to a neighboring storage electrode during a removal process of a sacrificial oxide, resulting in yield and characteristics of the device. And a problem of lowering reliability and making it difficult to integrate semiconductor devices.
본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 희생산화막의 제거 공정시 저장전극간의 붙음 ( leaning ) 현상이 유발되는 것을 방지하여 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 반도체소자의 저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems according to the related art, the present invention prevents the phenomenon of leaning between the storage electrodes during the removal process of the sacrificial oxide film, thereby improving the yield, the characteristics and the reliability of the semiconductor device, and thereby the semiconductor device. It is an object of the present invention to provide a method for forming a storage electrode of a semiconductor device that enables high integration of the semiconductor device.
도 1a 내지 도 1h 는 종래기술에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도.1A to 1H are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to the prior art.
도 2a 내지 도 2l 은 본 발명의 실시예에 반도체소자의 저장전극 형성방법을 도시한 단면도.2A to 2L are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device in accordance with an embodiment of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
11,31 : 하부절연층 13,33 : 저장전극 콘택플러그11,31: lower insulating layer 13,33: storage electrode contact plug
15,35 : 질화막 17 : 희생산화막15,35: nitride film 17: sacrificial oxide film
19,39,45 : 저장전극 영역 21 : 저장전극용 도전층19,39,45: storage electrode region 21: conductive layer for storage electrode
23,49 : 감광막 25,51 : 감광막패턴23,49: photosensitive film 25,51: photosensitive film pattern
37 : 제1희생산화막 41 : 저장전극용 제1도전층37: first rare layer 41: first conductive layer for the storage electrode
43 : 제2희생산화막 47 : 저장전극용 제2도전층43: second rare production film 47: second conductive layer for the storage electrode
53 : 저장전극53: storage electrode
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 저장전극 형성방법은,In order to achieve the above object, a method of forming a storage electrode of a semiconductor device according to the present invention includes:
저장전극 콘택플러그가 구비되는 하부절연층을 반도체기판 상부에 형성하고 그 상부에 제1희생산화막을 형성하는 공정과,Forming a lower insulating layer having a storage electrode contact plug on the semiconductor substrate and forming a first thin film on the upper portion of the semiconductor substrate;
저장전극 마스크를 이용한 사진식각공정으로 상기 희생산화막을 식각하여 상기 저장전극 콘택플러그를 노출시키는 저장전극 영역을 형성하는 공정과,Forming a storage electrode region to expose the storage electrode contact plug by etching the sacrificial oxide layer by a photolithography process using a storage electrode mask;
상기 저장전극 영역을 매립하는 평탄화된 저장전극용 제1도전층을 형성하는 공정과,Forming a planarized first conductive layer for the storage electrode to fill the storage electrode region;
전체표면상부에 제2희생산화막을 형성하는 공정과,Forming a second rare production film on the entire surface;
저장전극 마스크를 이용한 사진식각공정으로 상기 제2희생산화막을 식각하여 상기 저장전극용 제1도전층을 노출시키는 저장전극 영역을 형성하되, 상기 저장전극용 제1도전층을 소정두께 식각하여 트렌치를 형성하는 공정과,Photolithography process using a storage electrode mask to form the storage electrode region to expose the first conductive layer for the storage electrode by etching the second thin film, the trench by etching the first conductive layer for the storage electrode a predetermined thickness. Forming process,
상기 저장전극용 제1도전층의 트렌치를 포함한 상기 저장전극 영역 표면에 저장전극용 제2도전층을 형성하여 상기 저장전극용 제1도전층과 제2도전층으로 저장전극을 형성하는 공정을 포함하는 것과,Forming a storage electrode on the surface of the storage electrode region including the trench of the first conductive layer for the storage electrode to form the storage electrode as the first conductive layer and the second conductive layer for the storage electrode. To do that,
상기 저장전극의 높이에 따라 상기 제1희생산화막과 제2희생산화막의 두께를 조절하는 것을 특징으로 한다.The thickness of the first rare production film and the second rare production film is adjusted according to the height of the storage electrode.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2l 은 본 발명의 실시예에 따른 반도체소자의 저장전극 형성방법을 도시한 단면도이다.2A to 2L are cross-sectional views illustrating a method of forming a storage electrode of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 반도체기판(도시안됨)에 소자분리막(도시안됨)을 형성하여 활성영역(도시안됨)을 정의한다.Referring to FIG. 2A, an isolation region (not shown) is formed on a semiconductor substrate (not shown) to define an active region (not shown).
이때, 상기 소자분리막은 트렌치 방법을 이용하여 형성한다.In this case, the device isolation layer is formed using a trench method.
그 다음, 상기 반도체기판 상부에 게이트전극인 워드라인(도시안됨), 비트라인(도시안됨) 및 저장전극 콘택플러그(33)가 형성된 하부절연층(31)을 형성한다.Next, a lower insulating layer 31 having a word line (not shown), a bit line (not shown), and a storage electrode contact plug 33, which are gate electrodes, is formed on the semiconductor substrate.
이때, 상기 하부절연층(31)은 비.피.에스.지. ( boro phospho silicate glass, 이하에서 BPSG 라 함 ) 와 같이 유동성이 우수한 절연물질로 형성한다.In this case, the lower insulating layer 31 is made of B.S.G. It is formed of an insulating material with excellent fluidity such as boro phospho silicate glass (hereinafter referred to as BPSG).
그 다음, 상기 하부절연층(31) 상부에 질화막(35)을 형성한다.Next, a nitride film 35 is formed on the lower insulating layer 31.
이때, 상기 질화막(35)은 후속 식각 공정시 버퍼층으로 사용된다.In this case, the nitride layer 35 is used as a buffer layer in a subsequent etching process.
그 다음, 상기 질화막(35) 상부에 제1희생산화막(37)을 증착한다. 이때, 상기 제1희생산화막(37)은 USG, PSG 또는 BPSG 와 같이 유동성이 우수한 절연 산화 물질로 형성한다.Next, a first dilution film 37 is deposited on the nitride film 35. In this case, the first rare production film 37 is formed of an insulating oxide material having excellent fluidity, such as USG, PSG, or BPSG.
도 2b를 참조하면, 저장전극 마스크(도시안됨)를 이용한 사진식각공정으로 상기 저장전극 콘택플러그가 노출되는 저장전극 영역(39)을 형성한다.Referring to FIG. 2B, a storage electrode region 39 through which the storage electrode contact plug is exposed is formed by a photolithography process using a storage electrode mask (not shown).
도 2c 및 도 2d를 참조하면, 상기 저장전극 영역(39)을 매립하는 저장전극용 제1도전층(41)인 폴리실리콘막을 증착하고 이를 평탄화식각한다.2C and 2D, a polysilicon film, which is a first conductive layer 41 for a storage electrode, filling the storage electrode region 39 is deposited and planarized.
도 2e를 참조하면, 상기 전체표면상부에 제2희생산화막(43)을 증착한다.Referring to FIG. 2E, a second dilution film 43 is deposited on the entire surface.
이때, 상기 제2희생산화막(43)은 USG, PSG 또는 BPSG 와 같이 유동성이 우수한 절연 산화 물질로 형성한다.In this case, the second rare production film 43 is formed of an insulating oxide material having excellent fluidity, such as USG, PSG, or BPSG.
도 2f를 참조하면, 저장전극 마스크(도시안됨)를 이용한 사진식각공정을 상기 제2희생산화막(43) 및 제1저장전극용 도전층(41)을 식각하여 상기 저장전극용 제1도전층(41)에 트렌치가 형성되는 저장전극 영역(45)을 형성한다.Referring to FIG. 2F, a photolithography process using a storage electrode mask (not shown) is etched from the second rare metallization film 43 and the conductive layer 41 for the first storage electrode to etch the first conductive layer for the storage electrode. A storage electrode region 45 in which a trench is formed is formed in 41.
도 2g, 도 2h 및 도 2i를 참조하면, 상기 저장전극 영역(45) 표면을 포함한 전체표면상부에 저장전극용 제2도전층(47)인 폴리실리콘막을 증착하고 그 상부에 감광막(49)을 도포하여 평탄화한 다음, 상기 제2희생산화막(43)을 노출시키는 평탄화식각공정을 실시한다.2G, 2H, and 2I, a polysilicon film, which is a second conductive layer 47 for storage electrodes, is deposited on the entire surface including the storage electrode region 45 surface, and a photoresist film 49 is formed thereon. After applying and planarizing, a planar etching process for exposing the second rarely produced film 43 is performed.
이때, 상기 감광막(49) 대신에 산화막을 사용할 수도 있다.In this case, an oxide film may be used instead of the photosensitive film 49.
도 2j를 참조하면, 구조물 상부에 감광막패턴(51)을 형성한다.Referring to FIG. 2J, a photosensitive film pattern 51 is formed on the structure.
이때, 상기 감광막패턴(51)은 저장전극 마스크(도시안됨)를 이용한 노광 및 현상공정을 이용하여 형성한 것이다.In this case, the photoresist layer pattern 51 is formed by an exposure and development process using a storage electrode mask (not shown).
도 2k를 참조하면, 상기 감광막패턴(51)을 마스크로 하여 상기 저장전극 영역(45) 내의 감광막(49)을 제거하여 저장전극(53)을 형성한다.Referring to FIG. 2K, the storage electrode 53 is formed by removing the photoresist film 49 in the storage electrode region 45 using the photoresist pattern 51 as a mask.
도 2l을 참조하면, 상기 감광막패턴(51)을 제거한다.Referring to FIG. 2L, the photosensitive film pattern 51 is removed.
후속 공정으로 상기 제1,2희생산화막(41,47)을 제거하고, 유전체막 및 플레이트전극을 형성하여 반도체소자의 고집적화에 충분한 정전용량을 확보할 수 있는 캐패시터를 형성한다.Subsequently, the first and second rare production films 41 and 47 are removed, and a dielectric film and a plate electrode are formed to form a capacitor capable of securing a capacitance sufficient for high integration of the semiconductor device.
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 저장전극 형성방법은, 희생산화막의 제거 공정시 높은 에스펙트비를 갖는 저장전극이 무너지는 현상을 방지하기 위해 두 층의 희생산화막 구조로 적층된 구조의 저장전극을 형성함으로써 반도체소자의 수율, 특성 및 신뢰성을 향상시키고 그에 따른 반도체소자의 고집적화를 가능하게 하는 효과를 제공한다.As described above, the method of forming the storage electrode of the semiconductor device according to the present invention has a structure in which a storage electrode having a high aspect ratio is collapsed in two layers of sacrificial oxide structure in order to prevent the storage electrode from collapsing. By forming the storage electrode of the present invention, it is possible to improve the yield, characteristics and reliability of the semiconductor device, thereby providing a high integration of the semiconductor device.
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| KR101022670B1 (en) * | 2008-07-18 | 2011-03-22 | 주식회사 하이닉스반도체 | A semiconductor device having a multilayer pillar-type charge storage electrode and a manufacturing method thereof |
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| KR100881826B1 (en) * | 2007-09-07 | 2009-02-03 | 주식회사 하이닉스반도체 | Manufacturing Method of Semiconductor Device |
| KR20100092221A (en) | 2009-02-12 | 2010-08-20 | 삼성전자주식회사 | Semiconductor memory device having cylinder-type lower electrode of capacitor |
| KR101129909B1 (en) * | 2010-07-20 | 2012-03-23 | 주식회사 하이닉스반도체 | Pillar type capacitor of semiconductor device and method for forming the same |
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