KR100456983B1 - Apparatus for ATM switching of dual- rate - Google Patents

Abstract

The present invention implements a dual-rate switching device using an ATM cell multiplexer / demultiplexer to improve data transmission efficiency and to facilitate expansion to other rates. The present invention relates to a TEM switching apparatus, and the present invention provides a multiplexer for multiplexing input ATM cell data, first to fourth data memories for storing cell data multiplexed by the multiplexer, and an input channel corresponding to each output channel. Information stored in the first to fourth controllers and the first to fourth controllers for controlling the output of the stored data of the first to fourth data memories according to the information of the input channel and generating a channel selection signal. Only one channel data among the four channel data output from the first to fourth data memories is selected in response to the output channel selection signal. And the ATM cell multiplexer as a demultiplexer for demultiplexing and outputting multiplexed channel data outputted through the first to fourth channel selectors and the first to fourth channel selectors. It is possible.

Description

Apparatus for ATM switching of dual-rate

The present invention relates to a dual rate ATM switching device, and more particularly, by implementing a dual-rate switching device using an ATM cell multiplexer / demultiplexer. The present invention relates to a dual-rate ATM switching device that improves data transmission efficiency and facilitates expansion to another rate.

1 is a view showing an embodiment of a conventional shared memory type ATM switching device.

Reference numerals 11 to 11 + N denote serial / parallel converters for converting input serial data into parallel data, and reference numeral 20 denotes parallel data converted by the plurality of serial / parallel converters 11 to 11 + N. The multiplexing header information represents a multiplexer 20 which extracts and transfers the header information to the controller 40. A reference numeral 30 denotes a dual port random access memory for storing and outputting cell data, and a reference numeral 50 denotes the memory 30. Denoted by the demultiplexer to demultiplex the multiplexed data output from the reference numeral 40 denotes a controller for controlling the memory 30 and the demultiplexer 50, reference numeral 61 ~ 60 + N denotes the demultiplexer ( The parallel / serial converter converts the parallel data output from 50) into serial data.

In the conventional shared memory type ATM switching device configured as described above, the incoming cells are converted from the serial data to the parallel data in the serial / parallel converter 11. They are successively written to the dual port random access memory 30. The cell header with the internal path selection tag is sent to the controller 40, which is the memory controller, which determines the order in which the cells are read from the memory 30. The outgoing relay cell is demultiplexed by the demultiplexer 50, converted into serial form by the parallel / serial converter 61, and finally output.

Functionally this is an output queuing scheme, where the output buffers physically belong to a common buffer pool. The output buffer method is an attractive method because it can represent a given throughput under full load. In addition, sharing a common buffer pool has the advantage of minimizing the amount of buffer required to achieve a particular cell loss rate. If the traffic load on one output port is high, it can draw more buffer space until the common buffer pool is completely full. Because the buffer space is completely shared, this method requires the least amount of buffering and is very flexible because it can dynamically accommodate traffic in terms of shared memory types that can absorb large bursts for any output. For this reason, this approach is common, such as Hitachi's shared memory switch and ATT's GCNS-2000 switch.

However, such a conventional ATM switching device is capable of various geometries and applications, while the switching rate is dependent on the type of elements used and the physical path. Therefore, if the backbone switching rate changes, the efficiency decreases.

In other words, when switching the 155.52 Mbps data rate in a switch composed of ATM switching structure elements having a 622.08 Mbps switching rate, the efficiency is inferior.

Accordingly, the present invention has been proposed to solve various problems occurring in the conventional ATM switching device as described above.

An object of the present invention is to implement a dual-rate switching device using an ATM cell multiplexer / demultiplexer to improve data transmission efficiency and to expand to another rate. It is to provide a dual-rate ATM switching device to facilitate.

"Dual-rate ATM switching device" according to the present invention for achieving the above object,

The switching device is implemented to allow parallel switching with several control memories and data memories.

In addition, by implementing a switching scheme that provides sub-rate (155.52 Mbps) switching, a dual-rate switching scheme is implemented along with a full-rate (622.08 Mbps) switching scheme. In the case of sub-rate switching (155.52 Mbps), four channels of the same destination are collected to form one full-rate (622.08 Mbps) channel for desired switching.

1 is a configuration diagram of an embodiment of a conventional shared memory ATM switching device;

2 is a conceptual diagram illustrating a switching concept of the present invention;

3 is a block diagram showing the configuration of a dual-rate AT switch according to the present invention.

<Explanation of symbols for the main parts of the drawings>

310 ..... multiplexer

321 to 324 ..... 1st to 4th data memory

331 to 334 ..... 1st to 4th controller

341 to 344 ..... 1st to 4th channel selector

350 ..... Demultiplexer

Hereinafter, described in detail with reference to the accompanying drawings, preferred embodiments of the present invention according to the technical spirit as described above.

2 is a conceptual diagram illustrating an ATM switching concept of the present invention.

Reference numerals 110 to 110 + N denote sub-rate switches, and reference numeral 200 denotes full-rate switches.

Since the operations of the plurality of sub-rate switches 110 to 110 + N are the same, a detailed operation thereof will be described below with respect to only one sub-rate switch 110.

The sub-rate switch 110 and the full-rate switch 200 are implemented through channel grouping, and in particular, the switching from the sub-rate switch 110 to the full-rate switch 200 may be implemented. Can be.

In the sub-rate switch 110, four channels may be collected and switched through the full-rate switch 200. If four of the channels are not paired, one, two or three channels occupy the full-rate channel 200. Since the number of four paired channels is large, channel efficiency does not decrease. .

3 is a block diagram showing the configuration of a dual-rate AT switch according to the present invention.

Here, reference numeral 310 denotes a multiplexer for multiplexing the input ATM cell data, and reference numerals 321 to 324 denote first to fourth data memories for storing the multiplexed cell data in the multiplexer 310. , Reference numerals 331 to 334 store information of input channels corresponding to each output channel, and control the output of the stored data of the first to fourth data memories according to the information of the input channel, and generate a channel selection signal. First to fourth controllers, and reference numerals 341 to 344 denote one channel of the four channel data output from the first to fourth data memories in response to the channel selection signal output to the first to fourth controllers. A first to fourth channel selectors for selecting and outputting only data, and reference numeral 350 denotes multiplexing output through the first to fourth channel selectors 341 to 344. Demultiplexer for demultiplexing and outputting the channel data.

Referring to the operation of the dual-rate AT switch according to the present invention configured as described above are as follows.

First, the multiplexer 310 multiplexes ATM cell data input through a plurality of channels and stores the same in the first to fourth data memories 321 to 324.

Next, the first to fourth controllers 331 to 334 store the information of the input channel corresponding to each output channel, and since the channel number of the sub-rate stream is four times in the full-rate stream base, the input channel information In address, 2 bits are added. Using this information, a control signal for data output of the first to fourth data memories 321 to 324 is applied, and a channel selection signal is transmitted to the first to fourth channel selectors 341 to 344.

The first to fourth data memories 321 to 324 output the stored ATM cell data in response to data output control signals output from the first to fourth controllers 331 to 334, respectively.

The first to fourth channel selectors 341 to 344 may transmit one channel data among four data input through four channels according to a 2-bit selection signal output from the first to fourth controllers 331 to 334. Select only the input to the demultiplexer 350 of the rear stage. That is, the first to fourth channel selectors 341 to 344 serve to create four channels mixed in full-rate.

Next, the demultiplexer 350 demultiplexes and outputs the multiplexed channel data output through the first to fourth channel selectors 341 to 344.

According to the present invention described above, by implementing a dual-rate switching device using an ATM cell multiplexer / demultiplexer to improve the data transmission efficiency, different rates (Rate) The effect is to provide ease of expansion to the furnace.

Claims (1)

In the AT cell switching device, A multiplexer for multiplexing input ATM cell data; First to fourth data memories storing cell data multiplexed by the multiplexer; Information of an input channel corresponding to each output channel, the first to fourth controllers controlling the output of the stored data of the first to fourth data memories according to the input channel information, and generating a channel selection signal; ; First to fourth channel selectors for selecting and outputting only one channel data among the four channel data output from the first to fourth data memories in response to the channel selection signals output to the first to fourth controllers; And a demultiplexer configured to demultiplex and output the multiplexed channel data outputted through the first to fourth channel selectors.