KR100455444B1 - Method of manufacturing a semiconductor device - Google Patents

Abstract

The present invention relates to a method of fabricating a semiconductor device, wherein a thin etch stop layer is formed in a non-salicide region before formation of an insulating layer to prevent the phenomenon of the insulating film remaining on the semiconductor substrate during the insulating film etching process, and damage the semiconductor substrate during the etching of the insulating film. And a method of manufacturing a semiconductor device capable of preventing the phenomenon in which the device isolation film in the salicide region is reduced.

Description

Method of manufacturing a semiconductor device

TECHNICAL FIELD This invention relates to the manufacturing method of a semiconductor element. Specifically, It is related with the manufacturing method of the semiconductor element which can form stable silicide in the logic element of 0.09 micrometer or less tech.

Semiconductor devices are rapidly becoming highly integrated. In order to achieve such high integration, a large number of parts of a conventional device must be reduced. In addition, a process for lowering the diffusion junction layer depth is very important in a junction formation process in which impurity ions are implanted on a semiconductor substrate to form a source and a drain region. In addition, impurity ions are injected into the polysilicon used as the gate electrode during the ion implantation process to lower the specific resistance of the polysilicon.

Such improvement in conductivity in the active region must be accompanied by an increase in the degree of integration of the device for ohmic contact with the metal layer.

However, since the impurity ion implantation alone has a limitation in reducing the resistivity value, silicide, which is a compound of metal and silicon, is deposited by depositing high melting point metals such as Ta, Mo, W, Ti, and Co on the source and drain regions and the polysilicon gate. A method of forming silicide has been proposed.

When the silicide is formed in the source, gate and drain regions, a metal film is deposited on the entire surface including the source, gate and drain regions, and then heat-treated to a predetermined temperature to form silicide, and on the oxide films other than the source, gate and drain regions. A method of forming a self-aligned silicide (salicide), in which silicide remains only in the source, gate, and drain regions by selectively etching the remaining metal film without reaction, is widely used due to the advantage of reducing mask work.

As the self-aligned silicide process is applied to fabrication of the device, it is not applied to the entire substrate region, and only a portion of the specific region is patterned so that silicide is formed.

1A and 1B are cross-sectional views illustrating a problem of a conventional silicide process.

1A and 1B, the semiconductor substrate 10 includes a salicide region B in which the silicide layer 50 is to be formed by the self-aligned silicide process and a non-salicide region in which the self-aligned silicide process is not applicable. A) is defined. The regions may be separated through the device isolation layer 11. In the salicide region B, a transistor including a gate electrode 20 and a source / drain 30 is formed, and in the non-salicide region A, an insulating film 40 is patterned to form a silicide layer 50. Define the area. The self-aligned silicide process is applied to form the silicide layer 50a in the exposed region.

In this case, the salicide region B is formed using the self-aligned silicide process to form the silicide layer 50a on the gate electrode 20 and on the source / drain 30 without performing a mask or patterning process. On the other hand, the non-salicide region A is etched a part of the insulating film 40a through a patterning process. That is, the non-salicide region A may be wet etched after dry etching to prevent the silicon substrate from being damaged through the etching process, thereby removing a part of the insulating layer 40a. Due to the above-described etching characteristics, the insulating film 40a near the edge of the open semiconductor substrate 10 is not completely removed but remains (see enlarged portion of the non-salicide region in FIG. 1A; 40b).

In the above state, the edge of the semiconductor substrate 10 opened during cobalt deposition does not have cobalt directly positioned on the substrate. When the silicide phase transition occurs by the heat treatment process, cobalt ions on the insulating film 40b pass through the insulating film 40b to react with the silicon under the insulating film 40b to form the silicide film 50b or the insulating film ( 40b) prevents the silicide 50c film from forming. Therefore, the formed silicide films 50b and 50c are thin and the silicon substrate and silicide film interface are formed roughly and unstable, and the cobalt ions move to the place where cobalt reacts and the CoSi ₂ thickness becomes thick, resulting in deterioration of junction leakage or A problem arises in that the silicide film is not formed in some regions.

Accordingly, the present invention provides a method of manufacturing a semiconductor device that can prevent the phenomenon of the insulating film remaining on the semiconductor substrate during the etching process by forming a thin etching prevention film before forming the insulating film in the non-salicide region to solve the above problems. Its purpose is to.

1A and 1B are cross-sectional views illustrating a problem of a conventional silicide process.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 110: semiconductor substrate 11, 111: device isolation film

20, 120: gate electrode 30, 130: junction

40, 140 insulating film 50, 150 silicide film

112 gate oxide film 114 silicon film

116: oxide film 118: nitride film

132 and 142: photosensitive film pattern 144: metal film

146: capping film 200: etching prevention film

Providing a semiconductor substrate in which salicide regions and non-salicide regions are defined, forming a transistor including a gate electrode and a junction in the salicide region and the non-salicide region, and overall structure Sequentially forming an etch stop layer and an insulating layer on the substrate; and removing the insulating layer and the etch stop layer of the salicide region to expose the gate electrode and the junction of the salicide region, and the insulating layer of the non-salicide region. Patterning the etch stop layer to expose a portion of the semiconductor substrate of the non-salicide region; and exposing the gate electrode and the junction of the salicide region and the exposed semiconductor substrate of the non-salicide region. Forming a silicide film It provides a method for manufacturing a semiconductor device, characterized in that.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

2A to 2G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, an isolation layer 111 is formed on the semiconductor substrate 110 in which the non-salicide region A and the salicide region B are defined. The salicide region B refers to a region where a silicide film is formed by a self-aligned silicide process (sally side process) without a mask, and the non-salicide region A is a silicide layer formed locally only on a specific region through a mask process. Refers to an area. Alternatively, the salicide region B refers to a region where a logic element cell is formed, and the non-salicide region A refers to a region where an input / output circuit of the logic element is formed.

The gate electrode 120 is formed in the salicide region B. After the low concentration ion implantation is performed on the entire structure, spacers are formed on the sidewalls of the gate electrode 120. The same process is also applied to the non-salicide region b to form a junction with the gate electrode. In the present embodiment, only illustrated for convenience of description and characteristics of the cut surface.

Specifically, an STI structure trench (not shown) is formed by performing a shallow trench isolation (STI) process on the entire structure including the non-salicide region (A) and the salicide region (B). The device isolation film 111 for separation between devices is formed by buried using the HDP oxide film. Ion implantation may be performed before the device isolation layer 111 is formed or after the device isolation layer 111 is formed.

After the gate oxide film 112 and the polysilicon film 114 are sequentially deposited on the entire structure, a gate electrode is formed by performing a patterning process using a gate mask. Impurity ions may be implanted to impart conductivity to the polysilicon layer 114.

A low concentration ion implantation process is performed to form a low concentration ion implantation layer (not shown) for forming the junction portion 130 on the semiconductor substrate 110 at both edges of the gate electrode. An oxide film 116 and a nitride film 118 over the entire structure. At least one of the films is deposited and then the entire surface etching process is performed to form spacers on both sides of the gate electrode.

Referring to FIG. 2B, a high concentration of ion implantation is performed to form a junction portion of the LDD structure on the sidewall of the gate electrode 120. Specifically, a high concentration ion implantation process is performed to form a high concentration ion implantation layer (not shown) on the semiconductor substrate 110 at both edges of the gate electrode 120, thereby forming a junction (source / drain) 130. An ion implantation mask film may be formed to protect the lower element during the low concentration and high concentration ion implantation.

High concentration ion implantation is performed by P + or N + ion implantation and two patterning processes are performed. That is, after the photoresist is coated on the semiconductor substrate 110, a photolithography process using an ion implantation mask is performed to open a region to be implanted with P + ions and to shield a region to be implanted with N + ions. 132). P + ion implantation is performed by performing an ion implantation process using the first photosensitive film pattern 132 as an ion implantation mask. After removing the first photoresist layer pattern 132, a photoresist layer pattern (not shown) for N + ion implantation is formed to implant N + ions to form different types of junction regions.

The ion implantation process may be performed using various types of doses (P type ions, N type ions), and the ion implantation process may be performed in various ways. Make sure that you know it.

In this embodiment, the same process is applied to the non-salicide region A and the salicide region B to form a logic element (transistor) including a gate electrode and a junction. The present invention is not limited thereto, and transistors may be formed in respective regions by applying different processes.

2C to 2E, the etch stop layer 200 and the insulating layer 140 are sequentially formed on the entire structure. The patterning process is performed to remove the insulating layer 140 and the etch stop layer 200 of the salicide region B, and to pattern the insulating layer 140 and the etch stop layer 200 of the non-salicide region A.

Specifically, as the etch stop layer 200, a nitride film having a thickness of 50 kPa or less is formed. More preferably, a nitride film (Si ₃ N ₄ ) having a thickness of 10 to 45 Å is formed. The insulating film 140 is formed using various oxide film materials used in the manufacture of semiconductor devices. The insulating layer 140 refers to a material layer that serves to protect a region that should not be formed when the silicide layer is formed in the non-salicide region A through a subsequent process. The etch stop layer 200 has a high etch selectivity difference between the insulating layer 140 and the insulating layer 140 in order to prevent the remaining of the insulating layer 140 on the semiconductor substrate of the non-saliside region B or the damage of the substrate when the insulating layer 140 is patterned. It is made of a material film. When the nitride film is used as the etch stop layer 200, the SiH ₄ and 4NH ₃ mixed gas is deposited at a temperature of 700 to 900 ° C, or the 3SiCl ₂ H ₂ and 4NH ₃ mixed gas is deposited at a temperature of 700 to 800 ° C.

After the photoresist is coated on the insulating layer 140, a photolithography process using a mask for patterning the non-salicide region A is performed to open the salicide region B, and the non-salicide region A A second photosensitive film pattern 142 is formed to open a portion where the silicide film is to be formed.

The insulating layer 140 is etched by performing an etching process using the second photoresist layer pattern 142 as an etching mask. The etching process may be performed using etching conditions and methods in which the etch stop layer 200 may serve as a barrier layer and a stop layer, and completely remove the insulating layer 140 exposed by the second photoresist layer pattern 142. The etching process used in the semiconductor device can be applied. More preferably, the insulating film 140 is etched by dry etch, and then the insulating film 140 which is not removed from the dry etch is completely removed by a single wafer type wet etching method (FIG. See magnified area in 2d). In the single wafer type etching process, when a single wafer is placed on the stage, the stage is rotated, and the BOE solution is placed on the wafer to perform wet etching. In addition, when the wet etching is finished, the chemical solution on the wafer is removed by DIW. After that, the wafer is dried by the spin method and the wet etching of the wafer is completed. As a result, the semiconductor substrate may not be damaged during dry etching, and the residual insulating film 140 may be removed, and the phenomenon in which the field oxide film (device isolation layer) 111 in the salicide region is reduced during etching of the insulating film 140 may be prevented. .

After the insulating layer 140 is patterned by the method described above, the second photoresist layer pattern 142 used as an etching mask is removed. The second photoresist layer pattern 142 may be removed after etching the etch stop layer 200 in a subsequent process.

The exposed etch stop layer 200 is removed by performing an etching process using the patterned insulating layer 140 as an etch mask. As a result, the insulating layer 140 and the etch stop layer 200 in the salicide region B are completely removed, and the insulating layer 140 and the etch stop layer 200 are patterned in the non-salicide region A (enlarged in FIG. 2E). Area). The etching process may be performed under conditions that do not damage the semiconductor element including the semiconductor substrate 110 under the etch stop layer 200. That is, when the nitride film is used as the etch barrier 200, wet etching using phosphoric acid may be performed, but it may be sufficiently removed by adjusting various factors such as the concentration of the phosphoric acid aqueous solution and the time of wet etching. If you have knowledge of this is enough to know. That is, the etching process conditions for removing the nitride film having a thickness of 50 kHz is very diverse. As a result, it is possible to prevent residual phenomenon of the insulating film 200 and damage of the substrate, which have conventionally occurred in the non-salicide region A. FIG. For example, the nitride film is removed by performing wet etching at a temperature of 100 to 150 ° C. using an aqueous phosphate solution.

2F and 2G, the metal film 144 and the capping film 146 are sequentially formed along the step on the overall structure. The silicide layer 150 is formed on the exposed semiconductor substrate 110 of the non-salicide region A through an annealing process and an etching process, and the junction 130 and the gate electrode 120 of the salicide region B are formed. The silicide film 150 is formed on the film. In this case, the exposed semiconductor substrate of the non-salicide region A may be any one of a wafer including a gate electrode, a junction, and various types of semiconductor elements.

In detail, the non-salicide region A in which the etch stop layer 200 and the insulating layer 140 are patterned to expose the semiconductor substrate 110 where the silicide layer 150 is to be formed, the gate electrode 120 and the junction portion are exposed. The metal film 144 and the capping film 146 are sequentially formed on the salicide region A on which the step is formed. At this time, cobalt (Co) is used as the metal film 144 and Ti or TiN is used as the capping film 146. The lifting phenomenon of the metal film 144 and the capping film 146 does not appear (see the enlarged area of FIG. 2F).

The silicide layer 150 is formed by reacting the silicon component of the exposed portions of the non-salicide region A and the salicide region B with the metal component of the metal layer 144 by performing a first heat treatment process. The primary heat treatment process for forming the silicide film 150 is performed in RTP equipment, and CoSi phase is formed by performing for 30 to 60 seconds while maintaining the temperature of 500 to 550 ℃ in a nitrogen atmosphere. At this time, in the process of raising the internal temperature of the RTP equipment to 500 to 550 ℃ temperature after mounting the semiconductor substrate 110 as the RTP equipment, the temperature rise rate is set to 30 to 80 ℃ / sec to optimize the process conditions.

Since the silicide layer 150 is made of a silicide material having a small grain size, an increase in sheet resistance may be minimized, and the silicide layer 150 may be prevented from being broken or deteriorated in a subsequent heat treatment process.

After the capping layer 146 is removed, the remaining metal layer 144 is removed without reacting with the lower silicon component. That is, the capping film 146 and the unreacted metal film 144 may be prepared by using a SC-1 solution containing NH ₄ OH: H ₂ O ₂ : H ₂ O at about 0.2: 1: 10. After the first cleaning process for 10 to 15 minutes at a temperature of 5 to 5 at a temperature of 45 to 55 ℃ using an SC-2 solution in which HCl: H ₂ O ₂ : H ₂ O is mixed at about 1: 1: 5 The cleaning process is carried out for 10 minutes to remove.

Thereafter, the film quality of the silicide layer 150 is improved through the secondary heat treatment process. The secondary heat treatment process for improving the film quality of the silicide film 150 is carried out in the RTP equipment similar to the primary heat treatment process, it is carried out for 20 to 40 seconds while maintaining a temperature of 750 to 800 ℃ in a nitrogen atmosphere. Temperature increase rate is also set to 30 to 80 ℃ / sec like the primary heat treatment process to optimize the process conditions. As a result, the silicide layer 150 having the low sheet resistance and uniform thickness and preventing the electrical characteristics or film quality from being degraded by the subsequent thermal process is formed on the junction 130 of the salicide region B and the gate electrode 120. It is formed in a part of the non-salicide region (A). When the metal film 144 is used as cobalt, a cobalt silicide film is formed.

An interlayer insulating film (not shown) for forming bit line contacts (not shown) is formed, and then bit line contacts are formed. After that, a conventional semiconductor manufacturing process is applied to form various types of semiconductor elements (not shown).

As described above, the present invention can prevent the phenomenon of the insulating film remaining on the semiconductor substrate during the insulating film etching process by forming a thin etching prevention film in the non-salicide region before forming the insulating film.

In addition, the semiconductor substrate may be prevented from being damaged when the insulating layer is etched.

In addition, it is possible to prevent a phenomenon in which the isolation layer of the salicide region is reduced during the etching of the insulating layer.

Claims (4)

(a) providing a semiconductor substrate having defined salicide regions and non-salicide regions; (b) forming a transistor including a gate electrode and a junction in the salicide region and the non-salicide region; (c) sequentially forming an etch stop layer and an insulating layer on the entire structure; (d) removing the insulating layer and the etch stop layer of the salicide region to expose the gate electrode and the junction of the salicide region, and patterning the insulating layer and the etch stop layer of the non-salicide region to form the non-sally Exposing a portion of the semiconductor substrate in a side region; And (e) forming a silicide film on the exposed gate electrode and the junction of the salicide region and the exposed semiconductor substrate of the non-salicide region. The method of claim 1, wherein step (d) Performing a dry etching to etch the insulating film of the salicide region and to etch a portion of the insulating film of the non-salicide region; Performing a first wet etching process to completely etch the insulating layer which is not completely etched during the dry etching; And And removing the etch stop layer by performing a second wet etching process. The method of claim 1, wherein step (e) Sequentially forming a metal film and a capping film along the steps on the entire structure; Performing a first heat treatment process to form a silicide film on the gate electrode and the junction of the salicide region and to form a silicide film on the exposed semiconductor substrate of the non-salicide region; Performing an etching process to remove the remaining capping mix and the metal film; And And improving the film quality of the silicide film by performing a second heat treatment process. The method of claim 1, The insulating film is formed using an oxide film, the etch stop film is formed using a nitride film, the etch stop film is a semiconductor device manufacturing method, characterized in that to form a thickness of 10 to 40Å.