KR100454952B1 - Adaptive Channel Coding Method and Apparatus - Google Patents

Abstract

A coding apparatus of a communication system using a channel encoder in which convolutional codes are connected in parallel or in a serial structure, the apparatus comprising: a first component encoder for encoding input information bits and an input information bit according to a set rule; An interleaver composed of a memory and an index generator, a second component encoder for encoding the output of the interleaver, a first terminal device for terminating a frame of input and output information bits of the first component encoder and the second component encoder, A second end device, a tail bit storage device for storing and outputting tail bits used at the end of the frame, and a controller, a switch, and an information bit for controlling this process are punctured to adjust the code rate.

Description

Adaptive channel coding method and apparatus

The present invention relates to a channel encoding method and apparatus for a communication system, and more particularly, to an adaptive channel encoding method and apparatus for voice and data transmission.

A turbo encoder is a system that creates a parity symbol using two simple constituent encoders, which is composed of a frame of N information bits, and can be configured in parallel and serial structures. have. And the recursive systemic convolutional code of the turbo coder is used.

1 is a diagram illustrating a configuration of a turbo encoder having a conventional parallel structure, which is disclosed in US Pat. No. 5,446,747 invented by Berrou. The turbo encoder having the configuration as shown in FIG. 1 is connected to the interleaver 12 between the first component encoder 11 and the second component encoder 13. The interleaver 12 has the same size as the frame length N of the input information bits and reduces the correlation between the information bits by changing the order of the information bits input to the second component encoder 13. 2 is a diagram illustrating a structure of a turbo encoder in a conventional serial structure, in which an interleaver 12 is connected between a first component encoder 11 and a second component encoder 13.

The turbo coder having the above structure is used for a turbo code that has been used in space-space communication, and the constituent coders 11 and 13 are smaller in length than the convolutional code in which the constraint length K is K = 9, but the interleaver The memory used for 12 is very large. Therefore, the time delay during decoding is also very large.

The turbo decoder which decodes the output of the turbo encoder of the parallel structure as shown in FIG. 1 has the configuration as shown in FIG. 3 and is disclosed in US Patent No. 5,446,747 invented by Berrow. The turbo decoder which decodes the output of the turbo encoder of the serial structure as shown in Fig. 2 has the configuration as shown in Fig. 4 and is disclosed in a paper published by Benedetto. (IEEE Electronics Letters, June 1996, Vol. 13)

Referring to the operation of the turbo decoder of the parallel structure of FIG. 3, as shown in FIG. 3, by repeating the decoding using the iterative decoding algorithm on a frame-by-frame basis, an error rate is increased according to an increase in the number of repeated decoding. Rate: BER) has the advantage of gradually improving performance. In addition, the interleaver 323 distributes the uncorrected congestion error pattern in the first decoder 319 and then makes corrections in the second decoder 327 to improve the error correction capability.

The iterative decoding is decoding again by using the decoded symbols. When the iterative decoding is performed by using the decoded symbols and additional information derived with a specific rule, excellent performance can be obtained. Algorithms for iterative decoding include SOVA (Soft-Output Viterbi Algorithm) and MAP (Maximum A Posteriori Probability) algorithms, in which the decoded value has a soft-determined value. (SOVA: Proceedings of IEEE Vehicular Technology Conference, pp 941-944, May 1993, MAP: IEEE Transactions on Information Theory, pp 429-445, Vol. 42 No. 2, March 1996). The SOVA algorithm is modified to output a soft decision value in the Viterbi algorithm, thereby minimizing an error in a codeword. On the other hand, the MAP algorithm is an algorithm capable of minimizing symbol error, thereby obtaining a lower symbol error probability than the SOVA algorithm.

가 된다. 상기 터보 부호의 성능은 인터리버의 크기, 인터리버의 구조 및 반복 복호 횟수에 따라 성능이 결정된다.In FIG. 3, when the received parity symbol y _k is a value encoded by the first component encoder 11 of the parallel turbo encoder of FIG. 1, y _1k = y _k , y _2k = 0, and y _k is FIG. When the value is encoded by the second constituent encoder 13 of the parallel structure turbo encoder, y _1k = 0, y _2k = y _k . Z _{k + 1} is a soft decision value using an iterative decoding algorithm and is used as an input for the next iterative decoding. In the final decoding step, the hard decision value of Z _{k + 1} is finally desired.

Becomes The performance of the turbo code is determined according to the size of the interleaver, the structure of the interleaver and the number of iterative decoding.

As shown in FIG. 1, an interleaver 12 is provided inside the turbo encoder. The interleaver 12 performs encoding and decoding on a frame basis when encoding and decoding a turbo code. Therefore, as shown in FIG. 3, the frame size of the memory required for the first repeater 319 and the second repeater 327 is proportional to the product of the number of states of the constituent codes 11 and 13. Since the turbo code generally uses a very large frame, it is very difficult to apply to the transmission of voice and data. Increasing the number of states of the constituent codes of the turbo encoder to reduce the size of the interleaver reduces the memory size required for the interleaver, but increases the complexity of the first and second decoders of FIG.

When a concatenation error occurs in the decoder having the structure as shown in FIG. 3, the output of the first iteration decoder 319 has a correlation, and in the decoding process of the next step, the second iterative decoder 327 which is the second decoder is Correlated inputs prevent correct decoding. Therefore, there is an error in the entire block, which cannot be corrected in the next iterative decoding process. Therefore, in the code for performing the iterative decoding, the interleaver and the deinterleaver (12 of FIG. 1, 12 of FIG. 2, 323 of FIG. 3, 331 of FIG. 3, and 4 of FIG. 12, 13) of FIG. 4 is essential.

Therefore, the turbo code shows very good performance by using a random interleaver that makes the correlation very small. However, if the size of the frame is not large, even if the random interleaver is used, it is difficult to separate the error so that the collection error does not matter. Therefore, in the case of voice transmission or data transmission with low data rate, a frame size and a structured interleaver with a small number of states of the component code and minimum time delay should be used. Therefore, it is very difficult to transmit voice and multimedia data with the constrained length and interleaver of the component code used in the conventional turbo code. However, efforts to implement an encoder and a decoder of a communication system have been increasing by using the advantages of the turbo code.

In order to implement a turbo encoder that has similar or superior performance to that of the convolutional code used in the conventional communication system, but does not have high complexity, an interleaver having excellent performance while minimizing time delay and minimizing time delay should be used. In general, the larger the size of the interleaver 12 of FIG. 1 or 12 of FIG. 2, the better the performance. However, there is a limit in increasing the frame size in the turbo code. In this case, it is advantageous to use an interleaver that makes the turbo code the minimum Hamming distance of the turbo code from the point of view of the block code. In the case of small frames, this problem can be solved by using a structural interleaver.

Accordingly, an object of the present invention is to provide a turbo encoding method and apparatus capable of encoding voice and low data rate in a communication system.

Another object of the present invention is to provide a diagonal interleaver method capable of interleaving regardless of the size of a data frame input in a communication system.

Another object of the present invention is to provide a cyclic interleaver method capable of interleaving regardless of the size of a data frame input in a communication system.

It is still another object of the present invention to provide a parallel or serial turbo encoding method and apparatus using a diagonal interleaver capable of interleaving regardless of the size of a data frame input in a communication system.

Another object of the present invention is to provide a parallel encoding method or an apparatus for turbo encoding using a cyclic interleaver capable of interleaving regardless of the size of a data frame input in a communication system.

It is still another object of the present invention to provide a method and apparatus for transmitting a parity bit generated by tail bits and tail bits to a channel in an apparatus for encoding a voice and data signal using a turbo code.

It is still another object of the present invention to provide a method and apparatus for adjusting a data rate by puncturing data and parity information in an apparatus for encoding a voice and a data signal with a turbo code.

In order to achieve the above object, an encoding apparatus of a communication system according to an embodiment of the present invention includes at least two component encoders for encoding input bits and matrix information corresponding to a frame size of the input information. And diagonally interleaving the input information according to the matrix information of the frame and connecting the input information to at least one input terminal of the encoder.

In addition, the encoder of the communication system according to an embodiment of the present invention for achieving the above object comprises at least two encoders for encoding the information bits input, hop variable information corresponding to the size of the input data and the hop And a cyclic interleaver which cyclically interleaves the input information according to a variable and then connects the input terminal of at least one of the constituent encoders.

In addition, at least two component encoders for encoding the information bits inputted by the encoding apparatus of the communication system according to an embodiment of the present invention for achieving the above object, and after interleaving the input information of at least one of the encoders And an interleaver connected to an output terminal, and a tail bit generator connected to an input / output terminal of the component encoders and generating tail bits for terminating the component encoders at the end of frame data and inputting the tail bits to the corresponding component encoders, respectively.

In addition, according to an embodiment of the present invention for achieving the above object, an encoding apparatus of a communication system having a decoder using an iterative decoding algorithm interleaves input information and at least two component encoders for encoding input information bits. And an interleaver connected to an output terminal of at least one of the encoders, and a puncturer for puncturing the input information to adjust transmission rates of the input information and the parity symbol.

In addition, a turbo encoding apparatus according to an embodiment of the present invention for achieving the above object; A first component encoder for encoding the input information bits; An interleaver for interleaving the information bits according to a set rule to change the order of the information bits; A perforator capable of varying the transmission rate of the turbo encoder output; A second component encoder for encoding the output of the interleaver; A first switch and a second switch and a tail bit generator connected to input terminals of the first component encoder and the second component encoder; An all bit storage device and a third switch for transmitting tail bits of the tail bit generator to a transmission channel; A first tail bit generator configured to generate tail bits for terminating the first component encoder and input the tail bits to the first component encoder; A second tail bit generator which generates a tail bit for terminating the first component encoder and inputs the tail bit to the second component encoder; A memory device for storing data input to the interleaver and deinterleaver, a memory device for storing interleaved and deinterleaved data, and a controller for controlling the process. Characterized in that consisting of.

In the embodiment of the present invention, a configuration of a turbo encoder having a parallel chain circulation structure will be described as an example for convenience of description. 5 and 6 are diagrams illustrating a configuration of a turbo encoder according to an embodiment of the present invention. It is assumed that the encoders 410 and 420 use a component encoder, and the encoders 410 and 420 of FIG. 1 and FIG. Parity symbol Y _k is generated by encoding the received information bit d _k together with the constituent encoder. In addition, the diagonal interleaver 432 and the circular shifting interleaver 434 are interleavers according to the first and second embodiments of the present invention. It will be called.

5 and 6, the information bit d _k is input to the first component encoder 410 and simultaneously to the interleaver 430 so that the order of the information bits is changed and input to the second component encoder 420. The interleaver 430 uses an interleaver in which a minimum Hamming distance of a sequence (X _k , Y _k ) output after the input information bit d _k is encoded in the case of optimal interleaving is maximized. In addition, the frame size of data input to the channel encoder is not constant due to the addition of CRC bits and other control bits as well as data. If forcibly fixing the size of the input data frame, dummy bits should be added as much as the interleaver size. Since the dummy bits are not related to the improvement of the performance of the system, the fewer are better. Therefore, the interleaver 430 should perform well regardless of the parameter change related to the input data frame size.

FIG. 7 shows the configuration of the diagonal interleaver 432 and the cyclic interleaver 434 shown in FIGS. 5 and 6. The diagonal interleaver 432 and the cyclic interleaver 434 analyze the corresponding frame size when an information bit having a variable sized frame is input and perform an optimal interleaving operation according to the analysis result. In the embodiment of the present invention, the diagonal interleaver 432 and the cyclic interleaver 434 will be described as an example of implementing one interleaver. However, in the turbo encoder, when the interleaving method is fixedly used as a diagonal interleaving or a cyclic interleaving method, the interleaving method may be configured separately. The diagonal interleaver 432 and the cyclic interleaver 434 will be referred to as an interleaver 430.

Referring to FIG. 7, the register 511 receives and stores a frame size signal and an interleaver type signal output from a system controller (not shown). The diagonal interleaving table 513 is a table for storing values M and N of rows and columns which may have optimal diagonal interleaving characteristics according to the frame size of information bits when performing the diagonal interleaving function. That is, when diagonally interleaving information bits received with a variable frame size, M and N having an optimal diagonal interleaving effect are experimentally measured and stored in the diagonal interleaving table 513. The diagonal interleaving table 513 outputs M and N values corresponding to the frame size signal output from the register 511. The diagonal interleaving controller 517 inputs M and N values output from the diagonal interleaving table 513 and then generates a read address for interleaving and outputting information bits in a set diagonal interleaving scheme. The cyclic interleaving table 515 is a table for storing hop variable and step variable values p and STEP which may have optimal cyclic interleaving characteristics according to the frame size of the information bit when performing the cyclic interleaving function. That is, when cyclic interleaving information bits received with a variable frame size, p and STEP variables having an optimal cyclic interleaving effect are experimentally measured and stored in the cyclic interleaving table 515. The cyclic interleaving table 515 outputs p and STEP values corresponding to the frame size signal output from the register 511. The cyclic interleaving controller 519 inputs p and STEP values output from the cyclic interleaving table 515 and then generates a read address for interleaving and outputting information bits in a cyclic interleaving scheme. The multiplexer 521 inputs a read address output from the diagonal interleaving controller 517 and the cyclic interleaving controller 519, and selects an address of an interleaving scheme corresponding to the interleaver type signal output from the register 511 and outputs the read address to the read address. The memory 523 sequentially inputs the information bits, and interleaves the information bits stored by the read address output from the multiplexer 521. The memory 523 is set to a size capable of storing information bits having a maximum frame size from information bits that are variably input.

In the configuration of FIG. 7, the diagonal interleaver 432 may be implemented alone, and may include a register 511, a diagonal interleaving table 513, a diagonal interleaving controller 517, and a memory 523. In this case, the interleaver type signal is not used. In addition, when the cyclic interleaver 434 is implemented alone in the configuration of FIG. 7, the cyclic interleaver 434 may be configured as a register 511, a cyclic interleaving table 515, a cyclic interleaving controller 519, and a memory 523, and the interleaver type signal is not used here.

In the configuration of FIG. 7, the diagonal interleaving table 513 and the cyclic interleaving table 515 may be implemented using a ROM or a RAM, or may be implemented by combining logic elements. In addition, the diagonal interleaving controller 517 and the cyclic interleaving controller 519 may be implemented by combining logic elements, and may be implemented by using a digital signal processing function.

8 and 9, which will be described below, illustrate an implementation of the diagonal interleaving scheme, and FIGS. 10 and 11 illustrate an implementation of the cyclic interleaving scheme.

A first diagonal interleaving to a third diagonal interleaving operation will be described with reference to the configuration of the interleaver 430 as shown in FIG. 7.

8 is a flowchart illustrating an operation of first diagonal interleaving. Referring to FIG. 8, the first diagonal interleaving is a method of reading and writing data by viewing a sequence of input bits as an M * N matrix. Referring to the first diagonal interleaving, when the information bit d _K is input, the information is stored in the address old_addr [k] for sequentially storing the information bit input in step 611 in the memory 523, and the size (k) of the frame data is changed. Set it. Where k is a variable representing the size of input frame data. Thereafter, in step 613, the row and column variables (M * N) of the data frame for diagonal interleaving are determined. That is, in order to perform diagonal interleaving, the M and N values are set in the diagonal interleaving table with reference to the input frame data size variable k. In operation 615, the maximum common divisor of the M and N values is 1 [gcd (M, N) = 1]. In this case, when the greatest common divisor of M and N is 1, the address of the first diagonal interleaving is calculated in the same manner as in Equation 1 in operation 617.

[Equation 1]

As shown in Equation 1, the address of the output buffer is designated to interleave the input information bits stored in the input buffer and stored in the output buffer.

However, if the greatest common divisor of M and N is not 1 (gcd (M, N) ≠ 1) in step 615, the operation of the first diagonal interleaving is stopped and terminated in step 619.

An example of the first diagonal interleaving will be described. First, for example, when M = 6 and N = 5 stored in old_addr [k] of the input buffer, old_addr [k] = {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29}, the sequence stored in the output buffer new_addr [k] after the first diagonal interleaving is new_addr [k] = {25 21 17 13 9 0 26 22 18 14 5 1 27 23 19 10 6 2 28 24 15 11 7 3 29 20 16 12 8 4}.

When the above stored values are expressed in an M * N matrix, the data output after the first diagonal interleaving with the input data is shown in Table 1.

TABLE 1

However, the above first diagonal interleaving can be made only when the greatest common divisor (M, N) = 1. However, assuming the case of M = 6 and N = 6 where the greatest common divisor (M, N) ≠ 1, there is a disadvantage in that interleaving is not performed at all and the same data is obtained as shown in Table 2 below.

TABLE 2

The second diagonal interleaving method and the third diagonal interleaving method view a sequence of input information bits as an M * N matrix, and read and write data, but not only when the greatest common factor (M, N) = 1, but also the maximum common factor (M, Even if N) ≠ 1, interleaving is possible.

9 is a flowchart illustrating the operation of the second diagonal interleaving. Referring to FIG. 9, the second diagonal interleaving is a method of viewing an input bit sequence as an M * N matrix and reading and writing data, which can be applied to both the case where the greatest common divisor of M and N is 1 and not 1. Diagonal interleaving. Referring to the second diagonal interleaving, when the information bit d _K is input, in step 631, the information is stored in the address old_addr [k] of the input buffer and the size k of the frame data is set. Where k is a variable representing the size of input frame data. Thereafter, in step 633, the row and column variables (M * N) of the data frame for diagonal interleaving are determined. After setting M and N, in step 635, the address of the second diagonal interleaving is calculated in the same manner as in Equation 2 below. In Equation 2, M and N are variable information of columns and rows, j is a variable increasing from 1 to M, and i is a variable increasing from 1 to N.

[Equation 2]

As shown in Equation 2, the address of the output buffer is designated to interleave the input information bits stored in the input buffer and stored in the output buffer.

Using the second diagonal interleaving method, M = 6 and N = 5 having the greatest common divisor (M, N) = 1 are shown in Table 3 below.

TABLE 3

In addition, it can be seen that interleaving is performed properly with Table 4 below when M = 6 and N = 6 where the greatest common divisor (M, N) ≠ 1.

TABLE 4

Third, in the case of the third diagonal interleaving scheme, the diagonal interleaving controller 517 may be implemented as in Equation 3 below.

[Equation 3]

Using the diagonal interleaver 432, the input sequence is stored in a mapped memory address, and then data is read sequentially in rows or columns, or the input sequence is sequentially stored in memory in rows or columns, and then stored in the diagonal interleaving generator. Interleaving can be done by reading data one by one from an address.

The deinterleaving process may be performed in the reverse order of the method used in the interleaver.

FIG. 10 is a flowchart illustrating an operation of first cyclic interleaving of input information bits using the cyclic interleaver 434 as shown in FIG. 7. The first cyclic interleaving method according to an embodiment of the present invention is a method of viewing an input sequence as one or more circles and reading and writing data at regular intervals, and interleaving an input sequence having an arbitrary length.

Referring to the first cyclic interleaving operation with reference to FIG. 10, when the information bit d _K is input, in step 711, information is stored in the address old_addr [k] of the input buffer and the size (SIZE) of the frame data is set. In step 713, the P and STEP variables are set. Herein, the P variable is a hop interval variable and determines the performance of the cyclic interleaver. Therefore, the P variable is experimentally determined to have an optimal effect. In addition, the STEP variable is a variable that shifts to the left or right at the position hopping by the P variable. Here, the STEP variable is an integer. After calculating the p variable and the STEP variable as described above, it is checked in step 715 that the maximum common factor of the hop variable P and the STEP variable is 1 [gcd (P, SIZE = 1)]. In this case, when the greatest common factor of the P and SIZE variables is 1, the first cyclic interleaving address is calculated with Equation 4 below.

[Equation 4]

In Equation 4, the i variable is a variable representing the number of frame data sizes to be interleaved and varies from 0 to SIZE (address number). In addition, the SIZE is a circular size and is set equal to or smaller than the size of the entire data frame. p is any natural number that satisfies the greatest common divisor (SIZE, p) = 1. STEP is an integer and is the initial starting point.

Here, for example, a sequence having SIZE = 30 stored in the first input buffer old_addr [k] old_addr [k] = {0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29}, the sequence stored in the buffer new_addr [k] after the first cyclic interleaving with p = 11 and STEP = 0 is set to new_addr [k]

= {0 11 22 3 14 25 6 17 28 9 20 1 12 23 4 15 26 7 18 29 10 21 2 13 24 5 16 27 8 19}. When the above stored values are expressed in an M * N matrix, they are shown in Table 5 below.

TABLE 5

However, when using p = 6 having a maximum common divisor (SIZE, p) ≠ 1, the first cyclic interleaving as shown in FIG. 10 does not result in interleaving and an error of overwriting data at the same address occurs.

Herein, a sequence of SIZE = 30 stored in the sequential address old_addr [k] of the first memory is input, and assuming that p = 11 and STEP = 0, the first cyclic interleaving method as shown in FIG. The result of interleaving the input sequence is expressed as M * N matrix as shown in Table 6 below.

TABLE 6

의 행렬로 보고, 열로는 제1순환 인터리빙 방법을 사용하고 행으로는 블록 인터리빙 방법을 사용하는 방식이다.In order to compensate for the drawbacks of the first cyclic interleaving scheme as described above, a second cyclic interleaving scheme capable of interleaving even when the maximum common divisor (SIZE, p) ≠ 1 is illustrated in FIG. 11. The second cyclic interleaving scheme illustrated in FIG. 11 uses an input sequence.

In the matrix, the first cycle interleaving method is used as a column, and the block interleaving method is used as a row.

Secondly, FIG. 11 is a flowchart illustrating the operation of the second cyclic interleaving, and is a cyclic interleaving scheme applicable to both the case where the maximum common factor of the P and SIZE variables is 1 and not 1. Referring to the second cyclic interleaving operation, when the information bit _dk is input, in step 721, the information is stored in the sequential address old_addr [k] of the memory and the size SIZE of the frame data is set. The SIZE is a variable representing the size of input data to be interleaved. In step 723, hop variables P and STEP variables for cyclic interleaving are determined. After setting the P and STEP variables, in step 725, the address of the second cyclic interleaving is calculated in the same manner as in Equation 5 below. In Equation 5, i and k are variables representing numbers ranging from 0 to SIZE. j is an address variable and j is a number from 0 to d. P represents a hop variable for performing cyclic interleaving. STEP is a variable for shifting left and right by the STEP variable at the position determined by the hop variable P.

[Equation 5]

In Equation 5, (P * i + STEP) represents a cyclic interleaving operation, and j represents a block interleaving operation. Where SIZE is the size of the data frame to be interleaved, p is any natural number, and STEP is an integer.

Here, the second cyclic interleaving result of SIZE = 30 and p = 11 is represented by an M * N matrix, as shown in Table 7 below.

TABLE 7

The results of Table 7 are the same as the results of the first cyclic interleaving. However, the case of p = 15 with the greatest common divisor (SIZE, p) ≠ 1 is as follows.

TABLE 8

Using the above cyclic interleaving generator, store the input sequence in the mapped memory address, and then read the data sequentially in rows or columns, or sequentially store the input sequence in memory in rows or columns, and then address the cyclic interleaving generator. Interleaving can be done by reading data one by one.

The deinterleaving operation may be performed in the reverse order of the method used in the interleaver.

Fig. 12 is a diagram showing the performance of the cyclic interleaver used in the embodiment of the present invention with respect to the parallel chain structure, with the constraint length K = 3 of the configuration code, the input frame size is 104 bits, the number of repetitive decoding times, and the BPSK It shows the BER (Bit Error Rate) characteristics of the simulation results in the modulation method, AWGN (Additive White Gaussian Noise) environment. Compared with the simulation results of generally used block interleaver and random interleaver. As shown in FIG. 12, the Eb / No of the cyclic interleaver is about 3 dB at 10 ⁻⁵ BER and the block interleaver is 3.4 dB. Therefore, the cyclic interleaver is about 0.4 than the block interleaver at 10 ⁻⁵ BER. It can be seen that the performance is improved by about dB.

13 shows the configuration of a specific embodiment of a turbo encoder according to an embodiment of the present invention.

Referring to FIG. 13, the first component encoder 410 encodes and outputs an input information bit, and illustrates a case in which a constraint length is k = 3. The interleaver 430 interleaves the information bits according to a set rule to change the order of the information bits. 7 may be configured as shown in FIG. 7, and in this case, the first to third diagonal interleaving schemes or the first to second cyclic interleaving schemes may be implemented. The second component encoder 420 encodes and outputs the output of the interleaver 430, and exemplifies a case where the constraint length is k = 3.

The first tail bit generator 450 may include a first switch 455 connected to an input terminal of the first component encoder 410, an exclusive oragate 451 for exclusively ORing the outputs of the memory elements 412 and 413 of the first component encoder 410; The bit generator 453 initializes the memory of the first component encoder 410 and generates a frame termination signal to be applied to the first switch 455 according to the output of the exclusion unit oragate 451. At the end of the frame, the first tail bit generator 450 is connected to the first component encoder 410 to initialize the memory elements of the first component encoder 410 and simultaneously generate a frame termination signal. The second tail bit generator 460 includes: a second switch 465 connected to an input terminal of the first component encoder 420, an exclusive ora gate 461 exclusively ORing the outputs of the memory elements 422 and 423 of the first component encoder 420; The bit generator 463 is configured to initialize the memory of the first component encoder 420 and generate a frame termination signal to be applied to the second switch 465 according to the output of the exclusive unit or gate 461. When the frame ends, the first tail bit generator 460 is connected to the second component encoder 420 to initialize the memory elements of the second component encoder 420 and simultaneously generates a frame termination signal.

The first puncturer 470 punctures the information bits. The second puncturer 480 inputs the outputs of the first component encoder 410 and the second component encoder 420 and punctures the encoded data. The first puncturer 470 and the second puncturer 480 perform a function for adjusting the data transmission rate. The multiplexer 491 inputs the outputs of the bit generators 453 and 463 and multiplexes the two outputs. The third switch 493 switches the tail bits multiplexed and output from the multiplexer 491 to the transmission channel at the end of the frame.

Accordingly, the first tail bit generator 450 generates tail bits for terminating the first component encoder 410, and the second tail bit generator 460 generates tail bits for terminating the second component encoder 420. In addition, the first puncher 470 and the second puncher 480 performs a function for adjusting and outputting the transmission rate in a standardized state.

Referring to FIG. 3, which assumes a configuration of a parallel turbo encoder, the turbo code uses tail bits to terminate component encoders 410 and 420. At this time, since the configuration code of the turbo code is an organization code, the continuous input of " 0 " like the unstructured convolutional code does not initialize the memories 412-413 and 422-423 of the configuration coders 410 and 420. However, the constituent encoders 410 and 420 continue to make the memory closest to the input to "0" by inputting a value equal to the sum of the feedback values to the input using the tail bit generator. Therefore, the turbo encoder requires as many tail bits as the number of memories of each component code. In FIG. 13, the switch 455 connected to the input terminal of the first component encoder 410 and the switch 465 connected to the input terminal of the second component encoder 420 are switched at the time of generating the tail bit. Thereafter, the parity bits of the tail bits output to the first component encoder 410 and the second component encoder 420 are output to the second puncturer 480, and the tail bits generated by the tail bit generator are switched by the third switch 493. Outputted with information bit Xk.

In order to reduce the complexity of the hardware production, it is good to make the data rate a power of two. However, in the case of a data rate such as 384 kbps, using a turbo code with a code rate of 1/2 cannot make the data rate an exponential power of two. Therefore, in such a case, it is possible to use a turbo code having a code rate of 3/8, which is formed by punching a turbo code having a code rate of 1/2. Especially for the 144kbps data rate, the turbo code with 1/2 code rate is punctured to make the code rate 9/16. Here, Tables 9 and 10 show examples of 9/16 perforation matrices.

TABLE 9

TABLE 10

Applied to the <Table 9> and <Table 10> In the information bits are applied to and corresponding to an input information bit d _K first puncturer 470, RSC1 second perforator as parity bits output from the first constituent encoder 410 480 do. In this case, Table 9 shows an example of puncturing the parity bits output from the component encoders 410 and 420. In this case, there are several places where "0" appears continuously in the portion corresponding to the parity bits. That is, when the parity bit is punctured to match the transmission rate, there is a place where " 0 " appears continuously in the part corresponding to the parity bit as in the underlined part of Table 9. However, in the embodiment of the present invention, since the configuration encoders 410 and 420 have only two memories, a fatal error may occur if two or more parity bits are not transmitted consecutively. Therefore, in the embodiment of the present invention, the information bits are punctured as shown in Table 10. Table 10 is the same 9/16 puncturing matrix as Table 9, but does not transmit two or more parity bits in succession.

As described above, by reducing the size of the interleaver existing in the turbo encoder according to the embodiment of the present invention and presenting an interleaver having excellent performance in the turbo code, it is not applicable to voice and data transmission of a communication system due to the limitation of time delay. Turbo codes can be used for voice and data transmission. In addition, by using an interleaver with excellent performance, the complexity of the decoder can be reduced by reducing the number of states of the constituent encoder of the turbo encoder. In addition, as described in the embodiment of the present invention, the input information may be punctured to provide various code rates.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the configuration of a conventional parallel chain cyclic structural coder.

Fig. 2 is a diagram showing the configuration of a conventional serial chain cyclic structural coder.

3 is a diagram showing the configuration of a conventional parallel chain cyclic structural decoder.

4 is a diagram showing the configuration of a conventional serial chain cyclic structural decoder.

5 is a diagram showing a chain circular structural encoder according to a first embodiment of the present invention.

Fig. 6 is a diagram showing a chain circular structural encoder according to a second embodiment of the present invention.

7 is a diagram showing the structure of a diagonal interleaver and a cyclic interleaver in a turbo encoder according to a first embodiment of the present invention.

8 is a flowchart illustrating a first diagonal interleaving operation process according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG.

FIG. 9 is a flowchart illustrating a second diagonal interleaving operation process according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG. 7.

FIG. 10 is a flowchart illustrating a first cyclic interleaving operation process according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG.

FIG. 11 is a flowchart illustrating a second cyclic interleaving operation process according to an embodiment of the present invention in the structure of an interleaver having the configuration as shown in FIG.

12 illustrates characteristics of a turbo encoder using a random interleaving method and a block interleaving method and a turbo encoder using a cyclic interleaving method according to a second embodiment of the present invention.

13 is a diagram illustrating a configuration for explaining tail bit generation and puncturing operations in a turbo encoder according to an embodiment of the present invention.

Claims (9)

In the channel encoding method in a turbo encoder having a first component encoder and a second component encoder, Receiving the variable input information bits and outputting them to the information bit string; Generating a first parity bit string by inputting the variable input information bits to the first component encoder; Interleaving the input information bits; Generating a second parity bit string by inputting the interleaved input information bits to the second component encoder; Inputting an output of each of the first and second constituent encoders, and generating tail bits for each of the first and second constituent encoders by the input, Wherein the internal memories constituting each of the first and second constituent encoders are initialized by the tail bits. In the turbo encoding device, A receiving port for receiving variable input information bits; An output port for outputting the variable input information bits to an information bit string; A first component coder having a predetermined number of delay memories, the first component coder encoding the variable input information bits to generate a first parity bit string; An interleaver for interleaving the variable input information bits; A second component coder having a predetermined number of delay memories, the second component coder encoding the interleaved variable input information bits to generate a second parity bit string; A perforator for perforating the information bit stream and a portion of the first and second parity bit streams to adjust a data rate; A tail bit generator for inputting an output of each of said first and second constituent encoders and generating tail bits for each of said first and second constituent encoders by said input, Wherein the number of tail bits is equal to the number of delay memories, delay memories constituting the first and second constituent encoders are initialized by the tail bits, and the tail bits are framed when the delay memories are initialized. And output through the output port as a termination signal. A turbo encoder for encoding variable input information bits and outputting an information bit string and a first and second parity bit strings, A first component encoder for encoding the variable input information bits to generate a first parity bit string; An interleaver for interleaving the variable input information bits; A second component encoder for encoding the interleaved input information bits to generate a second parity bit string; A first tail bit generator for inputting an output of the first constituent encoder and generating first tail bits equal to feed-back values of the first constituent encoder, and an output of the second constituent encoder A second tail bit generator configured to generate second tail bits equal to feed-back values of the second constituent encoder by the input; A first switch which blocks input of the input information bits at the end of a frame and switches the first tail bits to be input to the first constituent encoder; And a second switch for blocking input of the interleaved input information bits at the end of the frame and switching the second tail bits to be input to the second constituent encoder. Here, the first memories constituting the first constituent encoder are initialized by the first tail bits of the number corresponding to the number of the first constituents, and the second memories constituting the second constituent encoder are the second memory. Initialized by the second tail bits in a number that matches the number of memories, The first and second tail bits are encoded into the first and second parity bit strings by the first and second component encoders, and the first and second tail bits are output as information bit strings. The device. 4. The apparatus of claim 3, further comprising a puncturer for puncturing one of the first parity bit string and the second parity bit string with respect to the parity bit string. 4. The apparatus of claim 3, further comprising a multiplexer for multiplexing the first tail bits and the second tail bits. A channel encoding method for encoding variable input information bits in a channel encoder having a first component encoder and a second component encoder and outputting the information bits to the information bit stream and the first and second parity bit streams, Generating the first parity bit stream by encoding the variable input information bits; Interleaving the variable input information bits; Generating the second parity bit stream by encoding the interleaved variable input information bits; Inputting an output of the first component encoder and generating first tail bits by the input; Inputting an output of the second constituent encoder and generating second tail bits by the input; Switching the input of the first component encoder from the variable input information bits to the first tail bits at the end of the frame, and the input of the second component encoder to the second tail bit in the interleaved variable input information bits The process of switching to Here, the first memories constituting the first constituent encoder are initialized by the first tail bits of the number corresponding to the number of the first constituents, and the second memories constituting the second constituent encoder are the second memory. Initialized by the second tail bits in a number that matches the number of memories, The first and second tail bits are encoded into the first and second parity bit strings by the first and second component encoders, and the first and second tail bits are output into the information bit string. Said method. 2. The method of claim 1, further comprising adjusting a data rate by puncturing the information bit stream and a portion of the first and second parity bit streams. The method of claim 1, wherein the number of tail bits coincides with the number of internal memories. The method as claimed in claim 1, wherein the tail bits are output to the information bit stream as a frame termination signal at the end of a frame.

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