KR100453182B1 - Method of forming a metal line in semiconductor device - Google Patents
Method of forming a metal line in semiconductor device Download PDFInfo
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- KR100453182B1 KR100453182B1 KR10-2001-0086864A KR20010086864A KR100453182B1 KR 100453182 B1 KR100453182 B1 KR 100453182B1 KR 20010086864 A KR20010086864 A KR 20010086864A KR 100453182 B1 KR100453182 B1 KR 100453182B1
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Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 하부 금속 배선과 상부 금속 배선을 전기적으로 접속시키기 위한 트렌치를 형성한 후 전처리 세정공정을 스킵(Skip)한 상태에서 상기 트렌치 내부면에 PVD(Physical Vapor Deposition) 방식으로 장벽 금속층을 증착한 후 아르곤 가스와 RF 바이어스를 인가하여 상기 트렌치 저면에 형성된 장벽 금속층 및 그 하부에 존재하는 구리 산화막을 제거함으로써 하부 금속 배선과 상부 금속 배선 간의 콘택저항을 감소시킴과 동시에 전처리 세정공정시 발생하는 구리 오염을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device. After depositing the barrier metal layer by the physical vapor deposition method, argon gas and RF bias are applied to remove the barrier metal layer formed on the bottom of the trench and the copper oxide film under the trench, thereby reducing the contact resistance between the lower metal wiring and the upper metal wiring. The present invention provides a method of forming a metal wiring of a semiconductor device capable of preventing copper contamination generated during a pretreatment cleaning process.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 구리 금속을 이용한 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and to a method for forming metal wirings in semiconductor devices using copper metal.
반도체 소자의 집적도가 증가함에 따라 전기적 특성이 우수한 알루미늄(Al) 또는 구리(Cu)를 이용한 금속배선 형성 방법에 대한 연구가 활발히 진행되고 있는 추세이다.As the degree of integration of semiconductor devices increases, researches on a method of forming metal wirings using aluminum (Al) or copper (Cu) having excellent electrical characteristics have been actively conducted.
알루미늄은 층간 절연막(Inter Layer Dielectric; ILD)으로 사용되는 SiO2로의 확산이 전혀 일어나지 않기 때문에 층간 절연막의 측벽(Side Wall)에 형성되는 장벽 금속층(Barrier Metal) 특성에 전혀 영향을 미치지 않는다. 그러나, 구리는 그 특성상 SiO2로의 확산이 잘 일어나고, 이 확산에 의해 층간 절연막을 통과해 인접한 소자로 까지 이동하게 된다. 이와 같이, 층간 절연막을 통과해 인접한 소자로 이동한 구리는 실리콘(Si)내 딥 레벨 도펀트(Deep Level Dopant)로 작용하여 실리콘의 금지대(Forbidden Band) 내에 여러 개의 억셉터(Acceptor)와 도너(Donor) 레벨을 형성시킨다. 이들 딥 레벨이 재결합 생성(Generation-Recombination)의 소오스(Source)로 작용함에 따라 소자 간의 누설 전류(Leakage Current)를 유발시켜 소정 소자를 파괴시키게 된다. 따라서, 구리를 금속 배선 공정에 사용하기 위해서는 이종 금속과 접촉하는 저면은 물론이고 측벽의 층간 절연막 재료에 대한 장벽 금속층이 필요하다.Aluminum does not affect the barrier metal layer (Barrier Metal) formed on the side wall (Side Wall) of the interlayer insulating film because no diffusion into SiO 2 used as an interlayer dielectric (ILD). However, copper is easily diffused into SiO 2 due to its characteristics, and the copper moves through the interlayer insulating film to the adjacent device. As such, the copper that has passed through the interlayer insulating film to the adjacent device acts as a deep level dopant in the silicon (Si) to allow several acceptors and donors in the silicon's Forbidden Band. Donor) form a level. As these deep levels act as a source of generation-recombination, leakage currents between devices cause destruction of certain devices. Thus, the use of copper in metal wiring processes requires a barrier metal layer for the interlayer insulating material of the sidewalls as well as the bottom contacting the dissimilar metal.
상기와 같은 문제를 해결하기 위해 최근에는 층간 절연막을 패터닝하여 트랜치 또는 비아홀을 형성한 후 트랜치 또는 비아홀을 통해 노출되는 하부 금속 배선층 상부 표면에 형성된 구리 산화막을 제거하기 위해 아르곤 스퍼터링(Ar Sputtering)과 같은 물리적인 방식으로 전처리 세정 공정을 실시한다. 이어서, 인 시튜(In-Situ)로 장벽 금속층 및 구리를 증착하여 하부 금속 배선층과 상부 금속 배선층을 전기적으로 접속시키고 있다. 그러나, 아르곤 스퍼터링 공정시 리스퍼터(Resputter)된 구리 원자가 패터닝된 층간 절연막의 측벽에 재증착(Redeposition)되어 층간 절연막의 특성을 열화시켜 소자의 신뢰성을 감소시키는 문제가 발생한다.In order to solve the above problem, in recent years, an interlayer insulating film is patterned to form trenches or via holes, and then, such as ar sputtering, to remove a copper oxide film formed on the upper surface of the lower metal wiring layer exposed through the trenches or via holes. The pretreatment cleaning process is carried out in a physical manner. Next, a barrier metal layer and copper are deposited in-situ to electrically connect the lower metal wiring layer and the upper metal wiring layer. However, during the argon sputtering process, the resputtered copper atoms are redeposited on the sidewalls of the patterned interlayer insulating layer to deteriorate the characteristics of the interlayer insulating layer, thereby reducing the reliability of the device.
따라서, 본 발명은 상기 문제를 해결하기 위해 안출된 것으로, 하부 금속 배선과 상부 금속 배선을 전기적으로 접속시키기 위한 트렌치를 형성한 후 전처리 세정공정을 스킵(Skip)한 상태에서 상기 트렌치 내부면에 PVD(Physical Vapor Deposition) 방식으로 장벽 금속층을 증착한 후 동일 챔버에 아르곤 가스와 RF 바이어스를 인가한 PVD 방식의 식각공정을 수행하여, 상기 트렌치 저면에 형성된 장벽 금속층 및 그 하부에 존재하는 구리 산화막을 제거함으로써 하부 금속 배선과 상부 금속 배선 간의 콘택저항을 감소시킴과 동시에 전처리 세정공정시 발생하는 구리 오염을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problem, PVD is formed on the inner surface of the trench in the state in which the pretreatment cleaning process is skipped after forming a trench for electrically connecting the lower metal wiring and the upper metal wiring. (Physical Vapor Deposition) method of depositing the barrier metal layer and then argon gas and RF bias applied to the same chamber to perform a PVD etching process, to remove the barrier metal layer formed on the trench bottom and the copper oxide film present below the trench. Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of reducing contact resistance between the lower metal wiring and the upper metal wiring and at the same time preventing copper contamination generated during the pretreatment cleaning process.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 구리 금속 배선 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도.1A to 1E are cross-sectional views of a semiconductor device for explaining a method of forming a copper metal wire in a semiconductor device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10 : 반도체 기판 12 : 제 1 층간 절연막10 semiconductor substrate 12 first interlayer insulating film
14 : 하부 금속 배선 16 : 식각 베리어층14 lower metal wiring 16 etching barrier layer
18 : 제 2 층간 절연막 20 : 트렌치18: second interlayer insulating film 20: trench
22 : 구리 산화막 24 : 장벽 금속층22 copper oxide film 24 barrier metal layer
26 : 시드 금속층 38 : 상부 금속 배선26: seed metal layer 38: upper metal wiring
상술한 목적을 달성하기 위해 하부 금속 배선등의 소정의 구조가 형성된 반도체 기판 상부에 층간 절연막을 형성하는 단계; 듀얼 다마신 공정을 실시하여 상기 하부 도전층의 소정 부위가 노출되도록 트랜치를 형성는 단계; 상기 트랜치를 포함한 전체 구조 상부에 장벽 금속층을 형성한 후 상기 트랜치의 하부면에 형성된 상기 장벽 금속층을 제거하기 식각공정을 실시하는 단계; 및 상기 트랜치를 매립하도록 상부 금속 배선을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.Forming an interlayer insulating film on the semiconductor substrate on which a predetermined structure such as a lower metal wiring is formed to achieve the above object; Performing a dual damascene process to form a trench to expose a predetermined portion of the lower conductive layer; Performing an etching process to form the barrier metal layer on the entire structure including the trench and to remove the barrier metal layer formed on the lower surface of the trench; And forming an upper metal line to fill the trench.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e는 본 발명의 실시예에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 도시한 반도체 소자의 단면도이다.1A to 1E are cross-sectional views of a semiconductor device for explaining a method for forming metal wirings of a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 소정의 구조가 형성된 반도체 기판(10) 상에 제 1 층간 절연막(12)을 형성한 후 포토리소그래피(Photolithography) 공정 및 사진 공정을 실시하여 반도체 기판(10)의 소정 부위가 노출되도록 콘택홀(도시하지 않음)을 형성한다.Referring to FIG. 1A, after forming a first interlayer insulating film 12 on a semiconductor substrate 10 having a predetermined structure, a photolithography process and a photo process are performed to form a predetermined portion of the semiconductor substrate 10. Contact holes (not shown) are formed to be exposed.
이어서, 콘택홀을 매립하도록 구리 금속으로 하부 금속 배선(14)을 형성하고, 전체 구조 상부에 식각 베리어층(16)과 제 2 층간 절연막(18)을 순차적으로 형성한 후 싱글(Single) 또는 듀얼 다마신 방식(Dual Damascene)을 이용하여 하부 금속 배선(14)의 소정 부위가 노출되도록 트렌치(또는, 비아홀)(20)을 형성한다. 이때, 노출되는 하부 금속 배선(14) 상부 표면에는 소정의 구리 산화막(22)이 형성된다.Subsequently, the lower metal interconnection 14 is formed of copper metal to fill the contact hole, and the etch barrier layer 16 and the second interlayer insulating layer 18 are sequentially formed on the entire structure, and then single or dual A trench (or via hole) 20 is formed to expose a predetermined portion of the lower metal line 14 by using a damascene method. At this time, a predetermined copper oxide film 22 is formed on the exposed upper surface of the lower metal wiring 14.
도 1b를 참조하면, 하부 금속 배선(14) 상부 표면에 형성된 구리 산화막(22)을 제거하기 위한 소정의 전처리 세정공정을 실시하지 않고, 트렌치(20)를 포함한 전체 구조 상부에 PVD(Physical Vapor Deposition) 방식으로 Ta, TaN, TaC, WN, TiN, TiW, TiSiN, WBN 또는 WC를 사용하여 단층 또는 적층 구조의 장벽 금속층(24)을 50 내지 500Å의 두께로 형성한다.Referring to FIG. 1B, a physical vapor deposition (PVD) is disposed on an entire structure including a trench 20 without performing a pretreatment cleaning process for removing a copper oxide film 22 formed on an upper surface of a lower metal wiring 14. By using Ta, TaN, TaC, WN, TiN, TiW, TiSiN, WBN or WC), a barrier metal layer 24 having a single layer or a laminated structure is formed to a thickness of 50 to 500 kPa.
도 1c를 참조하면, 상기 장벽 금속층(24)이 형성된 결과물에 PVD 방식을 이용한 식각공정을 실시하여 트렌치(20)의 하부면에 형성된 장벽 금속층(24) 및 구리 산화막(22)을 제거한다. 이때, 식각공정은 PVD 모듈(Module)에서 챔버의 압력을 50mTorr 내지 5Torr로 유지하는 상태에서 아르곤 가스를 주입하는 동시에 RF 바이어스(Radio Frequence Bias)를 50 내지 1000W 정도로 인가하여 5 내지 100sec 동안 실시한다.Referring to FIG. 1C, the barrier metal layer 24 and the copper oxide layer 22 formed on the lower surface of the trench 20 are removed by performing an etching process using the PVD method on the resultant product on which the barrier metal layer 24 is formed. At this time, the etching process is performed for 5 to 100 sec by injecting argon gas while maintaining the pressure of the chamber at 50 mTorr to 5 Torr in the PVD module and applying RF bias (Radio Frequence Bias) to about 50 to 1000 W.
도 1d를 참조하면, 트렌치(20)의 하부면에 형성된 장벽 금속층(24) 및 구리 산화막(22)을 제거하기 위한 식각공정 후 인-시튜로 PVD 방식을 이용하여 트렌치(20)를 포함한 전체 구조 상부에 구리 금속으로 시드 금속층(26)을 50 내지 1500Å의 두께로 형성한다.Referring to FIG. 1D, after the etching process for removing the barrier metal layer 24 and the copper oxide layer 22 formed on the lower surface of the trench 20, the entire structure including the trench 20 using an in-situ PVD method is used. The seed metal layer 26 is formed in the upper part with the thickness of 50-1500 micrometers with copper metal.
도 1e를 참조하면, 전체 구조 상부에 전기 도금, 무전해 도금 방식, PVD 또는 CVD 방식을 이용하여 구리 금속을 증착한 후 CMP(Chemical Mechanical Polishing) 공정을 이용한 평탄화 공정을 실시하여 트렌치(20)을 매립하도록 상부 금속 배선(28)을 형성한다. 이어서, 상부 금속 배선(28)에 대해 150 내지 450℃의온도에서 열처리 공정을 실시한다.Referring to FIG. 1E, the trench 20 is formed by depositing a copper metal on the entire structure by electroplating, electroless plating, PVD, or CVD, followed by a planarization process using a chemical mechanical polishing (CMP) process. The upper metal wiring 28 is formed to be buried. Subsequently, a heat treatment process is performed on the upper metal wiring 28 at a temperature of 150 to 450 캜.
본 발명은 하부 금속 배선과 상부 금속 배선을 전기적으로 접속시키기 위한 트렌치를 형성한 후 전처리 세정공정을 스킵(Skip)한 상태에서 상기 트렌치 내부면에 PVD(Physical Vapor Deposition) 방식으로 장벽 금속층을 증착한 후 동일챔버에 아르곤 가스와 RF 바이어스를 인가한 PVD 방식의 식각공정을 수행하여 상기 트렌치 저면에 형성된 장벽 금속층 및 그 하부에 존재하는 구리 산화막을 제거함으로써 하부 금속 배선과 상부 금속 배선 간의 콘택저항을 감소시킴과 동시에 전처리 세정공정시 발생하는 구리 오염을 방지할 수 있다. 이로써, 소자의 신뢰도를 향상시킬 수 있다.According to the present invention, a barrier metal layer is deposited on the inner surface of the trench by PVD (Physical Vapor Deposition) method while forming a trench for electrically connecting the lower metal wiring and the upper metal wiring and skipping the pretreatment cleaning process. Afterwards, the contact resistance between the lower metal wiring and the upper metal wiring is reduced by performing a PVD etching process in which argon gas and RF bias are applied to the same chamber to remove the barrier metal layer formed on the bottom of the trench and the copper oxide film under the trench. At the same time, copper contamination generated during the pretreatment cleaning process can be prevented. Thereby, the reliability of an element can be improved.
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US1742A (en) * | 1840-08-25 | Camphene-lamp | ||
| US20010001742A1 (en) * | 1998-10-02 | 2001-05-24 | Yimin Huang | Method of fabricating a dual -damascene structure in an integrated cirtcuit with multilevel-interconnect strcture |
| KR20000054970A (en) * | 1999-02-02 | 2000-09-05 | 정수홍 | Metal interconnection layer having barrier metal layer and fabricating method therefor |
| US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
| US20020106895A1 (en) * | 2001-02-08 | 2002-08-08 | Macronix International Co., Ltd. | Method for forming copper interconnect and enhancing electromigration resistance |
| US20020123219A1 (en) * | 2001-03-02 | 2002-09-05 | Jerald Laverty | Method of forming a via of a dual damascene with low resistance |
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| Publication number | Publication date |
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| KR20030056599A (en) | 2003-07-04 |
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