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KR100451151B1 - Method of plating back surface of wafer for increasing productivity by processing clearly dicing face thereof - Google Patents

Method of plating back surface of wafer for increasing productivity by processing clearly dicing face thereof Download PDF

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Publication number
KR100451151B1
KR100451151B1 KR1019970070085A KR19970070085A KR100451151B1 KR 100451151 B1 KR100451151 B1 KR 100451151B1 KR 1019970070085 A KR1019970070085 A KR 1019970070085A KR 19970070085 A KR19970070085 A KR 19970070085A KR 100451151 B1 KR100451151 B1 KR 100451151B1
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wafer
back surface
dicing
metal layer
plating
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KR19990050893A (en
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임태윤
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Chemically Coating (AREA)

Abstract

PURPOSE: A method of plating a back surface of a wafer is provided to process clearly a dicing face of the wafer by performing a partial plating process on the remaining part except for a cut part of the wafer. CONSTITUTION: A thin metal layer(13) is formed on a back surface of a wafer(11). A photoresist layer pattern is formed on the thin metal layer. A plating process for the back surface of the wafer is performed. The photoresist layer is removed therefrom and the thin metal layer is removed by an etching process. An adhesive tape(16) is adhered on the gold(15) plated on the back surface of the wafer. The wafer is cut along a dicing face. The photoresist layer pattern is formed only on a wafer dicing part.

Description

웨이퍼 뒷면의 도금처리 방법Plating method on back side of wafer

본 발명은 웨이퍼 처리 기술에 관한 것으로, 특히 소자가 형성된 웨이퍼의 다이싱면을 깨끗하게 처리하여 수율을 향상시키고자 한 웨이퍼 뒷면의 도금처리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer processing technique, and more particularly, to a plating treatment method of a back surface of a wafer to improve the yield by cleanly treating a dicing surface of a wafer on which an element is formed.

첨부도면을 참조하여 종래 웨이퍼 뒷면 도금처리 방법에 대해 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional wafer backside plating method will be described.

도 1은 일반적인 웨이퍼 다이싱(wafer dicing)의 개요도로서, 도 1a 및 도 1b는 종래 웨이퍼 뒷면의 도금처리 방법을 도시한 공정단면도이고, 도 1c는 도금 처리되어 분리된 웨이퍼 뒷면을 도시한 것이다.1 is a schematic view of a typical wafer dicing, Figures 1a and 1b is a process cross-sectional view showing a conventional plating process on the back side of the wafer, Figure 1c shows the back side of the wafer separated by plating.

웨이퍼(1) 앞면에 소자(2) 제조공정이 끝나면, 도 1a에 도시한 바와 같이 웨이퍼(1)의 뒷면을 일정 정도 갈아내고 금(5)을 도금한 다음 접착력이 있는 테이프(6)를 붙인다.After the manufacturing process of the device 2 is completed on the front surface of the wafer 1, as shown in FIG. 1A, the back surface of the wafer 1 is ground to some extent, the gold 5 is plated, and the adhesive tape 6 is attached. .

이후, 도 1b에 도시한 바와 같이 다이싱 칼날(7)을 이용하여 웨이퍼(1)상에 형성된 각각의 소자(2)를 분리한다.Thereafter, as shown in FIG. 1B, each element 2 formed on the wafer 1 is separated using the dicing blade 7.

그러나, 도 1c에서 알 수 있는 바와 같이, 다이싱면 즉, 절단면이 울퉁불퉁하게 되어 도금된 금(5)의 가장자리가 매끄럽지 못하다. 따라서, 이러한 현상은 기계를 이용하여 대량으로 분리된 칩을 캐리어에 탑재(mount)할 때 웨이퍼의 불량을 유발시켜 수율을 떨어뜨리는 문제가 있다.However, as can be seen in Fig. 1C, the dicing surface, i.e., the cut surface is rugged, and the edge of the plated gold 5 is not smooth. Therefore, this phenomenon causes a problem of lowering the yield by causing defects of the wafer when mounting a large amount of separated chips in a carrier using a machine.

본 발명은 상기와 같은 종래의 문제를 해결하기 위하여 창안된 것으로, 웨이퍼 뒷면 전체의 도금 대신 얇은 금속층을 이용한 부분도금으로 대체함으로써 웨이퍼 뒷면의 절단면을 매끄럽게 하고자 하는 데 그 목적이 있다.The present invention has been made to solve the above-mentioned conventional problems, and its object is to smooth the cut surface of the back side of the wafer by substituting partial plating using a thin metal layer instead of the entire back side of the wafer.

도 1a 및 도 1b는 종래 웨이퍼 뒷면의 도금처리 방법을 나타낸 공정단면도.1A and 1B are cross-sectional views showing a conventional plating method of a wafer back surface.

도 1c는 종래 기술에 의해 도금 처리된 웨이퍼 뒷면을 도시한 단면도.1C is a cross-sectional view showing the backside of a wafer plated by the prior art;

도 2a 내지 도2e는 본 발명에 의한 웨이퍼 뒷면의 도금처리 방법을 나타낸 공정단면도.2A to 2E are cross-sectional views illustrating a plating process of a back surface of a wafer according to the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

11 : 웨이퍼 12 : 소자11 wafer 12 element

13 : 금속층 14 : 감광막13 metal layer 14 photosensitive film

15 : 금 16 : 테이프15: gold 16: tape

17 : 다이싱 칼날17: dicing blade

상기와 같은 목적을 달성하기 위한 본 발명 웨이퍼 뒷면의 도금처리 방법은, 소자가 형성된 웨이퍼 뒷면에 얇은 금속층을 형성하는 공정과, 상기 금속층위 웨이퍼가 절단될 부분에 감광막을 증착형성하는 공정과, 웨이퍼 뒷면을 도금하는 공정과, 상기 감광막을 제거하고 감광막 아래의 얇은 금속층을 식각하여 제거하는 공정과, 상기 도금된 금위에 접착력 있는 테이프를 붙이는 공정, 및 다이싱면을 따라 웨이퍼를 절단하는 공정을 포함하여 이루어진다.The plating process of the back surface of the present invention for achieving the above object, the process of forming a thin metal layer on the back of the wafer on which the device is formed, the process of depositing and forming a photosensitive film on the portion where the wafer on the metal layer is to be cut, and the wafer Plating the back side, removing the photoresist film and etching the thin metal layer under the photoresist, etching the adhesive tape onto the plated gold, and cutting the wafer along the dicing surface. Is done.

이와같은 본 발명에 대해 첨부도면을 참조하여 좀 더 상세히 설명하면 다음과 같다.When described in more detail with reference to the accompanying drawings for the present invention as follows.

도 2a 내지 도 2e는 본 발명에 의한 웨이퍼 뒷면의 도금처리 방법을 나타낸 공정단면도이다.2A to 2E are process cross-sectional views showing a plating treatment method of a back surface of a wafer according to the present invention.

먼저, 웨이퍼(11) 앞면에 소자(12) 제조 공정이 끝나면, 도 2a에 도시한 바와 같이 웨이퍼(11)의 뒷면을 일정 정도 갈아내고 도금을 하기 위해 전류가 흐를 수 있는 얇은 금속층(13)을 형성한다. 이후, 도 2b에 도시한 바와 같이 웨이퍼(11)의 다이싱 부분에만 감광막(14)의 패턴을 형성한다.First, when the manufacturing process of the device 12 is completed on the front surface of the wafer 11, as shown in FIG. 2A, a thin metal layer 13 through which a current may flow to grind the back surface of the wafer 11 to a certain degree and to plate is formed. Form. Subsequently, as shown in FIG. 2B, the pattern of the photosensitive film 14 is formed only on the dicing portion of the wafer 11.

그런 다음, 도 2c에 도시한 바와 같이 금(15)을 도금한다. 이때, 감광막(14)이 형성된 부분(다이싱 부분)에는 금(15)이 도금되지 않는다. 즉, 웨이퍼(11) 뒷면 전체가 도금되는 것이 아니라 부분도금이 되는 것이다.Then, gold 15 is plated as shown in FIG. 2C. At this time, the gold 15 is not plated on the portion (dicing portion) on which the photosensitive film 14 is formed. That is, the entire back surface of the wafer 11 is not plated, but partially plated.

이후, 도 2d에 도시한 바와 같이 감광막(14)을 제거하고 그 아래 형성되었던 얇은 금속층(13)을 식각하여 제거한 다음 도금된 웨이퍼(11)의 뒷면에 접착력있는 테이프(16)를 붙인다.Thereafter, as shown in FIG. 2D, the photosensitive film 14 is removed, the thin metal layer 13 formed below is etched away, and then the adhesive tape 16 is attached to the backside of the plated wafer 11.

마지막으로, 도 2e에 도시한 바와 같이, 다이싱 칼날(17)을 이용하여 다이싱면을 따라 웨이퍼(11)를 절단한다.Finally, as shown in FIG. 2E, the wafer 11 is cut along the dicing surface using the dicing blade 17.

상술한 바와 같이, 본 발명은 웨이퍼(11)가 절단될 부분을 제외하고 부분도금을 수행하여 웨이퍼(11)를 절단함으로써, 웨이퍼(11) 뒷면의 도금된 금(15)이 울퉁불퉁하게 찢기는 현상을 막을 수 있게 되어 웨이퍼(11)의 다이싱면을 깨끗하게 할 수 있다. 즉, 패턴공정을 이용한 웨이퍼 다이싱으로 제조의 수율을 향상시킬 수 있는 효과가 있다.As described above, the present invention cuts the wafer 11 by performing partial plating except for the portion where the wafer 11 is to be cut, thereby preventing the plated gold 15 of the back surface of the wafer 11 from being ragged. It is possible to prevent the dicing surface of the wafer 11 from being cleaned. That is, the wafer dicing using the pattern process has the effect of improving the production yield.

Claims (2)

소자가 형성된 웨이퍼 뒷면에 얇은 금속층을 형성하는 공정과,Forming a thin metal layer on the back side of the wafer on which the device is formed; 상기 금속층위에 감광막의 패턴을 형성하는 공정과,Forming a pattern of the photosensitive film on the metal layer; 웨이퍼 뒷면을 도금하는 공정과,Plating the back side of the wafer, 상기 감광막을 제거하고 감광막 아래의 얇은 금속층을 식각하여 제거하는 공정과,Removing the photoresist layer and etching by removing the thin metal layer under the photoresist layer; 상기 도금된 금위에 접착력 있는 테이프를 붙이는 공정과,Attaching an adhesive tape on the plated gold; 다이싱면을 따라 웨이퍼를 절단하는 공정을 포함하여 이루어지는 것을 특징으로 하는 웨이퍼 뒷면의 도금처리 방법.And a step of cutting the wafer along the dicing surface. 제 1 항에 있어서, 상기 감광막의 패턴은 웨이퍼 다이싱 부분에만 형성되는 것을 특징으로 하는 웨이퍼 뒷면의 도금처리 방법.The method of claim 1, wherein the pattern of the photosensitive film is formed only on the wafer dicing portion.
KR1019970070085A 1997-12-17 1997-12-17 Method of plating back surface of wafer for increasing productivity by processing clearly dicing face thereof Expired - Fee Related KR100451151B1 (en)

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