KR100451036B1 - Method of forming a gate electrode in a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device, wherein after forming a metal layer, selectively implanting impurity ions to nitride or injecting impurity ions while forming a metal layer to form a metal gate and a metal nitride gate, respectively, A method of forming a gate electrode of a semiconductor device capable of easily forming a gate electrode having another work function is provided.

Description

Method of forming a gate electrode in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device, and in particular, by implanting impurity ions selectively after nitriding a metal layer, or by implanting impurity ions while forming a metal layer to form a metal gate and a metal nitride gate, respectively. A method of forming a gate electrode of a semiconductor device capable of easily forming a gate electrode having a different work function.

BACKGROUND OF THE INVENTION Due to the high integration of semiconductor devices, various problems occur in design or manufacturing processes. Among them, polysilicon is used as a gate electrode, which is very difficult to apply to next-generation highly integrated semiconductor memory devices due to the large specific resistance of polysilicon itself. In order to solve this problem, various methods have been tried to reduce the specific resistance of the gate electrode by using a metal as a gate electrode instead of polysilicon to facilitate high-speed operation. In particular, since the metal gate has a mid band gap work function for the P-type and N-type, NMOS transistors and PMOS transistors of surface channels can be easily manufactured. . However, a metal gate electrode having an actual mid band gap has a problem in that a short channel effect occurs during operation of the device by forming a buried channel in both the NMOS transistor and the PMOS transistor. In order to solve this problem, a method of patterning a metal gate for NMOS and PMOS, respectively, and nitriding either metal to form NMOS and PMOS as surface channels using the work function difference between the metal nitride film and the metal is studied. have. However, if a general CVD or PVD method is carried out in a nitrogen atmosphere after mounting a metal target to form a metal nitride film, it is very difficult to precisely control the film quality under various process conditions such as vacuum conditions, degree of bias or deposition temperature. . In particular, in the case of PVD, an atmosphere gas such as argon gas penetrates into the membrane to increase resistance or cause other defects. Therefore, accurate resistance setting is difficult due to such impurity mixing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device capable of easily forming a surface channel by nitriding a metal electrode in one of an NMOS region and a PMOS region to have a different work function.

Another object of the present invention is to provide a method for forming a gate electrode of a semiconductor device which can prevent the characteristics of the metal nitride film from being degraded by the process conditions in the step of nitriding the metal electrode.

1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to a first embodiment of the present invention.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrates 12 and 22: p-well

13 and 23: n-well 14: gate insulating film

15 and 25: metal layer 16 and 26: photosensitive film

17 and 28: metal nitride films 24 and 27: first and second gate insulating films

The gate electrode forming method of the semiconductor device according to the first embodiment of the present invention

The gate electrode forming method of the semiconductor device according to the second embodiment of the present invention

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to a first embodiment of the present invention.

Referring to FIG. 1A, an NMOS region A is formed by implanting p-type impurities and n-type impurities into a predetermined region of the semiconductor substrate 11 to form a p-well 12 and an n-well 13, respectively. And the PMOS region B are determined. The gate insulating film 14 and the metal layer 15 are formed on the entire structure. Predetermined regions of the metal layer 15 and the gate insulating layer 14 are etched to form gate electrodes in the NMOS region A and the PMOS region B, respectively. As the metal layer 15, any one of Ti, Al, Ta, Cr, and W or an alloy thereof is used.

Referring to FIG. 1B, after the photoresist layer 16 is coated on the entire structure, the gate pattern of the PMOS region B is exposed to be patterned. In addition, the nitrogen ion implantation process is performed at an energy of 10 eV to 1 MeV depending on the type and thickness of the metal layer 15 so that the gate pattern of the exposed PMOS region B is completely nitrided to form the metal nitride film 17. In this case, oxygen or carbon may be used instead of nitrogen ions, and the implantation energy is changed according to the impurity ions to be implanted. For example, when the metal layer is titanium, when nitrogen ions are implanted with an energy of 5 keV, a TiN thin film having a thickness of about 300 kHz is formed. In addition, the total ion implantation amount is set in accordance with the operating characteristics of the device to be manufactured and investigated. For example, in the case of titanium, a TiN phase is formed from Ti at 3E15 / cm 2 or more during nitrogen ion implantation. The crystal structure at this time has (111) or (111) + (110), and the structure with a very small surface roughness is formed. Thereafter, while the (100) structure is formed at 4E15 / cm 2 or more, the (100) structure is mainly formed at 2E16 / cm 2 or more, and the surface roughness has been confirmed to increase. Based on these results, the crystal structure and the surface roughness of the film quality to be formed are controlled, and ultimately appropriate selection of the work function is possible.

1C is a cross-sectional view of a state in which a gate is formed by a metal layer 15 in an NMOS region and a gate electrode is formed in a metal nitride film 17 in a PMOS region B by removing the photoresist pattern 16.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method of forming a gate electrode of a semiconductor device according to a second embodiment of the present invention.

Referring to FIG. 2A, an NMOS region A is formed by implanting p-type impurities and n-type impurities into predetermined regions of the semiconductor substrate 21 to form the p-well 22 and the n-well 23, respectively. And the PMOS region B are determined. In the NMOS region A, the first gate insulating film 24 and the metal layer 25 are sequentially formed. Predetermined regions of the metal layer 25 and the first gate insulating layer 24 of the NMOS region A are etched to form a gate electrode in the NMOS region A. FIG. As the metal layer 25, any one of Ti, Al, Ta, Cr, and W or an alloy thereof is used.

Referring to FIG. 2B, the photoresist layer 26 is formed on the entire structure, and then patterned to expose only the region where the gate of the PMOS region B is to be formed. In the exposed portion of the PMOS region B, the second gate insulating layer 27 is formed to have the same thickness as the first gate insulating layer 24. In addition, while depositing the metal layer by a general PVD method such as evaporation and helicon sputter, a nitrogen ion implantation process is performed at an energy of 10 eV to 3 keV depending on the type and thickness of the metal layer to form the metal nitride film 28. To form. Here, any one of Ti, Al, Ta, Cr and W, or an alloy thereof may be used as the metal material to be deposited to form the metal nitride film 28, and oxygen or carbon may be injected into nitrogen nitrogen. It may be. At this time, the implantation amount of the impurity ions and the deposition rate of the metal layer are adjusted to form the film structure of the metal nitride film 28 and the like for a desired use. For example, when the ratio of the deposition rate of titanium and the nitrogen ion implantation amount is 1 or more, a (111) directional structure is formed, and when it is less than or less, a (100) directional structure is formed.

2C is a cross-sectional view of a state in which a gate is formed of a metal layer 25 in an NMOS region and a gate electrode is formed of a metal nitride film 27 in a PMOS region B by removing the photoresist pattern 26.

In the first and second embodiments of the present invention, the metal layer of the PMOS region is commonly described as being nitrided, but the metal layer of the NMOS region may be nitrided according to the characteristics of the device.

Meanwhile, as a third embodiment of the present invention, after the photoresist is formed over the entire structure including the NMOS region and the PMOS region, patterning is performed so that only the portion where the gate electrode of each region is to be formed is exposed, and metal deposition and ion implantation processes Conduct. In this case, a metal layer is formed in the NMOS region, and the ion beam itself is covered with a patterned cover so that metal deposition and ion implantation are simultaneously performed only in the PMOS region. That is, the structure of a general ion implantation apparatus is largely divided into a portion where ionization is performed, a portion extracting only ions to be implanted, an acceleration portion, and a deflector. In this case, when a cover or the like that conforms to the pattern of the metal nitride film is introduced into the deflector or the like, an area in which ions are implanted and an area not otherwise may be easily distinguished. In another method, a direct writing method is applied to easily distinguish between a region where direct ions are implanted and a region where no ions are implanted. Here, the metal layer and the ion implantation conditions are the same as in the second embodiment.

However, in the second and third embodiments of the present invention, since the implanted ions are implanted into the semiconductor substrate through the metal layer to be initially deposited, the ion implantation energy needs to be lowered to 3 keV or less. On the other hand, in the present invention, since ion implantation can be performed while depositing a metal layer, it is easier to secure the characteristics of the device. In particular, the energy of the ions implanted in the second and third embodiments serves to provide the binding energy with the purely deposited metal layer. That is, the thickness of the growing thin film depends on the deposition and ion implantation times.

As described above, according to the present invention, a gate having a different work function may be formed by selectively implanting impurity ions into the metal layer after forming the metal layer or implanting impurity ions while forming the metal layer to form a metal gate and a metal nitride gate, respectively. The electrode can be easily formed. Therefore, the surface channel CMOS transistor can be easily manufactured.

Claims (12)

Sequentially forming a gate insulating film and a metal layer on the semiconductor substrate in which the first region and the second region are determined; Etching a predetermined region of the metal layer and the gate insulating layer to form a gate pattern on the semiconductor substrate of the first region and the second region, respectively; And forming a metal nitride film by performing a nitrogen ion implantation process only on the metal layer of any one selected from the first region and the second region. The method of claim 1, wherein the first region is an NMOS region, and the second region is a PMOS region. The method of claim 1, wherein the metal layer is formed using any one of Ti, Al, Ta, Cr, and W or an alloy thereof. The method of forming a gate electrode of a semiconductor device according to claim 1, wherein oxygen or carbon ions are implanted instead of the nitrogen ions. The method for forming a gate electrode of a semiconductor device according to claim 1 or 4, wherein the nitrogen, oxygen, or carbon ions are performed at an energy of 10 eV to 1 MeV. Providing a semiconductor substrate having first and second regions defined therein; Forming a metal gate pattern by forming a first gate insulating layer and a first metal layer on the semiconductor substrate in any one of the first region and the second region, and then patterning the first gate insulating layer and the first metal layer; After forming a second gate insulating film in a predetermined region on the semiconductor substrate of another region selected from the first region and the second region, a metal nitride film is formed by injecting nitrogen ions while depositing a second metal layer to form a metal nitride film gate pattern. A method of forming a gate electrode of a semiconductor device comprising the step of. 7. The method of claim 6, wherein the first region is an NMOS region and the second region is a PMOS region. 7. The method of claim 6, wherein the metal layer is formed using any one of Ti, Al, Ta, Cr, and W or an alloy thereof. 7. The method as recited in claim 6, wherein oxygen or carbon ions are implanted instead of the nitrogen ions. 10. The method of claim 6 or 9, wherein the nitrogen, oxygen or carbon ions are implanted at an energy of 10 eV to 3 keV. The method of claim 6, wherein the second metal layer deposition and nitrogen ion implantation process is performed using a photoresist pattern that exposes a predetermined region of the semiconductor substrate to form a gate pattern in the predetermined region of the semiconductor substrate. Method of forming a gate electrode of a semiconductor device. The gate of the semiconductor device according to claim 6, wherein the second metal layer deposition and nitrogen ion implantation process is performed using a patterned cover to deposit the second metal layer while implanting the nitrogen ion beam in a predetermined region. Electrode formation method.