KR100448935B1 - Liquid crystal display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, comprising a gate line formed in one direction, a data line formed in a direction perpendicular to the gate line, and a gate line and a data line. The pixel pattern includes a pixel pattern of 1 and a pixel pattern formed one by one, and the thin film transistor liquid crystal display functions to prevent stitch defects between blocks in the substrate and to remove flicker.

Description

Liquid crystal display

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display having a horizontal stripe pixel array.

In general, there are mosaic, triangle, 4 pixel arrangement, and stripe types in the pixel array method. Stripe types suitable for letter and figure notation are mainly used for OA. The stripe type is a vertical stripe type in which RGB color filters are alternately arranged in the horizontal direction, and the same color filters are arranged in the vertical direction, and the same color filters are arranged in the horizontal direction and RGB in the vertical direction. There is a horizontal stripe type structure in which filter patterns are alternately arranged.

Next, a liquid crystal display according to the related art will be described with reference to the accompanying drawings.

1 is a wiring diagram of a liquid crystal display device of a vertical stripe arrangement method according to the prior art.

As shown in FIG. 1, gate lines G _n , G _{n + 1} ,... Are formed in a horizontal direction on a substrate of a liquid crystal display, and data lines D _n-1 , D _{n in a} vertical direction. , D _{n + 1} , D _{n + 2} , ....) are formed. The pixel is formed by the boundary portion where the gate lines G _n , G _{n + 1} , ... and the data lines D _n-1 , D _n , D _{n + 1} , D _{n + 2} , .... intersect each other. The regions are partitioned, and thin film transistors, which are three-terminal elements, are formed in each pixel region, and terminals of the thin film transistors are gate lines G _n , G _{n + 1} ,..., And data lines D _{n −, respectively. 1} , D _n , D _{n + 1} , D _{n + 2} , ....) and the common electrode of the color filter substrate. As described above, when the pixel array is a vertical stripe type, R, G, and B color patterns are alternately formed for each pixel region for each pixel row corresponding to one gate line G _{n + 1} , and the pixel column direction The same kind of color pattern is formed. If the size of one pixel region is X × 3X, and the R, G, and B patterns form a single point region, the size of this point region is 3 ×× 3X. The load capacitance C _d for the data line in the point region and the load capacitance C _g for the gate line are generally as follows.

C _d = C _cr + C _dc + C _gd

C _g = C _cr + C _ge + [C _gs ⊥ (C _st // C _lc )] + [C _st ⊥ (C _gs // C _lc )]

C _d : total load capacity of the data line

C _cr : capacitance due to the intersection of the gate line and the data line

C _dc : auxiliary capacitance by data line

C _gc : Auxiliary capacity by gate line

C _gd : capacitance by the gate electrode and the drain electrode

However, the load capacities (C _d and C _g ) of the data lines and the gate lines should be considered in terms of fringe capacities according to the trend of higher definition and higher image quality of thin film transistor liquid crystal displays. The fringe capacitance (C _fringe ) refers to a capacitance that acts between the data line and the pixel electrode and between lines that are separated to some extent, such as between the data line and the gate line. Given this fringe capacity (C _fringe ),

C _d = C _cr + C _dc + C _{gd +} C _fringe

C _g = C _cr + C _ge + [C _gs ⊥ (C _st // C _lc )] + [C _st ⊥ (C _gs // C _lc )] + C _fringe

to be.

In view of the above equation, the conventional vertical stripe type thin film transistor liquid crystal display has a large fringe capacitance (C _fringe ).

That is, the length of the data line interacting with the pixel electrode for one point area is 9X (= 3X + 3X + 3X), and has a fringe capacity proportional to the length. In addition, one gate line G _n intersects with three data lines D _n-1 , D _n , D _{n + 1} in one point region, and the capacitance C _cr is formed by the intersection. do. At this time, a considerable amount of capacitance is formed. In particular, when the substrate is formed in units of blocks by using a stepper method, a difference in fringe capacity between blocks due to misalignment occurs. Stitch defects occur.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and to implement a thin film transistor liquid crystal display device which prevents flicker by reducing the fringe capacity to eliminate stitch defects caused by misalignment and reducing the load capacity applied to the gate line. Let's do that task.

1 is a wiring diagram of a liquid crystal display device according to the related art.

2 is a wiring diagram of a liquid crystal display device according to the present invention.

According to an exemplary embodiment of the present invention, a thin film transistor liquid crystal display device is partitioned by a gate line formed in one direction, a data line formed in a direction perpendicular to the gate line, a gate line, and a data line. A pixel area having a height ratio of 3: 1 and a color pattern formed by one pixel area are included.

The thin film transistor liquid crystal display prevents stitch defects and removes flicker.

Next, the thin film transistor liquid crystal display according to the exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings so that a person skilled in the art can easily implement the same.

2 is a wiring diagram of a horizontal stripe liquid crystal display according to an exemplary embodiment of the present invention.

As shown in Fig. 2, in the horizontal stripe type liquid crystal display device, a color pattern of the same color is formed for each pixel region for one pixel row by one gate line G _n , and R, G in the pixel column direction. , B color patterns are alternately formed. The horizontal length of the color pattern: The vertical length is 3: 1, and thus, the size of one pixel area is 3X × X. As in the related art, since the RGB patterns are gathered one by one to form one point region, one point region of the pixel has a size of 3X × 3X. However, in the fringe capacitance C _fringe between the data line D _n and the pixel electrode, one data line D _n present in one point region is 3X (X + X + X) long with the pixel electrode. Because of the mutual influence in the interval of, it is reduced to approximately 30% compared to the capacity for the conventional 9X length, and also the fringe capacitance (C _fringe ) acting between the gate line (G _n ) and the data line (D _n ) is also 30 Decreases in%

The variation of the voltage charged in the pixel electrode due to such fringe capacitance (C _fringe ) is

_{ΔV pix-ito} = [C _fringe / (C _total + C _fringe )] × _{ΔV d}

to be.

In order to reduce the variation ( _{ΔV pix-ito} ) of the voltage charged in the pixel electrode, the fringe capacitance (C _fringe ), which is a relatively smaller value than the _total capacitance (C _total ), should be smaller. Since C _fringe ) is reduced by about 30%, it is possible to greatly reduce the variation ( _{ΔV pix-ito} ) of the voltage charged in the pixel electrode. Therefore, even if a misalignment occurs between blocks, interblock stitch defects due to differences in fringe capacity (C _fringe ) are not relatively large.

In addition, in the case of the load capacitance C _{g applied to} the gate line, since only one data line D _n-1 intersects one gate line G _n in one point region, the data line and the gate line intersect each other. One gate line is reduced because the negative capacitance (C _cr ) is reduced to about 30% compared to the conventional one, and the fringe capacitance (C _fringe ) acting on the difference between the gate line and the data line is reduced to less than half of the conventional one. It can reduce the load capacity of about 50%. Therefore, the filling property in a board | substrate improves.

As described above, the liquid crystal display according to the present invention has the effect of preventing the flicker phenomenon by reducing the fringe capacity to prevent stitch defects, reduce the load capacity applied to the gate line to improve the charging characteristics in the substrate.

Claims (2)

A gate line formed in one direction, A data line formed in a direction perpendicular to the gate line; A pixel region partitioned by the gate line and the data line and having a ratio of width to height of 3: 1, A color pattern formed on each of the pixel areas Liquid crystal display comprising a. The liquid crystal display of claim 1, wherein the color patterns are arranged in a horizontal stripe type.

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