KR100443509B1 - Method for forming fine pattern of semiconductor - Google Patents
Method for forming fine pattern of semiconductor Download PDFInfo
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- KR100443509B1 KR100443509B1 KR10-2001-0082684A KR20010082684A KR100443509B1 KR 100443509 B1 KR100443509 B1 KR 100443509B1 KR 20010082684 A KR20010082684 A KR 20010082684A KR 100443509 B1 KR100443509 B1 KR 100443509B1
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- 238000000034 method Methods 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 238000001312 dry etching Methods 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000007789 gas Substances 0.000 claims description 35
- 230000008569 process Effects 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005108 dry cleaning Methods 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 239000000460 chlorine Substances 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- 125000005004 perfluoroethyl group Chemical group FC(F)(F)C(F)(F)* 0.000 claims description 3
- -1 or the like Substances 0.000 claims 1
- 238000004140 cleaning Methods 0.000 abstract description 5
- 239000006227 byproduct Substances 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 3
- 239000011247 coating layer Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 description 12
- 230000018109 developmental process Effects 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- DXHPZXWIPWDXHJ-UHFFFAOYSA-N carbon monosulfide Chemical compound [S+]#[C-] DXHPZXWIPWDXHJ-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052717 sulfur Inorganic materials 0.000 description 2
- 239000011593 sulfur Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
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- Inorganic Chemistry (AREA)
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Abstract
본 발명은 식각부산물에 의한 장비 세정 주기의 감소를 방지하면서 감광막의 건식 현상과 폴리실리콘막의 건식 식각을 연속적으로 수행할 수 있도록 하는 다층 구조의 감광막을 이용한 미세 패턴 형성방법을 개시한다. 개시된 본 발명의 방법은, 반도체 기판 상에 게이트 산화막 및 게이트용 도전막을 차례로 형성하는 단계와, 상기 게이트용 도전막 상에 유기성분의 하층 감광막과 실리콘이 1∼30wt%로 함유된 상층 감광막을 차례로 도포하는 단계와, 상기 상층 감광막을 노광 및 현상해서 게이트 형성 영역을 한정하는 상층 감광막 패턴을 형성하는 단계와, 상기 상층 감광막 패턴으로 가려지지 않은 하층 감광막 부분을 O2 및 HBr를 포함한 혼합 가스로 건식 현상하여 하층 감광막 패턴을 형성하는 단계와, 상기 상층 및 하층 감광막 패턴을 이용해서 상기 게이트용 도전막을 건식 식각하는 단계와, 상기 잔류된 감광막 패턴을 제거하는 단계를 포함한다.The present invention discloses a method of forming a fine pattern using a photosensitive film having a multilayer structure, which allows the dry phenomenon of the photosensitive film and the dry etching of the polysilicon film to be continuously performed while preventing the reduction of the equipment cleaning cycle by the etching by-product. The disclosed method comprises sequentially forming a gate oxide film and a gate conductive film on a semiconductor substrate, and then sequentially forming a lower photosensitive film of an organic component and an upper photosensitive film containing 1 to 30 wt% of silicon on the gate conductive film. Applying a coating layer, exposing and developing the upper photoresist film to form an upper photoresist pattern defining a gate formation region, and dry developing a portion of the lower photoresist layer not covered by the upper photoresist pattern with a mixed gas including O2 and HBr. Forming a lower photoresist pattern, dry etching the gate conductive film using the upper and lower photoresist patterns, and removing the remaining photoresist pattern.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 다층 구조의 감광막을 이용한 미세 패턴 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a fine pattern using a photosensitive film having a multilayer structure.
반도체 소자를 제조함에 있어서, 콘택홀을 포함한 각종 패턴들은 포토리소그라피(Photolithography) 공정을 통해 형성된다. 이러한 포토리소그라피 공정은, 주지된 바와 같이, 감광막 패턴을 형성하는 공정과 상기 감광막 패턴을 마스크로해서 피식각층을 식각하는 공정을 포함하며, 상기 감광막 패턴을 형성하는 공정은 피식각층 상에 감광막을 도포하는 공정과, 특정 노광 마스크를 이용하여 상기 감광막을 선택적으로 노광하는 공정 및 소정의 화학용액으로 노광되거나 또는 노광되지 않은 감광막 부분을 제거하는 현상 공정으로 구성된다.In manufacturing a semiconductor device, various patterns including contact holes are formed through a photolithography process. The photolithography process includes, as is well known, a process of forming a photoresist pattern and a process of etching the etched layer using the photoresist pattern as a mask, and the process of forming the photoresist pattern includes applying a photoresist on the etched layer. And a step of selectively exposing the photosensitive film using a specific exposure mask and a developing step of removing a portion of the photosensitive film exposed or not exposed with a predetermined chemical solution.
한편, 반도체 소자의 집적도가 증가됨에 따라 패턴 크기의 축소가 수반되고 있는 실정에서, 상기 포토리소그라피 공정에 대한 기술 개발도 활발하게 진행되고 있다.Meanwhile, as the degree of integration of semiconductor devices increases, the size of the pattern is accompanied by a decrease in the size of the pattern. Accordingly, the technology for the photolithography process is actively being developed.
여기서, 현재의 미세 패턴 형성 기술은 노광장치에서 사용되는 광원을 짧은 파장의 것을 선택하는 방법으로 진행되어 왔다. 예를들면, 기존의 노광장치는 광원으로서 G-line(λ=435㎚) 또는 I-line(λ=365㎚)을 주로 사용하여 왔으나, 이러한 광원들은 분해능 한계로 인해 고집적 소자에서 요구되는 미세 선폭의 패턴을 형성하기가 곤란하게 되었고, 그래서, 최근에는 상기 광원들 보다 더 짧은 파장을 갖는 KrF(λ=248㎚) 또는 ArF(λ=193㎚) 등을 노광장치의 광원으로 이용하게 되었으며, 더 나아가, 전자빔, 이온빔 및 X-ray와 같은 비광학적 광원도 이용하게 되었다.Here, the current fine pattern formation technique has been advanced by a method of selecting a short wavelength as the light source used in the exposure apparatus. For example, conventional exposure apparatuses have mainly used G-line (λ = 435 nm) or I-line (λ = 365 nm) as light sources, but these light sources have a fine line width that is required in high-density devices due to resolution limitations. It has become difficult to form a pattern of and thus, recently, KrF (λ = 248 nm) or ArF (λ = 193 nm) or the like having a shorter wavelength than those of the light sources has been used as the light source of the exposure apparatus. Furthermore, non-optical light sources such as electron beams, ion beams and X-rays have also been used.
그러나, 상기한 방법은 그 이용이 용이하다는 잇점은 있지만, 장비에 소요되는 투자 비용이 매우 크므로, 실질적으로 그 적용에는 어려움이 있다.However, the above-mentioned method has the advantage of ease of use, but the investment cost for the equipment is very large, so that its practical application is difficult.
따라서, 상기한 방법 이외에, 단일층의 감광막이 아닌 다층의 감광막을 이용하여 기존의 광원들을 이용하면서도 미세 패턴의 형성이 가능하도록 하는 기술이 새롭게 제안되었고, 이에 대한 연구가 활발하게 진행되고 있다.Therefore, in addition to the above-described method, a technique has been newly proposed to enable the formation of a fine pattern while using existing light sources using a multilayer photoresist instead of a single photoresist, and research on this has been actively conducted.
이하에서는 상기한 다층 구조의 감광막을 이용한 미세 패턴 형성방법을 간략하게 설명하도록 한다.Hereinafter, a method of forming a fine pattern using the photosensitive film of the multilayer structure will be described briefly.
우선, 반도체 기판 상에 식각대상층, 예컨데, 게이트 형성을 위한 폴리실리콘막을 증착한 상태에서, 상기 폴리실리콘막 상에 하층 감광막과 상층 감광막을 차례로 도포한다. 이때, 상기 하층 감광막은 두껍게 도포하는 반면, 상층 감광막은 붕괴(collapse) 현상의 방지를 위해 500∼2,500Å 정도의 낮은 두께로 도포한다.First, in a state in which an etching target layer, for example, a polysilicon film for gate formation is deposited on a semiconductor substrate, a lower photoresist film and an upper photoresist film are sequentially applied to the polysilicon film. In this case, the lower photoresist film is applied thickly, while the upper photoresist film is applied at a low thickness of about 500 to 2,500 Pa to prevent a collapse phenomenon.
그런다음, 상기 상층 감광막을 노광 및 현상해서 상층 감광막 패턴을 형성하고, 이어서, 하층 감광막 패턴이 형성되도록 상기 하층의 감광막을 건식 식각 장비에서 O2 및 SO2 가스를 이용하여 건식 현상한다.Thereafter, the upper photoresist film is exposed and developed to form an upper photoresist pattern. Then, the lower photoresist film is dry-developed using O2 and SO2 gas in a dry etching apparatus to form a lower photoresist pattern.
그리고나서, 상층 및 하층 감광막 패턴을 이용하여 그 하부의 폴리실리콘막을 식각함으로써, 소망하는 미세 폭의 게이트를 형성한다.Then, by etching the lower polysilicon film using the upper and lower photosensitive film patterns, a gate having a desired fine width is formed.
상기에서, 하층 감광막의 건식 현상을 위해 SOx(x=1∼4) 계열의 황(S)을 함유한 가스를 이용하게 되면, 상기 황(S)이 감광막에 포함되어 있는 탄소(C) 성분과 반응하여 CySz(y,z는 자연수), 즉, 황화탄소계열의 원소를 포함한 측벽 폴리머를 형성하게 되고, 이에 따라, 이방성 건식 현상이 이루어지게 되어 소망하는 미세 패턴을 형성할 수 있게 된다.In the above, when the gas containing SOx (x = 1 to 4) -based sulfur (S) is used for the dry development of the lower photoresist film, the sulfur (S) and the carbon (C) component included in the photoresist film By reacting, CySz (y, z is a natural number), that is, a sidewall polymer including carbon sulfide-based elements is formed, and thus, anisotropic dry phenomenon is performed to form a desired fine pattern.
그러나, 전술한 바와 같은 종래의 미세 패턴 형성방법은 저가의 장비를 사용하면서도 미세 패턴을 형성할 수 있다는 장점은 있지만, 황화탄소계열의 원소를 포함한 식각부산물이 식각 장비의 내벽에도 쌓이게 됨으로써, 장비 세정 주기가 짧아지게 되고, 그래서, 생산성이 저하된다는 단점이 있다.However, the conventional fine pattern forming method as described above has the advantage of being able to form a fine pattern while using a low-cost equipment, the etching by-products containing carbon sulfide-based elements are also accumulated on the inner wall of the etching equipment, cleaning equipment There is a disadvantage that the cycle is shortened, so that the productivity is lowered.
또한, O2 및 SO2 가스를 이용한 하층 감광막의 건식 현상은 그 자체로는 커다란 문제가 없지만, 웨이퍼 스테이지의 온도를 -20℃로 유지시켜 수행하는 것과 관련하여, 후속하는 폴리실리콘막의 식각을 연속적으로 진행할 수 없는 바, 공정 상의 번거로움이 존재한다. 여기서, 하층 감광막의 건식 현상과 폴리실리콘막의 건식 식각을 연속적으로 수행할 수 없는 이유는, 상기 건식 현상과 건식 식각을 연속적으로 수행하게 되면, SOx 계열의 폴리머가 폴리실리콘의 표면에 다량 증착되어 폴리실리콘의 식각시에 잔류물 등을 유발하게 되는 것과, 하층 감광막의 건식 식각과 폴리실리콘막의 건식 식각시에 웨이퍼 스테이지의 온도 차이가 30℃ 이상 차이가 난다는 것에 그 원인이 있다.In addition, the dry phenomenon of the lower photoresist film using O2 and SO2 gas is not a big problem in itself, but in connection with carrying out by keeping the temperature of the wafer stage at -20 ° C, the subsequent etching of the polysilicon film can be continuously performed. Unexpectedly, process hassles exist. The reason why the dry phenomenon of the lower photoresist film and the dry etching of the polysilicon film cannot be continuously performed is that when the dry phenomenon and the dry etching are continuously performed, a large amount of SOx-based polymer is deposited on the surface of polysilicon The reason for this is that residues are caused during the etching of silicon, and that the temperature difference between the wafer stages differs by 30 ° C or more during the dry etching of the lower photosensitive film and the dry etching of the polysilicon film.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 식각부산물에 의한 장비 세정 주기의 감소를 방지하면서 감광막의 건식 현상과 폴리실리콘막의 건식 식각을 연속적으로 수행할 수 있도록 하는 다층 구조의 감광막을 이용한 미세 패턴 형성방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, a multi-layered structure that allows the dry phenomenon of the photoresist film and the dry etching of the polysilicon film continuously while preventing the reduction of equipment cleaning cycle by the etching by-products. An object of the present invention is to provide a method of forming a fine pattern using a photosensitive film.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 미세 패턴 형성방법을 설명하기 위한 각 공정별 단면도.1A to 1F are cross-sectional views for each process for explaining a method for forming a fine pattern according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
1 : 반도체 기판 2 : 게이트 산화막1 semiconductor substrate 2 gate oxide film
3 : 폴리실리콘막 3a : 게이트3: polysilicon film 3a: gate
4 : 하층 감광막 4a : 하층 감광막 패턴4: lower layer photosensitive film 4a: lower layer photosensitive film pattern
5 : 상층 감광막 5a : 상층 감광막 패턴5: upper photoresist film 5a: upper photoresist film pattern
6 : 산화막 7 : 측벽 폴리머6: oxide film 7: sidewall polymer
상기와 같은 목적을 달성하기 위한 본 발명의 미세 패턴 형성방법은, 반도체 기판 상에 게이트 산화막 및 게이트용 도전막을 차례로 형성하는 단계; 상기 게이트용 도전막 상에 유기성분의 하층 감광막과 실리콘이 1∼30wt%로 함유된 상층 감광막을 차례로 도포하는 단계; 상기 상층 감광막을 노광 및 현상해서 게이트 형성 영역을 한정하는 상층 감광막 패턴을 형성하는 단계; 상기 상층 감광막 패턴으로 가려지지 않은 하층 감광막 부분을 O2 및 HBr를 포함한 혼합 가스로 건식 현상하여 하층 감광막 패턴을 형성하는 단계; 상기 상층 및 하층 감광막 패턴을 이용해서 상기 게이트용 도전막을 건식 식각하는 단계; 및 상기 잔류된 감광막 패턴을 제거하는 단계를 포함한다.The fine pattern forming method of the present invention for achieving the above object comprises the steps of sequentially forming a gate oxide film and a gate conductive film on a semiconductor substrate; Sequentially applying a lower photosensitive film of an organic component and an upper photosensitive film containing 1 to 30 wt% of silicon on the conductive film for the gate; Exposing and developing the upper photoresist film to form an upper photoresist pattern defining a gate formation region; Dry developing the lower photosensitive film portion not covered by the upper photosensitive film pattern with a mixed gas including O 2 and HBr to form a lower photosensitive film pattern; Dry etching the gate conductive film using the upper and lower photoresist patterns; And removing the remaining photoresist pattern.
여기서, 본 발명의 방법은 게이트용 도전막으로 폴리실리콘막 또는 비정질실리콘막을 이용한다.Here, the method of the present invention uses a polysilicon film or an amorphous silicon film as the gate conductive film.
또한, 본 발명의 방법은 하층 감광막의 건식 현상을 N2, H2 및 N2H2 가스 중에서 선택되는 어느 하나를 더 첨가하여 수행한다.In addition, the method of the present invention performs the dry phenomenon of the lower photosensitive film by further adding any one selected from N2, H2 and N2H2 gas.
게다가, 본 발명의 방법은 하층 감광막 패턴을 형성하는 단계 후, 그리고, 게이트용 도전막을 식각하는 단계 전, 상기 하층 감광막 패턴을 형성하는 단계에서 상기 상층 감광막 패턴의 표면에 형성된 실리콘산화막과 상기 폴리실리콘막 표면의 자연산화막 및 실리콘산화막이 제거되도록 건식 세정 공정을 수행하는 단계를 더 포함하며, 상기 건식 세정 공정은 C2F5, CF4, CHF3 및 SF6 등과 같은 불소 함유 가스, 또는, Cl2 및 CCl2∼4 등과 같은 염소 함유 가스를 이용하여 수행한다.In addition, the method of the present invention is a silicon oxide film and the polysilicon formed on the surface of the upper photosensitive film pattern in the step of forming the lower photosensitive film pattern after forming the lower photosensitive film pattern, and before etching the gate conductive film. And performing a dry cleaning process to remove the natural oxide film and the silicon oxide film on the surface of the film, wherein the dry cleaning process includes a fluorine-containing gas such as C2F5, CF4, CHF3, SF6, or Cl2, CCl2-4, or the like. It is carried out using a chlorine containing gas.
아울러, 본 발명의 방법은 상기 하층 감광막 패턴 형성을 위한 하층 감광막의 건식 현상과, 상기 게이트용 도전막의 건식 식각을 연속적으로 수행한다.In addition, the method of the present invention performs the dry phenomenon of the lower photosensitive film for forming the lower photosensitive film pattern, and the dry etching of the gate conductive film.
본 발명에 따르면, 하층 감광막의 건식 현상을 O2 및 HBr 가스를 사용하여 수행하기 때문에 장비 내벽의 폴리머 축적에 기인하는 장비 세정 주기의 감소를 방지할 수 있으며, 아울러, 하층 감광막의 건식 현상과 게이트용 도전막의 건식 식각을 연속적으로 수행할 수 있어서 공정 상의 번거로움을 해결할 수 있다.According to the present invention, since the dry phenomenon of the lower photoresist film is performed using O2 and HBr gas, it is possible to prevent the reduction of the equipment cleaning cycle due to the accumulation of polymer in the inner wall of the equipment, and also to prevent the dry phenomenon of the lower photoresist film and the gate. Dry etching of the conductive film can be performed continuously, thereby eliminating the inconvenience of the process.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1f는 본 발명의 실시예에 따른 미세 패턴 형성방법을 설명하기 위한 각 공정별 단면도이다.1A to 1F are cross-sectional views of respective processes for describing a method for forming a fine pattern according to an embodiment of the present invention.
도 1a를 참조하면, 반도체 기판(1) 상에 게이트 산화막(2)과 게이트용 도전막, 예컨데, 폴리실리콘막(3)을 차례로 형성한다. 여기서, 상기 폴리실리콘막(3) 대신에 비정질실리콘막을 형성하는 것도 가능하다. 이어서, 상기 폴리실리콘막(3) 상에 유기(organic) 성분의 하층 감광막(4)과 실리콘 등을 함유한 상층 감광막(5)을 차례로 도포한다. 이때, 상기 상층 감광막(5)은 실리콘 조성을 1∼30wt% 정도가 되도록 조절한다.Referring to FIG. 1A, a gate oxide film 2 and a gate conductive film, for example, a polysilicon film 3 are sequentially formed on the semiconductor substrate 1. It is also possible to form an amorphous silicon film instead of the polysilicon film 3 here. Subsequently, the lower photosensitive film 4 of an organic component and the upper photosensitive film 5 containing silicon etc. are apply | coated on the said polysilicon film 3 in order. In this case, the upper photoresist film 5 is adjusted to have a silicon composition of about 1 to 30 wt%.
도 1b를 참조하면, I-line 및 KrF와 같은 광원을 구비한 기존의 노광장비를 이용해서 상기 상층 감광막을 노광하고, 노광된 상층 감광막에 대한 현상을 수행하여 게이트 형성 영역을 한정하는 상층 감광막 패턴(5a)을 형성한다.Referring to FIG. 1B, the upper photoresist pattern is exposed using an existing exposure apparatus including a light source such as I-line and KrF, and the upper photoresist pattern is formed to define a gate formation region by performing development on the exposed upper photoresist. (5a) is formed.
도 1c를 참조하면, O2 및 HBr을 포함한 혼합가스을 이용해서 노출된 하층 감광막 부분을 건식 현상하고, 이 결과로, 하층 감광막 패턴(4a)을 형성한다. 이때, 상층 감광막 패턴(5a)의 표면에는 상기 상층 감광막 패턴(5a) 내에 함유되어 있는 실리콘과 건식 현상을 위해 공급된 O2 가스가 반응하여 실리콘산화막(SiO2 : 6)이 형성되며, 이러한 실리콘산화막(6)이 하층 감광막의 건식 현상 동안에 현상 베리어(barrier)로서 역할을 하여 상기 하층 감광막의 건식 현상이 이루어지게 된다. 또한, 상기 하층 감광막의 건식 현상시, 하층 감광막 패턴(4a)의 측벽에는 Br-O-C-H-Si 성분의 얇은 폴리머(7)가 형성되며, 이러한 폴리머(7)에 의해 상기 하층 감광막의 비등방성 현상이 이루어지게 된다.Referring to FIG. 1C, the exposed lower photosensitive film portion is dry-developed using a mixed gas containing O2 and HBr, and as a result, the lower photosensitive film pattern 4a is formed. At this time, the silicon oxide film (SiO 2: 6) is formed on the surface of the upper photoresist pattern 5a by reacting silicon contained in the upper photoresist pattern 5a with O 2 gas supplied for dry development. 6) acts as a developing barrier during the dry development of the lower photoresist film, resulting in dry development of the lower photoresist film. In the dry development of the lower photoresist film, a thin polymer 7 of Br-OCH-Si component is formed on the sidewall of the lower photoresist pattern 4a, and the polymer 7 prevents anisotropic phenomenon of the lower photoresist film. Will be done.
결국, 하층 감광막의 건식 현상은 O2 및 HBr 가스를 사용하더라도 그 진행이 가능하며, 특히, 기존의 SO2 가스 대신에 HBr 가스를 사용한 것과 관련하여 웨이퍼 스테이지의 온도를 -20℃ 이상으로 유지시켜도 상기 건식 현상의 진행이 가능하다.As a result, the dry phenomenon of the lower photoresist film can proceed even if O2 and HBr gases are used, and in particular, even if the temperature of the wafer stage is maintained above -20 ° C in relation to the use of HBr gas instead of the conventional SO2 gas. The development of the phenomenon is possible.
도 1d를 참조하면, 상기 결과물에 대해 C2F5, CF4, CHF3 및 SF6 등과 같은 불소 함유 가스, 또는, Cl2 및 CCl2∼4 등과 같은 염소 함유 가스를 이용한 건식세정을 수행하여 상기 O2 및 HBr 가스를 이용한 건식 현상 단계에서 상층 감광막 패턴(5a)의 표면에 발생된 산화막을 제거한다. 이때, 상기 상기 건식 세정은 상기 하층 감광막의 건식 현상의 결과로 노출된 폴리실리콘막(3) 표면에서의 자연산화막 및 그 이외의 인위적인 산화 현상에 의해 발생되는 산화막이 함께 제거되도록 수행한다.Referring to FIG. 1D, dry cleaning using fluorine-containing gas such as C2F5, CF4, CHF3 and SF6, or chlorine-containing gas such as Cl2 and CCl2 to 4 may be performed on the resultant product. In the developing step, the oxide film generated on the surface of the upper photosensitive film pattern 5a is removed. At this time, the dry cleaning is performed such that the natural oxide film on the surface of the polysilicon film 3 exposed as a result of the dry phenomenon of the lower photosensitive film and the oxide film generated by other artificial oxidation phenomenon are removed together.
도 1e를 참조하면, 상기 건식 현상 공정에 연속해서 상층 및 하층 감광막 패턴을 이용하여 노출된 폴리실리콘막 부분을 연속해서 건식 식각하고, 이 결과로서, 게이트(3a)를 형성한다. 이때, 상층 감광막 패턴은 이전 공정 단계에서 그 표면에 형성된 실리콘산화막이 제거된 것과 관련하여 상기 폴리실리콘막의 건식 식각시에 모두 제거된다.Referring to FIG. 1E, the polysilicon film portion exposed using the upper and lower photoresist pattern in succession to the dry development process is continuously dry-etched, and as a result, the gate 3a is formed. At this time, the upper photoresist pattern is removed during dry etching of the polysilicon film in relation to the removal of the silicon oxide film formed on the surface in the previous process step.
도 1f를 참조하면, 잔류된 하층 감광막 패턴을 제거함으로써, 본 발명의 미세 패턴, 즉, 미세 폭을 갖는 게이트(3a)의 형성을 완성한다.Referring to FIG. 1F, the formation of the fine pattern of the present invention, that is, the gate 3a having the fine width, is completed by removing the remaining lower photoresist pattern.
전술한 바와 같이, 본 발명은 O2 가스를 기본으로 하여 폴리실리콘의 건식 식각에 범용적으로 사용되는 HBr 가스를 혼합하여 사용함으로써, Br-O-C-H-Si의 측벽 폴리머를 형성시켜 하층 감광막의 비등방성 식각이 가능하도록 할 수 있으며, 아울러, 이러한 측벽 폴리머는 SOx 계열의 폴리머 보다 결합력이 약해서 식각 장비 내벽에 쌓이는 현상이 거의 일어나지 않는다. 또한, SO2 가스 대신에 HBr 가스를 사용함에 따라, 웨이퍼 스테이지의 온도를 -20℃ 이상으로 유지킬 수 있으며, 그래서, 후속하는 폴리실리콘막의 건식 식각을 연속해서 수행할 수 있다.As described above, the present invention uses a mixture of HBr gas commonly used for dry etching of polysilicon based on O2 gas, thereby forming a sidewall polymer of Br-OCH-Si to form an anisotropic etching of the lower layer photoresist film. In addition, such sidewall polymers have a weaker bonding force than SOx-based polymers, so that they rarely accumulate on the inner wall of the etching equipment. In addition, by using HBr gas instead of SO2 gas, the temperature of the wafer stage can be maintained at -20 ° C or higher, so that subsequent dry etching of the polysilicon film can be performed continuously.
한편, 전술한 본 발명의 실시예에서는 하층 감광막의 건식 현상을 O2 가스를 기본으로해서 HBr 가스를 사용하여 수행하였지만, N2, H2 또는 N2H2 가스를 첨가하여 수행할 수 있으며, 또한, 상기 HBr 가스 대신에 H2+Br2 가스, H2+Cl2 및 HCl 가스를 사용하는 것도 가능하다. 아울러, 측벽 폴리머의 형성을 위해 HBr 가스만을 사용하였지만, SOx(x=1∼4) 가스를 추가 첨가하여 HBr에 의한 측벽 폴리머 형성을 보조할 수도 있다.Meanwhile, in the above-described embodiment of the present invention, the dry phenomenon of the lower photoresist film is performed using HBr gas based on O2 gas, but may be performed by adding N2, H2 or N2H2 gas, and instead of the HBr gas. It is also possible to use H2 + Br2 gas, H2 + Cl2 and HCl gas. In addition, although only HBr gas was used to form the sidewall polymer, SOx (x = 1 to 4) gas may be further added to assist in the formation of the sidewall polymer by HBr.
이상에서와 같이, 본 발명은 미세 패턴을 형성하기 위해 다층 감광막 구조를 이용함에 있어서, 유기 성분의 하층 감광막의 건식 현상을 O2 및 HBr 가스를 사용함으로써, SO2 가스를 사용하는 종래와 비교해서 비등방성 식각 특성을 그대로 유지시키면서도 장비 내벽에의 폴리머 축적을 방지할 수 있고, 이에 따라, 식각부산물에 의한 장비 세정 주기가 짧아지는 현상을 방지할 수 있는 바, 생산성의 향상을 얻을 수 있다.As described above, the present invention is anisotropic compared to the conventional use of SO2 gas by using O2 and HBr gas in the dry phenomenon of the lower photosensitive film of the organic component in using a multilayer photosensitive film structure to form a fine pattern Accumulation of the polymer on the inner wall of the equipment can be prevented while maintaining the etching characteristics. As a result, a shortening of the equipment cleaning cycle due to the etching by-product can be prevented, thereby improving productivity.
또한, 본 발명은 상기 하층 감광막의 건식 현상시에 SO2 가스 대신에 HBr 가스를 사용함에 따라 웨이퍼 스테이지의 온도를 -20℃ 이상으로 조절할 수 있으며, 따라서, 후속하는 폴리실리콘막의 건식 식각을 동일 장비내에서 연속적으로 수행할 수 있어서, 공정 상의 잇점도 얻을 수 있다.In addition, the present invention can control the temperature of the wafer stage to -20 ℃ or more by using HBr gas instead of SO2 gas during the dry development of the lower photosensitive film, so that the dry etching of the subsequent polysilicon film in the same equipment Can be carried out continuously in order to obtain advantages in the process.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
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| KR20000012850A (en) * | 1998-08-01 | 2000-03-06 | 윤종용 | Method for etching of semiconductor device |
| US6277736B1 (en) * | 1998-12-08 | 2001-08-21 | United Microelectronics, Corp. | Method for forming gate |
| JP2001237218A (en) * | 2000-02-21 | 2001-08-31 | Nec Corp | Method of manufacturing semiconductor device |
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| KR20000012850A (en) * | 1998-08-01 | 2000-03-06 | 윤종용 | Method for etching of semiconductor device |
| US6277736B1 (en) * | 1998-12-08 | 2001-08-21 | United Microelectronics, Corp. | Method for forming gate |
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