KR100440788B1 - Semiconductor package and its manufacturing method - Google Patents
Semiconductor package and its manufacturing method Download PDFInfo
- Publication number
- KR100440788B1 KR100440788B1 KR10-1999-0059346A KR19990059346A KR100440788B1 KR 100440788 B1 KR100440788 B1 KR 100440788B1 KR 19990059346 A KR19990059346 A KR 19990059346A KR 100440788 B1 KR100440788 B1 KR 100440788B1
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- semiconductor chip
- lead
- semiconductor
- adhesive tape
- semiconductor package
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 131
- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000002390 adhesive tape Substances 0.000 claims abstract description 37
- 230000017525 heat dissipation Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 claims description 11
- 229920005989 resin Polymers 0.000 claims description 11
- 238000000465 moulding Methods 0.000 claims description 4
- 230000000694 effects Effects 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000010030 laminating Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지 및 이것의 제조방법에 관한 것으로서, 반도체칩을 제1,2반도체 칩으로 적층하고, 또 반도체 패키지를 적층하여 사용할 수 있도록 함으로써 대용량이며 고집적화를 실현하는 동시에 마더보드에 대한 실장면적을 최소화로 실현할 수 있고, 반도체 칩의 저면과 리드의 일면등을 외부로 노출시킴에 따라 열방출효과를 극대화할 수 있으며, 접착테이프를 사용함에 따라 칩탑재판을 배제하여 칩의 두께와 무게를 줄이는 등의 효과를 얻을 수 있도록 한 반도체 패키지 및 이것의 제조방법을 제공하고자 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, wherein a semiconductor chip is laminated with first and second semiconductor chips, and a semiconductor package can be laminated and used, thereby realizing high capacity and high integration, and at the same time mounting area on a motherboard. Can be minimized and the heat dissipation effect can be maximized by exposing the bottom of the semiconductor chip and one side of the lead to the outside, and the thickness and weight of the chip can be reduced by eliminating the chip mounting plate by using adhesive tape. An object of the present invention is to provide a semiconductor package and a method of manufacturing the same.
Description
본 발명은 반도체 패키지 및 이것의 제조방법에 관한 것으로서, 더욱 상세하게는 고집적화된 메모리 반도체를 수용할 수 있도록 반도체 칩이 적층 부착되고, 동시에 마더보드 실장시 실장면적을 극소화하고자 패키지 자체를 적층하여 이루어진 구조의 반도체 패키지 및 이것의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, a semiconductor chip is laminated and attached to accommodate a highly integrated memory semiconductor, and at the same time, the package itself is laminated to minimize the mounting area when mounting the motherboard. A semiconductor package having a structure and a method of manufacturing the same.
통상적으로 반도체 패키지는 전자기기의 집약적인 발달과 소형화로 제조되는 경향으로 고집적화, 소형화, 고기능화의 추세에 병행하여, 상기 반도체 칩탑재판의 저면이 외부로 노출된 구조의 반도체 패키지, 솔더볼과 같은 인출단자를 포함하는 반도체 패키지, 리드프레임, 인쇄회로기판, 필름등의 부재를 이용한 반도체 패키지등 다양한 종류의 패키지가 경박단소화로 개발되어 왔고, 개발중에 있다.In general, semiconductor packages tend to be manufactured by intensive development and miniaturization of electronic devices, and in parallel with trends of high integration, miniaturization, and high functionality, semiconductor packages having a structure in which the bottom surface of the semiconductor chip mounting board is exposed to the outside, such as solder balls, are drawn out. Various kinds of packages, such as semiconductor packages including terminals, lead frames, printed circuit boards, and semiconductor packages using members such as films, have been developed in light and short size and are being developed.
상기와 같은 통상적인 반도체 패키지보다 고집적화된 메모리 반도체를 수용하는 동시에, 마더보드 실장시 실장면적을 최소화할 수 있도록 한 반도체 패키지가 요구되어왔다.There has been a demand for a semiconductor package capable of accommodating more highly integrated memory semiconductors than the conventional semiconductor packages as described above and minimizing a mounting area when mounting a motherboard.
따라서, 본 발명은 상기와 같은 점을 감안하여 반도체 칩의 저면과 리드의 일면등을 외부로 노출시킴에 따라 열방출효과를 극대화할 수 있고, 접착테이프를 사용함에 따라 칩탑재판을 배제하여 칩의 두께와 무게를 줄이는등의 효과를 얻을 수 있으며, 고집적화된 메모리 반도체를 수용하는 동시에 마더보드 실장시 실장면적을 최소화할 수 있도록 반도체 칩이 상하 적층되고, 낱개의 반도체 패키지가 적층되어 이루어진 구조의 반도체 패키지와 이것의 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention can maximize the heat dissipation effect by exposing the bottom of the semiconductor chip and one side of the lead to the outside in consideration of the above point, and eliminates the chip mounting plate by using the adhesive tape It is possible to reduce the thickness and weight of the semiconductor chip.The semiconductor chip is stacked up and down, and the individual semiconductor packages are stacked so as to accommodate the highly integrated memory semiconductor and minimize the mounting area when mounting the motherboard. It is an object of the present invention to provide a semiconductor package and a method of manufacturing the same.
도 1a,1b는 본 발명에 따른 반도체 패키지의 일실시예를 나타내는 단면도,1A and 1B are cross-sectional views showing one embodiment of a semiconductor package according to the present invention;
도 2는 본 발명에 따른 반도체 패키지의 두번째 실시예를 나타내는 단면도,2 is a cross-sectional view showing a second embodiment of a semiconductor package according to the present invention;
도 3은 본 발명에 따른 반도체 패키지의 세번째 실시예를 나타내는 단면도,3 is a cross-sectional view showing a third embodiment of a semiconductor package according to the present invention;
도 4는 본 발명에 따른 반도체 패키지의 네번째 실시예를 나타내는 단면도,4 is a cross-sectional view showing a fourth embodiment of a semiconductor package according to the present invention;
도 5는 본 발명에 따른 반도체 패키지의 다섯번째 실시예를 나타내는 단면도,5 is a sectional view showing a fifth embodiment of a semiconductor package according to the present invention;
도 6은 본 발명에 따른 반도체 패키지의 여섯번째 실시예를 나타내는 단면도,6 is a cross-sectional view showing a sixth embodiment of a semiconductor package according to the present invention;
도 7은 본 발명에 따른 반도체 패키지의 일곱번째 실시예를 나타내는 단면도.7 is a sectional view showing a seventh embodiment of a semiconductor package according to the present invention;
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10a,10b,10c,10d,10e,10f,10g : 반도체 패키지10a, 10b, 10c, 10d, 10e, 10f, 10g: semiconductor package
12a,12b,12c,12d,12e : 리드프레임의 리드12a, 12b, 12c, 12d, 12e: lead of lead frame
14 : 제 1반도체 칩 16 : 제 2반도체 칩14: first semiconductor chip 16: second semiconductor chip
18 : 와이어 20 : 수지18: wire 20: resin
22 : 인출단자 24 : 접착테이프22: withdrawal terminal 24: adhesive tape
26 : 히트싱크26: heat sink
이하 첨부도면을 참조로 본 발명을 상세하게 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명의 반도체 패키지(10a,10b,10c,10d,10e,10f,10g)는 소정 면적의 접착테이프(24)와, 이 접착테이프(24)상에 부착되는 제 1반도체칩(14)과 일면상의 일부가 식각처리된 리드(12a,12b,12c,12d)와, 상기 제 1반도체칩(14)의 상면에 적층되어 부착되는 제 2반도체칩(16)과, 상기 제 1반도체칩(14)과 제 2반도체칩(16)의 본딩패드와 상기 리드(12a,12b,12c,12d)간에 연결되는 와이어(18)와, 상기 제 1반도체칩(14)과 제 2반도체칩(16)과 리드(12a,12b,12c,12d)와 와이어(18)등을 외부로부터 보호하기 위하여 몰딩된 수지(20)로 구성되되, 상기 제 1반도체칩(14)의 저면과 상기 리드(12a,12b,12c,12d)의 일면상의 일부가 외부로 노출되도록 상기 접착테이프(24)를 분리시켜 달성된 것을 특징으로 한다.The semiconductor packages 10a, 10b, 10c, 10d, 10e, 10f, and 10g of the present invention have an adhesive tape 24 having a predetermined area, and a first semiconductor chip 14 attached to the adhesive tape 24 on one surface thereof. Leads 12a, 12b, 12c, and 12d on which portions of the phase are etched, a second semiconductor chip 16 stacked on and attached to an upper surface of the first semiconductor chip 14, and the first semiconductor chip 14 And a wire 18 connected between the bonding pad of the second semiconductor chip 16 and the leads 12a, 12b, 12c, and 12d, the first semiconductor chip 14, the second semiconductor chip 16, and the lead. (12a, 12b, 12c, 12d) and a molded resin 20 to protect the wire 18 from the outside, wherein the bottom surface of the first semiconductor chip 14 and the leads 12a, 12b, 12c , 12d) is achieved by separating the adhesive tape 24 so that a portion on one side of the surface is exposed to the outside.
특히, 상기 반도체 패키지(12d,12f)는 접착테이프(24)를 분리시키지 않고, 접착테이프(24)의 저면에 열방출을 위한 히트싱크(26)를 부착시킨 것을 특징으로 한다.In particular, the semiconductor packages 12d and 12f are characterized in that the heat sink 26 for heat dissipation is attached to the bottom surface of the adhesive tape 24 without separating the adhesive tape 24.
또한, 상기 리드(12a)는 저면 바깥쪽이 식각처리된 구조이고, 상기 리드(12b)는 저면 안쪽과 바깥쪽이 식각처리된 구조이고, 상기 리드(12c)는 상면 안쪽이 식각처리된 구조이며, 상기 리드(12d)는 상면 안쪽과 바깥쪽이 식각처리된 구조이다.In addition, the lid 12a has a structure in which the outer side of the bottom is etched, the lid 12b has a structure in which the inside and the outside of the bottom are etched, and the lid 12c has a structure in which the inside of the top is etched. The lead 12d has a structure in which the inside and the outside of the upper surface are etched.
상기 반도체 패키지(10d,10e,10f,10g)의 리드(12c,12d)의 외부로 노출된 부분에는 인출단자(22)를 부착시킬 수 있다.A lead terminal 22 may be attached to a portion of the semiconductor packages 10d, 10e, 10f, and 10g exposed to the outside of the leads 12c and 12d.
또한, 상기 인출단자(22)를 포함하는 반도체패키지(10d,10e,10f,10g)는 하나 이상으로 적층시킬 수 있다.In addition, one or more semiconductor packages 10d, 10e, 10f, and 10g including the lead terminals 22 may be stacked.
상기와 같이 이루어진 본 발명의 반도체 패키지 제조방법은 접착테이프(24)상에 식각처리된 리드프레임의 리드(12a,12b,12c,12d)를 부착 고정시키는 단계와, 상기 접착테이프(24)의 중앙부에 제 1반도체 칩(14)을 부착시키는 단계와, 이 제 1반도체칩(14)상에 제 2반도체칩(16)을 적층 부착시키는 단계와, 상기 리드(12a,12b,12c,12d)와 제 1반도체칩(14)과 제 2반도체칩(16)을 와이어(18)로 연결하는 단계와, 상기 제 1반도체칩(14)과 제 2반도체칩(16)과 와이어(18)와 리드((12a,12b,12c,12d)를 외부로 부터 보호하기 위하여 수지(20)로 몰딩하는 단계와, 상기 제 1반도체칩(14)의 저면과 리드(12a,12b,12c,12d)의 일면이 외부로 노출되도록 상기 접착테이프(24)를 떼어내는 단계로 이루어진 것을 특징으로 한다.The semiconductor package manufacturing method of the present invention made as described above is a step of fixing and fixing the leads (12a, 12b, 12c, 12d) of the lead frame etched on the adhesive tape 24, the central portion of the adhesive tape 24 Attaching the first semiconductor chip 14 to the first semiconductor chip 14, laminating and attaching the second semiconductor chip 16 on the first semiconductor chip 14, and the leads 12a, 12b, 12c, and 12d. Connecting the first semiconductor chip 14 and the second semiconductor chip 16 with a wire 18, the first semiconductor chip 14, the second semiconductor chip 16, the wire 18 and the lead ( Molding (12a, 12b, 12c, 12d) with resin 20 to protect it from the outside, and the bottom surface of the first semiconductor chip 14 and one surface of the leads 12a, 12b, 12c, 12d Characterized in that the step of removing the adhesive tape 24 to be exposed to the outside.
특히, 상기 접착테이프(24)를 떼어내지 않은 상태에서 접착테이프(24)에 열방출을 위한 히트싱크(26)를 부착시키는 단계를 진행시킬 수 있다.In particular, the step of attaching the heat sink 26 for heat dissipation to the adhesive tape 24 in a state where the adhesive tape 24 is not removed.
또한, 상기 리드(12c,12d)의 외부로 노출된 부분에는 입출력수단으로서 인출단자(22)를 부착시키는 단계를 진행시킬 수 있다.In addition, the step of attaching the lead terminal 22 as an input / output means to the part exposed to the outside of the leads (12c, 12d).
또한, 상기 접착테이프(24)를 떼어내어 인출단자(22)가 부착되어진 반도체 패키지를 적층되게 부착시키는 단계가 진행될 수 있다.In addition, the adhesive tape 24 may be peeled off to attach the semiconductor package to which the drawing terminal 22 is attached.
여기서 본 발명의 일실시예를 첨부한 도 1a,1b를 참조로 설명하면 다음과 같다.Referring to Figures 1a, 1b attached to an embodiment of the present invention as follows.
도 1a에 도시한 바와 같이, 상기 반도체패키지(10a)는 소정 면적의 접착테이프(24)에 리드프레임의 리드(12a)를 부착 고정시키는 바, 상기 리드(12a)는 안쪽단 일부를 제외하고 저면 바깥쪽이 식각처리된 구조이다.As shown in FIG. 1A, the semiconductor package 10a attaches and fixes the lead 12a of the lead frame to an adhesive tape 24 having a predetermined area. The lead 12a has a bottom surface except a part of an inner end thereof. The outer side is etched structure.
또한, 상기 접착테이프(24)의 중앙부에는 제 1반도체칩(14)이 부착되어지며, 이 제 1반도체칩(14)의 상면에 보다 작은 크기의 제 2반도체칩(16)이 적층되어 부착되어진다.In addition, a first semiconductor chip 14 is attached to the center portion of the adhesive tape 24, and a second semiconductor chip 16 having a smaller size is stacked and attached to an upper surface of the first semiconductor chip 14. Lose.
상기 제 1반도체칩(14)과 제 2반도체칩(16)을 서로 부착되게 하는 방법은 서로 다른 크기로 소잉된 반도체 칩을 부착하는 방법이 있고, 또는 낱개로 소잉된 반도체칩을 접착수단을 부착시킨 웨이퍼상의 각각의 반도체칩에 부착하는 방법이 있다.The method of attaching the first semiconductor chip 14 and the second semiconductor chip 16 to each other may be a method of attaching a sawed semiconductor chip to a different size, or attaching a bonding means to a single sawed semiconductor chip. There is a method of adhering to each semiconductor chip on the wafer.
상기와 같이 부착 고정된 리드(12a)와 상기 제 1반도체칩(14)간을, 또 상기 리드(12a)와 제 2반도체칩(16)간을 와이어(18)로 연결시키게 된다.The wire 12 is connected between the lead 12a and the first semiconductor chip 14 attached and fixed as described above, and between the lead 12a and the second semiconductor chip 16.
다음으로, 상기 제 1,2반도체칩(14,16)과 와이어(18)와 리드(12a)의 상면 일부를 외부로부터 보호하기 위하여 수지(20)로 몰딩을 하게 된다.Next, in order to protect a part of the upper surface of the first and second semiconductor chips 14 and 16, the wire 18, and the lead 12a from the outside, the resin 20 is molded.
상기 몰딩후에, 상기 접착테이프(24)를 떼어내게 되는데, 접착테이프(24)의 분리와 동시에 상기 제 1반도체칩(14)의 저면과 상기 리드(12a)의 저면과 리드(12a)의 바깥쪽 상면 일부가 외부로 노출되어진다.After the molding, the adhesive tape 24 is peeled off. At the same time as the adhesive tape 24 is separated, the bottom surface of the first semiconductor chip 14 and the bottom surface of the lid 12a and the outside of the lid 12a are removed. Part of the upper surface is exposed to the outside.
좀 더 상세하게는, 상기 리드(12a)의 저면 노출부위는 마치 밑으로 돌출된 돌기와 같이 형성된 부위 즉, 식각처리되지 않은 안쪽단 저면부가 된다.More specifically, the bottom exposed portion of the lid 12a may be a portion formed like a protrusion projecting downward, that is, an inner bottom surface portion which is not etched.
따라서, 반도체 칩(14,16)에서 발생되는 열이 외부로 노출된 상기 제 1반도체칩(14)의 저면과 리드(12a)의 노출면으로 용이하게 빠져나가게 되고, 반도체칩을 이중으로 적층 구성함에 따라 보다 고집적화를 실현할 수 있게 된다.Therefore, heat generated in the semiconductor chips 14 and 16 is easily escaped to the bottom surface of the first semiconductor chip 14 exposed to the outside and the exposed surface of the lead 12a, and the semiconductor chips are stacked in a double configuration. As a result, higher integration can be realized.
첨부한 도 1b의 반도체 패키지는 도 1a의 반도체 패키지와 그 구조는 유사하나, 리드(12a)의 상면이 노출되게 수지(20)가 몰딩되어져 있고, 접착테이프(24)를 리드(12a)의 저면 노출부위만 떼내어 그 자리에 인출단자(22)를 부착시킨 구조로 된 것이다. 또한, 도 1b의 반도체 패키지는 리드(12a)가 엇갈리게 형성되어져 리드(12a)의 거리가 넓어짐에 따라 리드간의 쇼트등을 방지할 수 있다.The semiconductor package of FIG. 1B is similar in structure to that of FIG. 1A, but the resin 20 is molded so that the top surface of the lead 12a is exposed, and the adhesive tape 24 is attached to the bottom surface of the lead 12a. Only the exposed part is removed, and the withdrawal terminal 22 is attached in place. In addition, in the semiconductor package of FIG. 1B, as the leads 12a are alternately formed, the short between the leads can be prevented as the distance of the leads 12a increases.
여기서 첨부한 도 2를 참조로 본 발명에 따른 반도체 패키지의 두번째 실시예를 설명한다.A second embodiment of a semiconductor package according to the present invention will now be described with reference to FIG. 2.
도 2에 도시한 바와 같은 반도체 패키지(10b)는 상술한 도 1a의 반도체 패키지(10a)와 동일한 구조로 이루어져 있되, 리드와 몰딩 구조가 다르다.The semiconductor package 10b as shown in FIG. 2 has the same structure as the semiconductor package 10a of FIG. 1A described above, but has a different structure from the lead.
상기 반도체 패키지(10b)의 리드(12b)는 식각처리부위가 저면 안쪽과 바깥쪽이 되어, 중간부분의 식각처리되지 않은 부위가 밑으로 돌출된 식으로 형성되고, 그 저면이 외부로 노출되어진다.The lead 12b of the semiconductor package 10b is formed in such a manner that the etched portions are inward and outward of the bottom surface, and the unetched portions of the middle portion protrude downward, and the bottom surface thereof is exposed to the outside. .
또한, 리드(12b)의 몰딩수지와의 결합력을 높이기 위하여 리드(12b)의 상면 전체를 수지(20)로 몰딩하는 동시에 리드(12b)의 돌출된 중간부분 저면(식각면적이 증대된 상태)만이 노출되고 그 양쪽으로는 수지(20)가 몰딩되어져, 리드(12b)는 수지와 락킹되는 효과가 있어 결합력을 증대시킬 수 있게 된다.In addition, in order to increase the bonding force of the lid 12b with the molding resin, the entire upper surface of the lid 12b is molded with the resin 20 and at the same time, only the bottom surface of the protruding middle portion of the lid 12b (the etched area is increased). Exposed and the resin 20 is molded on both sides, the lead 12b has the effect of locking with the resin can increase the bonding force.
여기서 첨부한 도 3을 참조로 본 발명에 따른 반도체 패키지의 세번째 실시예를 설명하면 다음과 같다.A third embodiment of the semiconductor package according to the present invention will now be described with reference to the accompanying FIG. 3.
마찬가지로 첨부한 도 3의 반도체 패키지(10c)는 단지 리드프레임의 리드의 구조가 다른 것으로서, 리드(12c)의 상부면 안쪽 일부가 식각처리된 구조로 되어 있고, 접착테이프(24)를 떼어냄에 따라 상기 리드(12c)의 저면과 바깥쪽면이 외부로 노출되어져 열방출을 보다 극대화시킬 수 있다.Similarly, the semiconductor package 10c shown in FIG. 3 has only a structure of a lead of the lead frame, and a part of the upper surface of the lead 12c is etched to remove the adhesive tape 24. Accordingly, the bottom and the outer surface of the lead 12c are exposed to the outside to maximize heat dissipation.
여기서 첨부한 도 4를 참조로 본 발명에 따른 반도체 패키지의 네번째 실시예를 설명하면 다음과 같다.A fourth embodiment of the semiconductor package according to the present invention will now be described with reference to the accompanying FIG. 4.
도 4에 도시된 반도체 패키지(10d)는 접착테이프(24)를 분리시키지 않고, 리드(12c)의 상면(상면 안쪽부위가 식각처리됨에 따라 상부로 돌출된 식으로 형성된 부위)이 외부로 노출되도록 한 패키지로서, 상기 리드(12c)의 상면에 솔더볼과 같은 인출단자(22)가 부착되고, 상기 접착테이프(24)의 저면에는 열방출수단인 히트싱크(26)되어 달성된 것이다.The semiconductor package 10d shown in FIG. 4 does not separate the adhesive tape 24, and the upper surface of the lid 12c (a portion formed in a manner protruding upward as the upper inner portion is etched) is exposed to the outside. As one package, a lead terminal 22, such as a solder ball, is attached to an upper surface of the lead 12c, and a heat sink 26, which is a heat dissipation means, is achieved on the bottom surface of the adhesive tape 24.
여기서 첨부한 도 5를 참조로 본 발명에 따른 반도체 패키지의 다섯번째 실시예를 설명하면 다음과 같다.A fifth embodiment of the semiconductor package according to the present invention will now be described with reference to the accompanying FIG. 5.
도 5에 도시된 반도체 패키지(10e)는 리드(12d)의 구조가 상면 안쪽과 바깥쪽, 또는 상면 바깥쪽이 식각처리된 구조로서, 리드(12d)의 중간부위 즉 식각처리되지 않고 마치 위로 돌출된 부위가 외부로 노출되고, 또한 접착테이프(24)를 떼어냄에 따라 제 1반도체 칩(14)의 저면과 리드(12d)의 저면이 외부로 노출되어진다.The semiconductor package 10e shown in FIG. 5 is a structure in which the structure of the lead 12d is etched on the inside and the outside of the top surface or the outside of the top surface, and protrudes upward from the middle portion of the lead 12d, that is, not etched. The exposed portion is exposed to the outside, and as the adhesive tape 24 is removed, the bottom of the first semiconductor chip 14 and the bottom of the lid 12d are exposed to the outside.
또한, 상기 반도체 패키지(10e)는 리드(12d)의 외부로 노출된 상면에는 솔더볼과 같은 인출단자(22)가 부착되어져 달성된 패키지이고, 상하로 적층시켜 사용할 수 있는 바, 상부쪽에 위치하는 반도체패키지(10e)의 인출단자(22)와 하부쪽 반도체패키지(10e)의 외부로 노출된 리드(12d)면이 부착되어져 2중 구조의 반도체 패키지로 사용할 수 있게 된다.In addition, the semiconductor package 10e is a package achieved by attaching a lead terminal 22, such as a solder ball, to an upper surface exposed to the outside of the lead 12d. The semiconductor package 10e can be stacked vertically and used. The lead terminal 22 of the package 10e and the lead 12d surface exposed to the outside of the lower semiconductor package 10e are attached to each other so that the semiconductor package of the double structure can be used.
여기서, 첨부한 도 6을 참조하여 본 발명에 따른 반도체 패키지의 여섯번째 실시예를 설명하면 다음과 같다.Herein, a sixth embodiment of a semiconductor package according to the present invention will be described with reference to FIG. 6.
도 6에 도시된 반도체 패키지(10f)는 도 5에 도시한 반도체패키지(10e)와 그 구조에서 동일하며, 단지 접착테이프(24)를 떼어내지 않고 접착테이프(24)의 저면에 히트싱크(26)를 부착시킴으로써 달성된다.The semiconductor package 10f shown in FIG. 6 is the same in structure as the semiconductor package 10e shown in FIG. 5, and the heat sink 26 is disposed on the bottom surface of the adhesive tape 24 without removing the adhesive tape 24 only. ) Is achieved.
여기서, 첨부한 도 7을 참조로 본 발명에 따른 반도체 패키지의 일곱번째 실시예를 설명하면 다음과 같다.Herein, a seventh embodiment of a semiconductor package according to the present invention will be described with reference to the accompanying FIG. 7.
도 7에 도시한 반도체 패키지(10g)는 도 5에 도시한 반도체 패키지와 그 구조에서 동일하나, 반도체 패키지의 두께에서 인출단자의 직경 정도만큼 다소 두꺼운 구조이고, 또 리드(12e)의 구조가 다른 바, 리드(12e)의 저면 안쪽과 바깥쪽이식각처리되고 또는 저면 바깥쪽이 식각처리된 구조이다.The semiconductor package 10g shown in FIG. 7 is the same in structure as the semiconductor package shown in FIG. 5, but is somewhat thicker than the diameter of the lead terminal in the thickness of the semiconductor package, and the structure of the lead 12e is different. The inside and outside of the bottom of the lid 12e are etched or the outside of the bottom is etched.
따라서, 상기 리드(12e)의 식각처리 되지 않은 상면 전체가 외부로 노출되는 동시에 접착테이프(24)를 떼어냄에 따라 리드(12e)의 식각처리되지 않은 저면 중간부분이 외부로 노출되어진다.Accordingly, the entire unetched top surface of the lid 12e is exposed to the outside, and as the adhesive tape 24 is removed, the middle portion of the lid 12e which is not etched is exposed to the outside.
이때, 상기 반도체패키지(10g)는 접착테이프(24)를 떼어냄에 따라 외부로 노출된 리드(12e)의 저면 중간부분에 솔더볼과 같은 인출단자(22)가 부착함으로써 완성되고, 이렇게 완성된 반도체 패키지(10g)를 상하로 적층시켜 사용할 수 있는 바, 즉, 상부쪽 반도체 패키지(10g)의 인출단자(22)와 하부쪽 반도체패키지(10g)의 외부로 노출된 리드(10e) 상면을 서로 부착되게 하여, 2중 구조의 반도체패키지로 사용할 수 있게 된다.At this time, the semiconductor package 10g is completed by attaching a lead terminal 22, such as a solder ball, to the middle portion of the bottom surface of the lead 12e exposed to the outside as the adhesive tape 24 is removed. The package 10g may be stacked up and down, that is, the lead terminal 22 of the upper semiconductor package 10g and the upper surface of the lead 10e exposed to the outside of the lower semiconductor package 10g are attached to each other. As a result, it can be used as a semiconductor package of a double structure.
이상에서 본 바와 같이, 본 발명에 따른 반도체 패키지와 이것의 제조방법에 의하면, 반도체칩을 제1,2반도체 칩으로 적층하고, 또 반도체 패키지를 적층하여 사용할 수 있도록 함으로써 대용량이며 고집적화를 실현하는 동시에 마더보드에 대한 실장면적을 최소화로 실현할 수 있고, 반도체 칩의 저면과 리드의 일면등을 외부로 노출시킴에 따라 열방출효과를 극대화할 수 있으며, 접착테이프를 사용함에 따라 칩탑재판을 배제하여 칩의 두께와 무게를 줄이는등의 효과를 얻을 수 있는 장점이 있다.As described above, according to the semiconductor package and the manufacturing method thereof according to the present invention, the semiconductor chip is laminated with the first and second semiconductor chips, and the semiconductor package can be laminated and used to realize high capacity and high integration. The mounting area of the motherboard can be minimized, and the heat dissipation effect can be maximized by exposing the bottom of the semiconductor chip and one side of the lead to the outside, and the chip mounting plate is excluded by using the adhesive tape. This has the advantage of reducing the thickness and weight of the chip.
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| KR100444164B1 (en) * | 2001-12-27 | 2004-08-11 | 동부전자 주식회사 | multi chip semiconductor package |
| US8710675B2 (en) | 2006-02-21 | 2014-04-29 | Stats Chippac Ltd. | Integrated circuit package system with bonding lands |
| US8471374B2 (en) | 2006-02-21 | 2013-06-25 | Stats Chippac Ltd. | Integrated circuit package system with L-shaped leadfingers |
| US8692377B2 (en) | 2011-03-23 | 2014-04-08 | Stats Chippac Ltd. | Integrated circuit packaging system with plated leads and method of manufacture thereof |
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