KR100440476B1 - Method for fabricating semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In order to prevent dishing phenomenon and poor adhesion of wiring, a metal layer is grown from a metal seed layer to form wiring. In order to manufacture the semiconductor device according to the present invention, after forming an insulating film on the substrate on which the conductive layer is formed, holes are formed in the insulating film to expose the conductive layer. Subsequently, after forming a seed layer along the surface of the insulating film in which a hole is formed, the seed layer is polished until the insulating film is exposed. Next, a metal layer filling the hole from the seed layer is grown.

Description

Manufacturing Method of Semiconductor Device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a wiring forming method.

As semiconductor devices have been increasingly integrated and multilayered, multilayer wiring has emerged as one of the important technologies. In this multilayer wiring technology, a metal wiring layer and an insulating film are alternately formed on a semiconductor substrate on which a circuit element is formed, and separated by an insulating film. The circuit operation is performed by electrically connecting the metal wiring layers through the vias.

In addition, by applying the multi-layered wiring technology in the semiconductor device, cross wiring is possible, which improves the degree of freedom and integration degree in the circuit design of the semiconductor device, and also reduces the length of the wiring so that the speed of the wiring can be increased. By shortening the delay time, the operation speed of the semiconductor device can be improved. In addition, the line width of the metal wiring layer is gradually decreasing with the miniaturization of semiconductor elements.

One conventional technique for forming a multilayer wiring of a semiconductor device is to form a via hole exposing the lower wiring in an insulating film covering the lower wiring, and then deposit and planarize the upper wiring in contact with the lower wiring in the via hole.

However, in the manufacture of such a semiconductor device, when the metal wiring widths are different in the substrate, dishing phenomenon in which the wiring having a wider width is polished more than the wiring having a narrower width and the inner part of the wiring is recessed. This happens. In addition, there is a problem that after polishing of the metal wiring, the surface of the film becomes rough and the adhesion to the subsequent film is lowered.

The present invention is to prevent dishing phenomenon and poor adhesion of the wiring in the multilayer wiring structure of the semiconductor device.

1A to 1D are process diagrams for forming wiring in the manufacture of a semiconductor device according to an embodiment of the present invention.

In order to solve the technical problem, the present invention forms a wiring by growing a metal layer from the metal seed layer.

Specifically, in order to manufacture the semiconductor device according to the present invention, after forming an insulating film on the substrate on which the conductive layer is formed, holes are formed in the insulating film to expose the conductive layer. Subsequently, after forming a seed layer along the surface of the insulating film in which a hole is formed, the seed layer is polished until the insulating film is exposed. Next, a metal layer filling the hole from the seed layer is grown.

Here, the metal layer may be grown by electroplating, wherein the metal layer may be a copper layer. After the seed layer is polished, heat treatment may be performed.

In this case, the hole may include a via hole exposing the conductive layer and a trench positioned on the via hole, and the metal layer may include a via filling the via hole and a wiring filling the trench. In addition, a high melting point metal film of CoN, TiN, TaN can be formed under the seed layer, and the thickness of the high melting point metal film can be 50 kPa to 300 kPa.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1A to 1D show a process diagram for forming a wiring in the manufacture of a semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1A, an insulating film 20 and a lower metal wiring 30 are formed on a semiconductor substrate 10. In this case, an electric element such as a transistor or a wiring may be formed under the insulating film 20, but the description thereof is omitted in the exemplary embodiment of the present invention. In addition, the lower metal wiring 30 may be a wiring connected to the junction region or the junction region of the transistor.

Subsequently, an interlayer insulating film 40 covering the lower metal wiring 30 and the insulating film 20 is deposited by an oxide film or the like, and then the interlayer insulating film 40 is planarized by chemical mechanical polishing.

Subsequently, a via hole 44 exposing the lower metal wiring 30 and a trench 45 positioned on the via hole 44 are formed in the interlayer insulating layer 40 through a photolithography process.

In order to form the via holes 44 and the trench 45, a first photoresist pattern (not shown) defining the via holes 44 is formed on the interlayer insulating film 40, and then the photoresist pattern is used as a mask. The interlayer insulating film 40 is etched to expose the lower metal wiring 30. Subsequently, a second photosensitive film pattern (not shown) defining the trench 45 is formed on the interlayer insulating film 40, and then the upper portion of the interlayer insulating film 40 is etched using the photosensitive film pattern as a mask. . At this time, the etching operation that proceeds using the first photosensitive film pattern and the etching operation that proceeds using the second photosensitive film pattern may be performed in reverse order.

Next, as shown in FIG. 1B, a copper layer is formed on the surface of the interlayer insulating film 40 on which the via holes 44 and the trench 45 are formed, and on the upper surface of the upper metal wiring 30 exposed through the via holes 44. For this purpose, the seed layer 50 is thinly deposited with Cu, Pd (palladium), or the like to a thickness of 1000 Å or less. At this time, before depositing the seed layer 50, a high melting point metal film such as CoN, TiN, TaN, or the like may be deposited to a thickness of 50 to 300 GPa.

Next, as shown in FIG. 1C, the seed layer 50 is removed by chemical mechanical polishing or etch back until the interlayer insulating film 40 is exposed. As a result, the seed layer 50 has a pattern shape located along side surfaces of the via hole 44 and the trench 45 in the interlayer insulating film 40.

Here, in order to remove moisture remaining on the seed layer 50 during the etching process by the chemical mechanical polishing method, it is preferable to perform a heat treatment. At this time, the heat treatment may be performed at 200 to 500 ℃ for 1 to 3 hours.

Next, as shown in FIG. 1D, copper is selectively grown from the seed layer 50 by electroplating to form a copper layer 62 filling the via hole 44 and the trench 45. At this time, the copper layer portion filling the via hole 44 becomes a via, and the copper layer portion filling the trench 45 becomes an upper metal wiring.

In order to perform such electrolytic plating, an electrochemical cell must be constructed. The electrochemical cell includes an electrode (cathode and anode), an electrolyte for copper plating, and a power supply device. After the electrochemical cell is constructed, the substrate on which the metal seed layer 50 is formed is maintained as a cathode to uniformly electroplat copper on the surface of the seed layer 50 to form the copper layer 62. Subsequently, in order to improve the adhesion between the seed layer 50 and the copper layer 62, it is preferable to proceed the heat treatment within 3 hours at 100 to 450 ° C. At this time, when the heat treatment temperature is increased, the size of the copper particles constituting the copper layer 62 can be increased. However, when the size of the particles constituting the copper layer is increased, the self-resistance value of the copper layer 62 is reduced. There is this. The copper layer 62 formed by such an electroplating method is not rough in the surface thereof, so that the adhesive force with the subsequent film does not decrease.

Here, before the copper layer 62 is grown, the substrate is subjected to a heat treatment for 30 seconds to 5 minutes in the range of 200 to 500 ° C., or after such heat treatment, sputtering using an inert gas is performed on the seed layer 50. It is desirable to remove the native oxide film.

As described above, the present invention can form a wiring existing in the via hole or the trench without using a chemical mechanical polishing process through the electroplating method. In particular, in the present invention, since the metal layer is grown by the electroplating method, wirings for filling holes having different widths can be formed at the same time.

Subsequently, a metal protective film (not shown) covering the copper layer 62 may be formed to improve durability of the copper layer 62. At this time, the metal protective film is preferably formed of a high melting point metal material.

In the present invention, since the polishing operation is not performed, dishing on the surface of the wiring and poor adhesion to the subsequent film generated during the polishing of the wirings having different widths can be prevented.

Claims (8)

Forming an insulating film on the substrate on which the conductive layer is formed, Forming a hole in the insulating layer to expose the conductive layer; Forming a seed layer along a surface of the insulating film on which the hole is formed; Performing a heat treatment after removing the seed layer by polishing until the insulating layer is exposed; Growing a metal layer filling the hole from the seed layer Method for manufacturing a semiconductor device comprising a. In claim 1, The metal layer is a semiconductor device manufacturing method of growing by the electroplating method. In claim 1, The metal layer is a copper layer manufacturing method of a semiconductor device delete In claim 1, And growing the metal layer, and then performing heat treatment. In claim 1, The hole includes a via hole exposing the conductive layer and a trench positioned on the via hole. And the metal layer comprises a via filling the via hole and a wiring filling the trench. In claim 1, And forming a high melting point metal film of CoN, TiN, TaN under the seed layer. In claim 7, The high melting point metal film has a thickness of 50 kPa to 300 kPa.