KR100431739B1 - Method of forming capacitor in memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a capacitor of a semiconductor device. In the deposition of a sacrificial layer, a first step is to deposit an undoped sacrificial layer, and a second is to deposit a doped oxide layer, which is doped by a subsequent thermal process. By inhibiting the growth of MPS by converting undoped polysilicon near the top of the polysilicon lower electrode into doped polysilicon by diffusion of dopants in the oxide film Production yield can be increased by preventing the deterioration of the capacitor value itself caused by short circuit between capacitors and CD (Critical Dimension).

Description

METHODS OF FORMING CAPACITOR IN MEMORY DEVICE

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the density of dynamic random access memory (DRAM) of semiconductor memory devices increases, the area of a memory cell that stores one bit, which is a basic unit of memory information, is decreasing. However, it is not possible to reduce the area of the capacitor in proportion to the shrinking of the cell, which is necessary for sensing signal margin, sensing speed, and durability against soft errors caused by α-particles. This is because a certain charging capacity is required per unit cell. Therefore, the method for maintaining the capacity (C) of the memory capacitor in the limited cell area more than the appropriate value is the first dielectric thickness (d), such as C = ε As / d (ε: dielectric constant, As: surface area, d: dielectric thickness) The second method is to increase the effective surface area (As) of the capacitor, and the third method is to use a material having a high dielectric constant (ε).

The third case in detail is as follows. Conventional dielectric films used in capacitors have been mainly made of a thin film of NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) using Si ₃ N ₄ , which has a dielectric constant almost doubled from SiO ₂ . However, because SiO ₂ , Nitride-Oxide (NO), and Oxide-Nitride-Oxide (ONO) thin films have a low dielectric constant, there is no room for high capacitance even if the thickness of the dielectric thin film is reduced or the surface area is increased. The situation led to the introduction of new materials. As a result, high-density DRAM introduces dielectric thin films such as (Ba, Sr) TiO ₃ (hereinafter referred to as BST), (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), and Ta ₂ O ₅ as materials to replace existing dielectric films. It was. Among them, the Ta ₂ O ₅ dielectric thin film has a dielectric constant of about 20 to 25 times higher than that of silicon nitride and is easier to etch than BST or PZT. In addition, the step coverage is excellent when deposited by chemical vapor deposition (CVD). On the other hand, TaON has been recently developed to improve the unstable stoichiometric ratio of Ta ₂ O ₅ .

As described above, in the capacitor using Ta ₂ O ₅ or TaON having a high dielectric constant as the dielectric film, the selection of the electrode material greatly affects the characteristics of the ferroelectric. That is, in the case of using Ta ₂ O ₅ or TaON as a dielectric film, unlike a conventional NO-nitride (NO) capacitor, it is based on a MIS structure. Where M represents a metal electrode used as a plate node, I represents a dielectric that is an insulator, and S represents polysilicon used as a storage node. The plate electrode, which is the upper electrode of the Ta ₂ O ₅ capacitor, has a laminated structure of polysilicon / TiN or polysilicon / WN. The storage electrode, which is a lower electrode, uses polysilicon whose surface is treated with Rapid Thermal Nitration (RTN).

1A to 1D are cross-sectional views of capacitor formation of a MIS structure according to the prior art.

1A is a cross-sectional view of a storage node hole formation of a capacitor according to the prior art.

After the interlayer insulating layer 105 is formed on the semiconductor substrate 100, a contact hole is formed through the interlayer insulating layer to be connected to an active region (not shown) of the semiconductor substrate. The contact hole is filled with polysilicon, a silicide layer, and a barrier layer to form a conductive plug 110. Next, a sacrificial layer is formed to form a storage node of the concave capacitor, and the upper portion corresponding to the conductive plug 110 is selectively etched to form the storage node hole 113 and the sacrificial layer pattern 115a.

1B is a cross-sectional view of forming a polysilicon lower electrode conductive layer 140 in which MPS is grown according to the prior art.

First, doped polysilicon 130 is deposited. Next, an undoped polysilicon is deposited, and a polysilicon 135 having MPS grown is grown by growing metastable polysilicon (MPS) having an uneven embossed shape on the polysilicon. Form. The MPS structure is to increase the effective surface area of the capacitor.

1C is a cross-sectional view of a lower electrode pattern 140a formed by separating a lower electrode according to the related art.

In order to separate the lower electrode, a sacrificial layer having a sufficient thickness is formed on the resultant in which the lower electrode conductive layer is deposited to completely fill the inside of the storage node hole. The sacrificial layer may be formed of a photoresist film or an oxide film. Subsequently, a portion of the lower electrode conductive layer and a portion of the sacrificial layer are removed by etch back or chemical mechanical polishing (hereinafter referred to as CMP) until the upper surface of the interlayer insulating film is exposed, thereby removing a plurality of lower electrode conductive layers. The lower electrode of the pattern is separated. The lower electrode pattern 140a includes a doped polysilicon pattern 130a and a polysilicon pattern 135a in which MPS is grown.

1D is a cross-sectional view of forming the dielectric film 145 and the upper electrode 150 according to the prior art.

Ta ₂ O ₅ or TaON is used as the dielectric film, and the upper electrode has a laminated structure of polysilicon / TiN or polysilicon / WN.

As described above, methods that have been performed to increase the capacitance of a capacitor of a Ta ₂ O ₅ or TaON having a conventional MIS structure have a rugged structure to increase the height of the capacitor or increase the surface area of the polysilicon. Methods of growing metastable polysilicon of phosphorus-embossed shapes are used. However, in using the method of forming the MPS structure to increase the capacitance of the capacitor, when the MPS structure is overgrown, there is a part that cannot be separated between the electrodes, which is due to the dual bit failure in the subsequent evaluation of the electrical characteristics. Bit Fail). In order to prevent this, CMP is used for separation, which also causes a problem of causing a single bit failure when the MPS fragment is not removed from the lower electrode.

In addition, when the CD (Critical Dimension) near the upper portion of the capacitor is small, there is a problem in that the upper electrode of the capacitor is blocked when the MPS grows, so that the upper electrode cannot be filled, thereby lowering the yield.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a capacitor and a capacitor electrode which can prevent a short circuit between capacitors and increase a yield.

Figure 1a is a cross-sectional view of the storage node hole formation according to the prior art,

1B is a cross-sectional view of forming a polysilicon lower electrode conductive layer in which MPS is grown according to the prior art;

Figure 1c is a cross-sectional view of the lower electrode pattern formation according to the prior art,

1D is a cross-sectional view of forming a dielectric film and an upper electrode according to the prior art;

2A is a cross-sectional view of the storage node hole formation according to the present invention;

Figure 2b is a cross-sectional view of the lower electrode conductive layer formed of the capacitor according to the present invention,

Figure 2c is a cross-sectional view of the MPS grown according to the present invention,

2D is a cross-sectional view of the dielectric film and the upper electrode formed according to the present invention;

* Explanation of symbols for the main parts of the drawings

200: semiconductor substrate 225a: sacrificial film pattern

230: first polysilicon 235: second polysilicon

235c Polysilicon with MPS

Capacitor manufacturing method of the present invention for achieving the above object comprises the steps of: forming an undoped sacrificial film on a semiconductor substrate; Forming a doped sacrificial layer on the undoped sacrificial layer; Selectively etching the undoped sacrificial layer and the doped sacrificial layer to form a plurality of capacitor holes; Stacking doped polysilicon and undoped polysilicon on the entire surface of the substrate including the capacitor hole, the undoped sacrificial layer and the doped sacrificial layer; Diffusing a dopant of the doped sacrificial layer through a thermal process to convert only the undoped polysilicon positioned around the doped sacrificial layer into doped polysilicon among the doped sacrificial layers; Growing an MPS structure on polysilicon remaining in an undoped state; And etching the polysilicon to perform inter-electrode separation.

The present invention deposits the sacrificial film in two steps, firstly depositing the undoped sacrificial film and secondly depositing the doped sacrificial film. Subsequent thermal processing converts the undoped polysilicon near the top of the capacitor into doped polysi licon by diffusion of dopants in the doped sacrificial layer by subsequent thermal processes. By suppressing the growth of the MPS, the production yield can be increased by preventing the short-circuit between the capacitors and the deterioration of the capacitor value itself generated as the CD (critical dimension) becomes smaller.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A-2D are embodiments according to the present invention.

2A is a cross-sectional view illustrating the formation of the storage node hole 213 according to the present invention.

After the interlayer insulating layer 205 is formed on the semiconductor substrate 200, a contact hole is formed through the interlayer insulating layer to be connected to an active region (not shown) of the semiconductor substrate. The contact hole is filled with polysilicon, a silicide layer, and a barrier layer to form a conductive plug 210.

Next, a sacrificial layer is formed to form a storage node of the concave capacitor. The sacrificial layer includes a lower undoped sacrificial layer and an upper doped sacrificial layer.

In the method of forming a sacrificial layer, an undoped sacrificial layer may be formed, and a doped oxide layer may be formed by implanting a dopant into the upper portion of the undoped sacrificial layer by ion implantation.

Alternatively, the non-doped first sacrificial layer may be deposited and the doped second sacrificial layer may be deposited. The doped second sacrificial layer may be formed of any one or a combination of PSG (Phospho-Silicate Glass), BPSG (Boro-Phospho-Silicate Glass), and BSG (Boro-Silicate Glass).

Next, the first and second sacrificial layers of a region corresponding to the conductive plug are selectively etched to form a storage node hole 213 and a sacrificial layer pattern 225a. The sacrificial layer pattern 225a includes the first sacrificial layer pattern 215a and the second sacrificial layer pattern 220a.

2B is a cross-sectional view of the lower electrode conductive layer 240 formed of the capacitor according to the present invention.

First, in order to form a lower electrode of the capacitor, a first doped polysilicon 230 and an undoped agent are formed on a structure in which the first sacrificial layer pattern 215a and the second sacrificial layer pattern 220a are stacked. 2 polysilicon (undoped polysilicon, 235) is formed by laminating in sequence. Here, the doped first polysilicon 230 serves as a conductor, and the undoped second polysilicon 235 serves as a seed in which MPS grows in the future. In addition, the undoped second polysilicon 235 may be divided into a portion 235b that is still doped and a portion 235b which is still undoped through a subsequent dopant diffusion process. Only the remaining parts will grow MPS.

As described above, the first polysilicon 230 and the second polysilicon 235 are stacked and deposited, and then a thermal process for diffusing dopants of the doped second sacrificial layer 220a is performed. That is, when an appropriate thermal process is applied, dopants inherent in the second sacrificial layer 220a start to diffuse into the surroundings, and as a result, as shown in FIG. 2B, the undoped covering the second sacrificial layer 220a is performed. A portion of the second polysilicon 235 is converted into doped polysilicon. That is, the undoped second polysilicon 235 is divided into a portion 235b and a doped portion 235a that remain undoped.

The top doped second polysilicon 235a then suppresses MPS on top of the polysilicon in the MPS process.

Figure 2c is a cross-sectional view of the growth of MPS according to the present invention.

MPS is grown to increase the effective area of the capacitor. At this time, as described above, the MPS does not grow in the second polysilicon 235a doped on the upper surface by diffusion of the dopant, and the second polysilicon in which the MPS grows in the second undoped second polysilicon is grown. (235c).

2D is a cross-sectional view of forming the dielectric film 245 and the upper electrode 250 according to the present invention.

After the second polysilicon 235c having the MPS is formed, the lower electrode pattern 240a is formed by separating the electrodes.

In order to separate the lower electrode, a sacrificial layer having a sufficient thickness is formed on the resultant in which the lower electrode conductive layer is deposited to completely fill the inside of the storage node hole. The sacrificial layer may be formed of a photoresist film or an oxide film. Subsequently, a portion of the lower electrode and a portion of the sacrificial layer are removed by an etch back or CMP method until the upper surface of the interlayer insulating film is exposed, thereby separating the lower electrode film into a plurality of lower electrodes.

The lower electrode pattern includes a doped first polysilicon pattern 230a, a second polysilicon 235c in which MPS is grown, and a doped second polysilicon pattern 235b.

Next, the dielectric film and the upper electrode conductive layer are formed and patterned to complete the capacitor.

The dielectric film 245 uses TaON or Ta ₂ O ₅ .

The upper electrode 250 uses a polysilicon / TiN or a polysilicon / WN stacked structure or a material selected from Pt, Ir, Ru, IrO _x , RuO _x , W, WN _x , and TiN.

In the above-described embodiment, a capacitor of a convex type is taken as an example, but may be used in various capacitor structures such as a cylinder structure and a multi-pin structure.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

According to the present invention, the sacrificial layer is deposited in two steps, and the dopant of the doped sacrificial layer is diffused to the upper portion of the second polysilicon lower electrode conductive layer, thereby selectively generating MPS in the second polysilicon upper region. In the upper region, it is possible to prevent overgrowth of the MPS structure at the source, so that electrode separation is easy, and there is an advantageous effect of eliminating the cause of bit defects caused by dropping of the MPS structure.

In addition, the yield is improved by solving the problem of lowering the capacitance value itself as the CD (Critical Dimension) value becomes smaller.

Claims (10)

Forming an undoped sacrificial layer on the semiconductor substrate; Forming a doped sacrificial layer on the undoped sacrificial layer; Selectively etching the undoped sacrificial layer and the doped sacrificial layer to form a plurality of capacitor holes; Stacking doped polysilicon and undoped polysilicon on the entire surface of the substrate including the capacitor hole, the undoped sacrificial layer and the doped sacrificial layer; Diffusing a dopant of the doped sacrificial layer through a thermal process to convert only the undoped polysilicon positioned around the doped sacrificial layer into doped polysilicon among the doped sacrificial layers; Growing an MPS structure on polysilicon remaining in an undoped state; And Etching the polysilicon to perform electrode-to-electrode separation Capacitor electrode manufacturing method comprising a. The method of claim 1, Forming the doped sacrificial layer on the undoped sacrificial layer, A method of manufacturing a capacitor electrode, characterized in that formed by implanting a dopant by ion implantation on top of the undoped sacrificial film. The method of claim 1, Forming the doped sacrificial layer on the undoped sacrificial layer, Capacitor electrode manufacturing method characterized in that formed by any one or a combination thereof selected from PSG, BPSG, and BSG. The method of claim 1, Etching the polysilicon to perform the inter-electrode separation, Forming a sacrificial layer over the polysilicon having a thickness sufficient to completely fill the interior of the hole; Separating the polysilicon into a plurality of electrodes by removing a portion of the polysilicon and a portion of the sacrificial layer until the top surface of the sacrificial layer is exposed; And Removing the remaining part of the sacrificial layer Electrode manufacturing method of a capacitor comprising a. The method of claim 4, wherein And the sacrificial layer is made of a photoresist film or an oxide film. delete delete delete delete delete