KR100424171B1 - Method of manufacturing flash mamory device - Google Patents

Abstract

The present invention discloses a method of manufacturing a flash memory device capable of preventing substrate damage in the peripheral circuit region and dielectric film damage in the cell region. The disclosed method includes forming a buffer oxide film over an entire region of a silicon substrate having a cell region and a peripheral circuit region, and forming a first photoresist pattern covering the peripheral circuit region on the buffer oxide film; Removing the buffer oxide layer on the cell region by etching using the first photoresist pattern, removing the first photoresist pattern, and conducting the tunnel oxide layer and the conductive layer on the buffer oxide layer of the cell region and the peripheral circuit region of the silicon substrate. Forming a film in sequence, forming a second photoresist pattern defining a floating gate formation region in the cell region on the conductive layer, and forming a floating gate in the cell region by etching using the second photoresist pattern And removing the conductive film on the peripheral circuit area, removing the second photoresist pattern, and the steps up to the step. Forming a dielectric film formed of an ONON film on the resultant, forming a third photoresist pattern covering the cell region on the dielectric film, and removing the dielectric film on the peripheral circuit region by etching using the third photoresist pattern. And removing the polymer oxide and the buffer oxide layer on the peripheral circuit region generated during the etching of the dielectric layer, and removing the third photoresist pattern.

Description

Manufacturing method of flash memory device {METHOD OF MANUFACTURING FLASH MAMORY DEVICE}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device that can prevent damage to the substrate in the peripheral circuit region and damage to the dielectric film in the cell region.

Flash memory devices are manufactured using the advantages of EPROM with programming and erasing characteristics and EEPROM with programming and erasing characteristics. . Such a flash memory device realizes a bit storage state as one transistor, and can be electrically programmed and erased.

Such a flash memory device, unlike a DRAM device, which preserves data only when power is supplied, has a characteristic of preserving data even when the power is cut off. ) Is divided into a low voltage region and a high voltage region to form a low voltage transistor and a high voltage transistor in each region, and a floating gate is formed in a cell region. In addition, since the data must be written and erased by the floating gate, a dielectric film needs to be formed. In this case, the dielectric film is formed in the cell region, but in a region other than the cell region, that is, the peripheral circuit region. It is not formed due to the driving by the transistor.

Here, in forming the dielectric film, in the manufacturing process of the 32M flash memory device having a class of 0.25 µm or less, the dielectric film forming process is performed with a gate oxide film of 80 kV and 160 kV formed in each of the low voltage region and the high voltage region of the peripheral circuit region. The dielectric film formed in the peripheral circuit region is subsequently removed so that the dielectric film is formed only in the cell region.

However, in the manufacturing process of the 64M and 128M flash memory devices of 0.18㎛ class or more, it is difficult to secure the area at the time of forming the wells due to the small cell area. Before forming the low voltage and high voltage regions, a dielectric film forming process is performed.

Hereinafter, a method of manufacturing 64M and 128M flash memory devices of 0.18 μm or more according to the prior art will be described with reference to FIGS. 1A to 1C.

First, as shown in FIG. 1A, a thin-film tunnel oxide film 2 is formed on the silicon substrate 1 in a state where a silicon substrate 1 having a cell region and a peripheral circuit region is provided. A floating gate conductive film, for example, a polysilicon film 3, is deposited on the tunnel oxide film 2. Subsequently, a first photoresist layer pattern 4 defining a floating gate is formed on the polysilicon layer formed in the cell region. At this time, the polysilicon film portion formed in the peripheral circuit region is exposed.

Next, as illustrated in FIG. 1B, the polysilicon layer is etched by a dry etching process using the first photoresist layer pattern to form a floating gate. Then, the first photoresist film pattern used as the etching mask is removed, wet etching is performed to remove polymer generated in this process, and then preliminary cleaning is performed as a pretreatment process for forming the dielectric film.

Here, when the polysilicon film 3 is etched, about 30 to 40% of the tunnel oxide film 2 formed in the peripheral circuit region is removed from the total thickness thereof, and some removal is also performed during wet etching for removing the polymer. Only 20 to 30% of the total thickness is retained, and completely removed during preliminary cleaning as the pretreatment step.

Subsequently, as shown in FIG. 1C, a dielectric film 5 made of an ONO film is deposited on the resultant up to the step, and then a second photoresist film is disposed so as to cover only a portion formed in the cell region on the dielectric film 5. The pattern 6 is formed. Then, the portion of the dielectric film in the exposed peripheral circuit area is removed by dry etching.

Subsequently, although not shown, after removing the second photoresist pattern formed on the cell region, a wet etching process using a BOE solution is performed to remove the polymer generated in this process, and then cleaning as a pretreatment process for the subsequent process. The process is performed. Thereafter, a well-known subsequent process is performed to manufacture a flash memory device.

However, the conventional method of manufacturing a flash memory device as described above has the following problems.

First, in the process of manufacturing a conventional 0.25M or less 32M flash memory device, the dielectric film forming process is performed in a state where a gate oxide film is formed in each of the low voltage region and the high voltage region of the peripheral circuit region. The gate oxide layer can prevent the attack, that is, damage of the silicon substrate during the dry etching of the dielectric layer, the wet etching for removing the polymer, and the precleaning process.

On the other hand, in the manufacturing process of 64M and 128M flash memory devices of 0.18㎛ or more, the dielectric film formed in the peripheral circuit region is removed since the process of the low voltage region and the high voltage region in the peripheral circuit region is performed after the dielectric film forming process is performed. In the dry etching process, excessive etching occurs to cause the silicon substrate to be attacked.

In addition, further damage of the silicon substrate occurs in the subsequent wet etching and preliminary cleaning process for the removal of the polymer, as well as the loss of the upper oxide layer in the dielectric layer in the cell region, that is, the ONO structure as well as the destruction of the nitride layer. ), Which results in deterioration of the leakage current and threshold voltage characteristics in the dielectric film.

2 and 3 are photographs for explaining a conventional problem, where FIG. 2 is a photo showing a polymer caused by hardening of the photosensitive film during dry etching of the dielectric film, and FIG. 3 is a dry etching of the dielectric film. This is a photo showing the attack of the silicon substrate caused by the excessive etching at the time. In addition, in FIG. 2, reference numeral A denotes a region where the photoresist film was formed, and B denotes a polymer generated when the photoresist film is removed. In FIG. 3, reference numeral 1 denotes a silicon substrate in which an attack is induced, and STI An isolation region is shown.

Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of preventing substrate damage in a peripheral circuit region and dielectric layer damage in a cell region.

1A to 1C are cross-sectional views illustrating a method of manufacturing a flash memory device according to the prior art.

FIG. 2 is a photograph showing a polymer caused by hardening of the photosensitive film during dry etching of the dielectric film. FIG.

Figure 3 is a photograph showing a state in which the attack of the silicon substrate caused by the excessive etching during the dry etching of the dielectric film.

4A to 4F are cross-sectional views illustrating a method of manufacturing a flash memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

11 silicon substrate 12 buffer oxide film

13: first photosensitive film pattern 14: tunnel oxide film

15 polysilicon film 16 second photosensitive film pattern

17 dielectric layer 18 third photoresist pattern

A method of manufacturing a flash memory device of the present invention for achieving the above object comprises the steps of: forming a buffer oxide film on the entire region of the silicon substrate having a cell region and a peripheral circuit region; Forming a first photoresist pattern covering the peripheral circuit region on the buffer oxide film; Removing the buffer oxide layer on the cell region by etching using the first photoresist pattern; Removing the first photoresist pattern; Sequentially forming a tunnel oxide film and a conductive film on a buffer oxide film of a cell region and a peripheral circuit region of the silicon substrate; Forming a second photoresist pattern defining a floating gate formation region in a cell region on the conductive layer; Forming a floating gate in a cell region by etching using the second photoresist pattern and simultaneously removing a conductive layer on a peripheral circuit region; Removing the second photoresist pattern; Forming a dielectric film of the ONON film on the substrate resultant up to this step; Forming a third photoresist pattern covering the cell region on the dielectric layer; Removing the dielectric film on the peripheral circuit region by etching using the third photoresist pattern; Removing the buffer oxide layer on the polymer and the peripheral circuit region generated during the etching of the dielectric layer; And removing the third photoresist pattern.

In the method of the present invention, the buffer oxide film is formed into an HTO film by using an LP-CVD process, and is formed to a thickness of 150 to 300 kPa.

According to the present invention, since the buffer oxide film is formed before the dielectric film forming step, it is possible to prevent the attack of the silicon substrate from being caused by the buffer oxide film. In addition, since the photoresist pattern is removed after the polymer is removed while changing the material of the dielectric film to the ONON structure, the loss of the dielectric film can be prevented.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention proceeds the process based on the following principle to prevent the attack caused to the silicon substrate during dry etching of the dielectric film, which is a conventional problem, and to prevent the dielectric film loss during polymer removal.

In the former case, before the dielectric film is formed, a buffer oxide film is formed on the peripheral circuit region of the silicon substrate to a predetermined thickness, for example, 150 to 300 microns thick, thereby causing attack of the substrate during dry etching of the subsequent dielectric film by the buffer oxide film. To prevent.

In the latter case, first, dry etching of the dielectric film is performed under conditions of low power and high pressure, and a low polymer process to minimize the generation of the polymer, and at the same time, The photoresist film is removed and wet etched while the dielectric film is removed, and the dielectric film is changed to the ONON structure to use the selectivity between the nitride film and the oxide film in the BOE and HF bath to prevent the loss of the dielectric film.

4A to 4D are cross-sectional views illustrating a method of manufacturing a flash memory device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 4A, a silicon substrate 11 having a cell region and a peripheral circuit region is provided, and on the entire surface of the silicon substrate 11, the silicon substrate 11 in a subsequent dielectric film forming process. In order to prevent the attack from occurring in the peripheral circuit area of the film, a buffer oxide film 12 made of an HTO film is formed to have a thickness of 150 to 300 Å using the LP-CVD process. Then, in order to operate the floating gate formed in the cell region at a low voltage, a cell open mask, that is, a first photoresist pattern 13, covering only the peripheral circuit region is formed on the buffer oxide layer 12.

Next, as shown in FIG. 4B, the buffer oxide film 12 formed in the cell region is removed by wet etching, which can suppress substrate damage, and then the first photoresist pattern used as an etching mask is removed. Then, a thin tunnel oxide film 14 is formed on the buffer oxide film 12 in the cell region and the peripheral circuit region of the exposed silicon substrate 11 to a thickness of 80 Å. At this time, the tunnel oxide film 14 is deposited in the cell region because the buffer oxide film 12 does not have all about 80 Å, and also as a gate oxide film to ensure the characteristics, while in the peripheral circuit region of the buffer oxide film 12 Due to their presence, only about 20-30 μs are deposited. That is, the tunnel oxide layer 14 is formed only 25 to 40% on the buffer oxide layer 12 on the peripheral circuit region to the thickness formed on the exposed cell region.

Then, as shown in FIG. 4C, a floating gate conductive film, for example, a polysilicon film 15 is deposited on the tunnel oxide film 14 in the cell region and the peripheral circuit region, and the polysilicon film 15 is deposited. A second photoresist pattern 16 defining a floating gate is formed thereon.

Next, as shown in FIG. 4D, the polysilicon layer 15 is etched using the second photoresist layer pattern 16 as an etching mask. At this time, the polysilicon film formed in the peripheral circuit region is etched away, thereby exposing the tunnel oxide film 14 in the peripheral circuit region.

Subsequently, as shown in FIG. 4E, in a state where the second photoresist pattern is removed, a dielectric film 17 including an ONON film is deposited on the resultant. In this case, the dielectric film 17 is changed to the ONON structure in order to secure the etching selectivity of the nitride film and the oxide film with respect to the BOE and HF solutions so that the loss of the dielectric film is suppressed. Subsequently, a third photoresist pattern 18 covering only the cell region is formed on the dielectric layer 17.

Next, as shown in FIG. 4F, the dielectric layer 14 in the exposed peripheral circuit region is dry-etched using the third photoresist layer pattern as an etching mask. In this case, in the dry etching of the dielectric layer 14, a low polymer generation process is performed under low voltage and high pressure to minimize hardening of the third photoresist film.

Subsequently, the buffer oxide layer including the polymer generated during the dry etching of the dielectric layer 14 and the tunnel oxide layer in the peripheral circuit region is removed by wet etching using a BOE or HF solution, and then the third photoresist pattern Remove it.

Thereafter, although not shown, a flash memory device according to the present invention is manufactured by performing a subsequent known process.

In the flash memory device of the present invention, which is manufactured through the process described above, the buffer oxide film is formed in the peripheral circuit region of the silicon substrate before the dielectric film forming process is performed, causing attack of the silicon substrate due to the excessive etching of the dielectric film. In addition, the control margin of the residual oxide film due to dry etching of the dielectric film can be secured, and thus, the process margin can be secured.

In addition, the formation of the buffer oxide layer may prevent the attack of the silicon substrate even during wet etching for removing the polymer. In particular, the buffer oxide layer may be removed together with the wet etching for removing the polymer, thus removing the buffer oxide layer. No further processing is necessary.

In addition, by changing the material of the dielectric film to the ONON structure, it is possible to prevent the loss of the dielectric film during the etching of the polymer and the deterioration of the characteristic of the dielectric film.

In addition, the tunnel oxide film deposited on the buffer oxide film can prevent the problem of further increasing the wet target during the etching of the buffer oxide film which is subsequently performed. The loss can be adjusted accurately.

As described above, the present invention can prevent the attack from occurring in the peripheral circuit region of the silicon substrate through the buffer oxide film by forming a buffer oxide film before performing the dielectric film forming process, and thus, in the peripheral circuit region The characteristics of the low voltage and high voltage transistors formed can be ensured.

In addition, according to the present invention, by changing the material of the dielectric film to the ONON structure, it is possible to prevent the loss of the dielectric film when the photoresist film is removed, thereby securing the gate characteristics and the device characteristics.

Therefore, by using the method of the present invention, a highly integrated flash memory device can be manufactured reliably.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (5)

Forming a buffer oxide film over the entire region of the silicon substrate having the cell region and the peripheral circuit region; Forming a first photoresist pattern covering the peripheral circuit region on the buffer oxide film; Removing the buffer oxide layer on the cell region by etching using the first photoresist pattern; Removing the first photoresist pattern; Sequentially forming a tunnel oxide film and a conductive film on a buffer oxide film of a cell region and a peripheral circuit region of the silicon substrate; Forming a second photoresist pattern defining a floating gate formation region in a cell region on the conductive layer; Forming a floating gate in a cell region by etching using the second photoresist pattern and simultaneously removing a conductive layer on a peripheral circuit region; Removing the second photoresist pattern; Forming a dielectric film of the ONON film on the substrate resultant up to this step; Forming a third photoresist pattern covering the cell region on the dielectric layer; Removing the dielectric film on the peripheral circuit region by etching using the third photoresist pattern; Removing the buffer oxide layer on the polymer and the peripheral circuit region generated during the etching of the dielectric layer; And And removing the third photoresist pattern. The method of claim 1, wherein the buffer oxide layer is formed of an HTO layer using an LP-CVD process. 2. The method of claim 1, wherein the buffer oxide film is formed to a thickness of 150 to 300 kHz. The method of claim 1, wherein the tunnel oxide layer is formed to have a thickness of 25 to 40% on the buffer oxide layer on the peripheral circuit region with respect to the thickness formed on the exposed cell region. delete