KR100419026B1 - Isolation method of semiconductor device - Google Patents
Isolation method of semiconductor device Download PDFInfo
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- KR100419026B1 KR100419026B1 KR1019960079869A KR19960079869A KR100419026B1 KR 100419026 B1 KR100419026 B1 KR 100419026B1 KR 1019960079869 A KR1019960079869 A KR 1019960079869A KR 19960079869 A KR19960079869 A KR 19960079869A KR 100419026 B1 KR100419026 B1 KR 100419026B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000002955 isolation Methods 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 229920000642 polymer Polymers 0.000 claims abstract description 13
- 150000004767 nitrides Chemical class 0.000 claims description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 238000004140 cleaning Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
본 발명은 반도체 소자의 소자분리 방법에 관한 것으로, 트랜치 식각시 질화막 식각공정에서 유도된, 즉 포토레지스트 패턴과 그 측벽에 형성된 측벽 폴리머의 잔류 상태에서 낮은 바이어스 파워의 식각조건하에서 트랜치 식각하여 한번의 메인 식각공정으로 저부의 모서리부분이 라운딩된 트랜치를 형성함으로써 종래의 메인 식각공정과 후처리 식각공정을 별도로 실시하는데 따른 제조공정 단계를 간소화시킬 수 있으며, 제조 공정시간을 단축시킬 수 있는 기술이다.The present invention relates to a device isolation method of a semiconductor device, wherein a trench is etched under a low bias power etching condition in a residual state of a photoresist pattern and a sidewall polymer formed on the sidewall of the trench. By forming a trench with rounded corners at the bottom of the main etching process, a manufacturing process step of separately performing a conventional main etching process and a post-treatment etching process can be simplified, and a manufacturing process time can be shortened.
Description
본 발명은 반도체 소자의 소자분리 방법에 관한 것으로, 특히 레지스트를 마스크로 하여 질화막을 식각하고, 레지스트 측벽 폴리머가 있는 상태에서 트랜치 식각하는 하나의 식각공정공정으로 저부가 라운딩된 트렌치를 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to a method of forming a bottom rounded trench in one etching process of etching a nitride film using a resist as a mask and trench etching in the presence of a resist sidewall polymer. will be.
반도체 소자가 점점 고집적화됨에 따라 트랜치 식각을 이용한 소자분리방법이 적용되고 있다.As semiconductor devices have been increasingly integrated, device isolation methods using trench etching have been applied.
특히, 디자인 룰(Design Rule)이 0.25㎛ 이하로 축소될 경우 트랜치 식각을 이용한 방법이 필수적으로 적용되고 있다.In particular, when the design rule is reduced to 0.25 μm or less, a method using trench etching has been applied.
도 1a 내지 도 1d 는 종래의 기술에 따른 반도체 소자의 소자분리 공정단계를 도시한 단면도이다.1A to 1D are cross-sectional views illustrating device isolation process steps of a conventional semiconductor device.
도 1a 를 참조하면, 실리콘 기판(10) 상부로 패드 산화막(13), 질화막(15)을 차례로 형성한다.Referring to FIG. 1A, a pad oxide film 13 and a nitride film 15 are sequentially formed on the silicon substrate 10.
다음, 상기 질화막 상부에 포토레지스트 패턴(17)을 형성한다.Next, a photoresist pattern 17 is formed on the nitride film.
도 1b 를 참조하면, 상기 포토레지스트 패턴(17)을 마스크로 하여 하부의 질화막(15)과 패드 산화막(13)을 차례로 식각한다.Referring to FIG. 1B, the lower nitride layer 15 and the pad oxide layer 13 are sequentially etched using the photoresist pattern 17 as a mask.
이때 상기 질화막(15) 식각후에는 질화막(15) 및 포토레지스트 패턴(17)의 측벽에 폴리머(19)가 잔류하게 된다.In this case, after etching the nitride film 15, the polymer 19 remains on sidewalls of the nitride film 15 and the photoresist pattern 17.
도 1c 를 참조하면, 상부의 포토레지스트 패턴(17)과 측벽에 형성된 잔류 폴리머(19)를 제거한다.Referring to FIG. 1C, the remaining photoresist pattern 17 and the residual polymer 19 formed on the sidewalls are removed.
도 1d 를 참조하면, 상기 질화막 패턴(15)을 식각 마스크로 하여 하부의 실리콘 기판(10)을 소정 깊이만큼 식각하여 트랜치(24)를 형성한다.Referring to FIG. 1D, the trench 24 is formed by etching the lower silicon substrate 10 by a predetermined depth using the nitride film pattern 15 as an etching mask.
이때, 상기 트랜치(24) 형성공정은 통상 고밀도 플라즈마 식각장비에서 수행되므로 대개는 트랜치(24) 하부 모서리부에서 마이크로 트랜치(23)가 형성된다.At this time, since the trench 24 forming process is usually performed in a high density plasma etching equipment, a micro trench 23 is generally formed at the lower edge portion of the trench 24.
또한 상기 생성된 마이크로 트랜치(23)를 제거하기 위하여 SF6플라즈마 공정을 추가하면 트랜치(24) 측면부에서 언더컷이 발생하게 된다. 여기서, 상기 마이크로 트랜치(23)를 근본적으로 제거하기 위해서, 상기 질화막 패턴(15)을 식각 마스크로 하여 하부 실리콘 기판(10)을 1차적으로 식각하는 메인 식각(Main Etch) 공정을 진행한 뒤, 2차적인 후처리 식각공정을 별도로 실시한다.In addition, when the SF 6 plasma process is added to remove the generated micro trench 23, an undercut is generated at the side surface of the trench 24. Here, in order to fundamentally remove the micro trench 23, after the main etching process is performed to primarily etch the lower silicon substrate 10 using the nitride film pattern 15 as an etching mask, Secondary post-treatment etching process is performed separately.
그러나 상기와 같은 종래의 트랜치(24) 형성은, 상기 실리콘 기판(10)을 식각하여 트랜치(24)를 형성하는 메인 식각공정과, 상기 메인 식각공정 이후 후처리 식각공정을 별도로 분리해서 실시되는 다단계(Multi-step) 공정으로 진행되기때문에 그 공정이 복잡하고 시간이 많이 소요되므로 반도체 소자 제조공정수율을 저하시키고 제품의 신뢰성을 저하시키는 문제점이 있다.However, the conventional trench 24 is formed as described above, in which the main etching process of etching the silicon substrate 10 to form the trench 24 and the post-process etching process after the main etching process are performed separately. Since the process is complicated and time-consuming because it is a multi-step process, there is a problem of lowering the semiconductor device manufacturing process yield and reducing the reliability of the product.
본 발명은 상기한 문제점을 해결하기 위한 것으로, 질화막 식각공정시 유도된 측벽 폴리머가 포토레지스트 패턴과 질화막 패턴의 측벽에 그대로 잔류한 상태에서 트랜치 식각공정을 진행함으로써 한번의 트랜치 식각공정으로 마이크로 트랜치가 생성되지 않으면서도 저부의 모서리 부분이 라운딩된 트랜치를 얻을 수 있도록 하여 반도체소자의 특성, 수율 및 신뢰성을 향상시킬 수 있도록 하는 반도체소자의 소자분리 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, micro trench is formed by one trench etching process by performing a trench etching process while the sidewall polymer induced during the nitride film etching process remains on the sidewalls of the photoresist pattern and the nitride film pattern. It is an object of the present invention to provide a device isolation method of a semiconductor device which can improve the characteristics, yield and reliability of the semiconductor device by obtaining a rounded trench at the bottom of the bottom without being generated.
도 1a 내지 도 1d 는 종래의 기술에 따른 반도체 소자의 소자분리 공정단계를 도시한 단면도1A to 1D are cross-sectional views illustrating device isolation process steps of a semiconductor device according to the related art.
도 2a 내지 도 2d 는 본 발명의 방법에 따른 반도체 소자의 소자분리 공정단계를 도시한 단면도2A to 2D are cross-sectional views illustrating device isolation process steps of a semiconductor device according to the method of the present invention.
＜ 도면의 주요부분에 대한 부호의 설명＞<Explanation of symbols for the main parts of the drawings>
10 : 실리콘 기판 13 : 패드 산화막10 silicon substrate 13 pad oxide film
15 : 질화막 17 : 포토레지스트 패턴15 nitride film 17 photoresist pattern
19 : 측벽 폴리머 21 : 바텀 라운딩부19 sidewall polymer 21 bottom rounding
23 : 마이크로 트랜치부 24,25 : 트랜치23: micro trench portion 24, 25: trench
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리 방법은,Device separation method of a semiconductor device according to the present invention to achieve the above object,
실리콘 기판 상부에 패드 산화막, 질화막 및 포토레지스트 패턴을 적층하는 단계와,Stacking a pad oxide film, a nitride film and a photoresist pattern on the silicon substrate;
상기 포토레지스트 패턴을 마스크로 하여 하부의 질화막과 패드 산화막을 식각하며 상기 질화막 및 패드산화막과 포토레지스트 패턴 측벽에 폴리머를 형성하는 단계와,Etching a lower nitride film and a pad oxide film using the photoresist pattern as a mask and forming a polymer on sidewalls of the nitride film and the pad oxide film and the photoresist pattern;
상기 포토레지스트 패턴 및 질화막을 마스크로 하여 사용전력이 50 ∼ 100 와트(watt)인 Cl2/N2혼합 가스 분위기의 고밀도 플라즈마 식각장비에서 상기 실리콘 기판을 식각함으로써 저부의 모서리부분이 라운딩된 트랜치를 형성하는 단계를 포함하는 것을 특징으로 한다.A trench with rounded corners is formed by etching the silicon substrate in a high density plasma etching apparatus in a Cl 2 / N 2 mixed gas atmosphere having a power of 50 to 100 watts using the photoresist pattern and the nitride film as a mask. It characterized by comprising the step of forming.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 소자분리 방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a device isolation method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d 본 발명의 방법에 따른 반도체 소자의 소자분리 제조 공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a device isolation fabrication process for semiconductor devices in accordance with the method of the present invention.
도 2a 를 참조하면, 실리콘 기판(10) 상부에 패드 산화막(13), 질화막(15)을 순차적으로 형성한다.Referring to FIG. 2A, a pad oxide film 13 and a nitride film 15 are sequentially formed on the silicon substrate 10.
다음, 상기 질화막 상부에 포토레지스트 패턴(17)을 형성한다.Next, a photoresist pattern 17 is formed on the nitride film.
도 2b 를 참조하면, 상기 포토레지스트 패턴(17)을 마스크로 하여 상기 질화막(15)과 패드 산화막(13)을 차례로 식각한다.Referring to FIG. 2B, the nitride film 15 and the pad oxide film 13 are sequentially etched using the photoresist pattern 17 as a mask.
이때, 상기 질화막(15)의 식각공정시 상기 질화막(15)과 포토레지스트(17)의 측벽에 폴리머(19)가 남게 된다.At this time, the polymer 19 is left on the sidewalls of the nitride film 15 and the photoresist 17 during the etching process of the nitride film 15.
도 2c 를 참조하면, 상기 포토레지스트 패턴(17) 및 폴리머(19)를 마스크로 하여 상기 실리콘기판(10)을 소정깊이 식각하여 트랜치(25)를 형성한다.Referring to FIG. 2C, the trench 25 is formed by etching the silicon substrate 10 by a predetermined depth using the photoresist pattern 17 and the polymer 19 as a mask.
이때, 상기 트랜치(25) 식각공정은 상기 질화막(15)의 식각공정을 실시한 장비와는 다른 식각장비에서 실시하되, 상기 포토레지스트 패턴(17)과 폴리머(19)가 있는 상태에서 Cl2/N2가스계 식각가스와 50 ∼ 100 와트(watt) 의 바이어스 전력으로 실시함으로써 저부 모서리 부분이 라운딩된 바텀 바운딩부(21)를 구비하는 트랜치(25)를 형성한다.In this case, the trench 25 may be etched in an etching apparatus different from that in which the nitride layer 15 is etched, and Cl 2 / N is present in the photoresist pattern 17 and the polymer 19. A trench 25 having a bottom bounding portion 21 with rounded bottom edges is formed by performing a two- gas etching gas and a bias power of 50 to 100 watts.
여기서, 상기 실리콘기판(10)이 놓이는 식각장비 내부의 하부전극 온도가 내려갈수록 마이크로 트랜치는 감소하게 되며, 바람직하게는 -60 ∼ -20 ℃ 로 조절한다.Here, as the temperature of the lower electrode inside the etching apparatus on which the silicon substrate 10 is lowered, the micro trench decreases, and is preferably controlled at -60 to -20 ° C.
또한, 상기 식각조건중 하나라도 만족되지 않을 경우에는 정도의 차이가 있지만 마이크로 트랜치가 발생하게 된다.In addition, when any one of the etching conditions is not satisfied, there is a difference in degree, but micro trenches are generated.
도 2d 를 참조하면, 상부의 포토레지스트 패턴(17)을 제거한 후, 세정공정을 실시하여 트랜치(25) 형성을 완료한다.Referring to FIG. 2D, after the upper photoresist pattern 17 is removed, the trench 25 is formed by performing a cleaning process.
이때, 상기 트랜치(25)는 트랜치(25) 저부 모서리부분이 라운딩된 형상으로 형성됨을 알 수 있다.In this case, it can be seen that the trench 25 is formed in a rounded shape of the bottom edge of the trench 25.
이상 상술한 바와 같이, 본 발명에 따른 반도체 소자의 소자분리 방법은 트랜치 식각을 이용한 소자분리공정에 있어서, 트랜치 식각시 질화막 식각공정에서 유도된 포토레지스트 패턴과 그 측벽에 형성된 측벽 폴리머를 마스크로 하여 낮은 바이어스 전력의 식각조건하에서 트랜치 식각을 진행함으로써 한번의 메인 식각공정으로 트랜치 저부 모서리부분이 라운딩되도록 형성하여 별도의 후처리공정을 생략할 수 있으므로 소자의 제조공정을 단순화시키고 그에 따른 반도체소자의 수율, 특성 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the device isolation method of the semiconductor device according to the present invention, in the device isolation process using trench etching, the photoresist pattern induced in the nitride film etching process during the trench etching and the sidewall polymer formed on the sidewall thereof are used as a mask. The trench etching is performed under the etching condition of low bias power so that the corner part of the bottom of the trench can be rounded by one main etching process, so that a separate post-processing step can be omitted, thus simplifying the manufacturing process of the device and the yield of the semiconductor device accordingly. In addition, it provides an effect to improve the characteristics and reliability.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019960079869A KR100419026B1 (en) | 1996-12-31 | 1996-12-31 | Isolation method of semiconductor device |
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| KR1019960079869A KR100419026B1 (en) | 1996-12-31 | 1996-12-31 | Isolation method of semiconductor device |
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|---|---|---|---|---|
| US4784720A (en) * | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
| JPH0513378A (en) * | 1991-06-29 | 1993-01-22 | Sony Corp | Dry etching method |
| JPH08186111A (en) * | 1994-12-28 | 1996-07-16 | Sony Corp | Forming method for connecting hole |
| KR960026302A (en) * | 1994-12-29 | 1996-07-22 | 김주용 | Trench manufacturing method of semiconductor device |
| KR980006052A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | Device Separation Method of Semiconductor Device |
| KR980011971A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Photoresist mask trench etching method through polymer deposition |
| KR19980036490A (en) * | 1996-11-18 | 1998-08-05 | 김광호 | Trench of semiconductor device and forming method |
| KR100224782B1 (en) * | 1996-12-31 | 1999-10-15 | 김영환 | Method of forming an element isolation region in a semiconductor device |
-
1996
- 1996-12-31 KR KR1019960079869A patent/KR100419026B1/en not_active Expired - Fee Related
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4784720A (en) * | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
| JPH0513378A (en) * | 1991-06-29 | 1993-01-22 | Sony Corp | Dry etching method |
| JPH08186111A (en) * | 1994-12-28 | 1996-07-16 | Sony Corp | Forming method for connecting hole |
| KR960026302A (en) * | 1994-12-29 | 1996-07-22 | 김주용 | Trench manufacturing method of semiconductor device |
| KR980006052A (en) * | 1996-06-26 | 1998-03-30 | 김광호 | Device Separation Method of Semiconductor Device |
| KR980011971A (en) * | 1996-07-29 | 1998-04-30 | 김광호 | Photoresist mask trench etching method through polymer deposition |
| KR19980036490A (en) * | 1996-11-18 | 1998-08-05 | 김광호 | Trench of semiconductor device and forming method |
| KR100224782B1 (en) * | 1996-12-31 | 1999-10-15 | 김영환 | Method of forming an element isolation region in a semiconductor device |
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