KR100418017B1 - Data and clock recovery circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data and clock recovery circuit, wherein a reset signal is generated using a voltage control signal generated from a phase synchronization circuit (PLL), and the reset signal is a transition of serial data (hereinafter, referred to as "input data"). A reset signal generator for causing a pulse width of 1/2 of the data bit rate at each time point of occurrence; N clock signals are generated, and N clock signals are generated using the voltage control signal generated from the phase synchronization circuit, and the (N-1) th clock (clock [N-1]) and the (N) signal are generated. A clock signal generator which makes the delay time between the < RTI ID = 0.0 >) th clock < / RTI > N phase control signal generation blocks, the reset signal output from the reset signal generator, a clock signal generation block [N-1] and a clock signal [N-1] output from the clock signal generation block [N]; A phase control signal generator for receiving a clock N, generating a phase control signal PC [N] for controlling the phase of the clock N, and inputting the clock signal to the clock signal generation block N; It consists of (N-1) flip-flops and uses (N-1) clocks from clock [1] to clock [N-1] to convert (N-1) parallel data into (N-1) It comprises a flip-flop unit for storing in the flip-flop.

Description

Data and clock recovery circuit

The present invention relates to a data and clock recovery circuit, and more particularly, in a high-speed data transmission system, a data and clock having a function capable of providing a stable clock and restoring transmitted data without error. It relates to a restoration circuit.

As illustrated in FIG. 1, a clock and data recovery circuit for a conventional serial data link utilizes a phase locked loop (PLL) 11 having serial input data as input. A restored clock synchronized with the data is provided, and serial input data is stored in the flip-flop 13 using the provided restored clock to recover the data. In addition, serial-to-parallel converter 15 is used to parallelize the serial data into N parallel data in order to convert the high speed serial data into parallel data. The phase synchronization circuit uses a frequency phase detector that directly compares the phase of the transition of the input data with the phase of the clock pulse transition output from the voltage controlled oscillator.

However, when using a phase-locked circuit having data as an input, the serial input data has the same frequency as the bit rate of the data for the case where logic '0' or '1' is continued, and has a phase synchronized with the serial input data. Difficult to provide clock

In addition, in order to recover the data transmitted at high speed, when jitter of the input data occurs, a phase synchronization circuit that provides a clock synchronized with the data in a short time is required. In the prior art, since the data is used as an input of the phase synchronization circuit, generation of a synchronized clock according to the jitter of the data depends on the performance of the frequency phase detector and the charge pump, making it difficult to produce a clock synchronized with the data in a short time.

In addition, a system for multi-channel serial data transmission requires a phase synchronization circuit for each channel and an additional serial-to-parallel converter for parallelizing high-speed data into low-speed data, thereby increasing physical area during chip fabrication. There is a problem.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above problems in the conventional data and clock recovery circuits, and it is possible to make a clock synchronized with data in a short time, and to phase each channel in a system for serial data transmission of multiple channels. It is an object of the present invention to provide a data and clock recovery circuit that does not require a synchronous circuit and does not need an additional serial-parallel converter for parallelizing high-speed data to low-speed data, thereby reducing chip area.

1 is an exemplary diagram of a conventional data and clock recovery circuit.

Figure 2a is a clock signal generator and phase control signal generator of the circuit according to the present invention

Figure 2b is a detailed configuration of the flip-flop portion of the circuit according to the present invention

3 is a detailed configuration diagram of a reset signal generator of a circuit according to the present invention;

4 is a detailed block diagram of a phase control signal generation block of a circuit according to the present invention;

5 is a detailed block diagram of a clock signal generation block of a circuit according to the present invention;

6 is a timing diagram of a circuit according to the present invention;

7 is a circuit diagram illustrating data input through multiple channels.

8 is a block diagram of a circuit to which a divider is added;

<Description of Major Symbols in Drawing>

10 reset signal generator, 20 clock signal generator, 30 phase control signal generator, 40 flip-flop, 45 second flip-flop, 50 phase control circuit (PLL)

Composition of the Invention

To this end, a circuit for generating a clock synchronized with data after half the data bit rate (T / 2) after the transition point of the data was made, and a block for performing such an operation was connected in the form of a ring oscillator. The delay time of the block performing this operation is equal to the data bit rate, and when N is connected in a ring structure, it acts as a voltage controlled oscillator that is as slow as 1 / N of the data bit rate. Therefore, no phase synchronization circuit suitable for high-speed data is required.

The output of the ring-controlled voltage-controlled oscillator is used as a clock to sequentially restore the serial input data, which acts as a serial-to-parallel converter. This means that no additional serial-to-parallel converter is required.

In the serial data transmission of the multi-channel, only the voltage control signal is used in the phase synchronization circuit. This reduces the area of chip fabrication because multi-channel serial data transmission is possible using only one phase synchronization circuit.

In the prior art, the limit of high-speed data transmission is determined by the performance of the voltage controlled oscillator and the flip-flop, but the new circuit is determined by the XOR logic having the data transfer rate as the limit corresponding to the half period of the data bit rate. Therefore, a high speed phase detector, a charge pump, a voltage controlled oscillator, a flip-flop, etc., which are required for a high speed phase synchronization circuit are not required, and even a low speed circuit can have sufficient performance.

In more detail, the technical components of the present invention, the data and clock recovery circuit according to the present invention,

A reset signal is generated using the voltage control signal generated by the phase synchronization circuit PLL, and the reset signal is a pulse of 1/2 of the data bit rate every time a transition of the input serial data (hereinafter, “input data”) occurs. A reset signal generator having a width,

N clock signals are generated, and N clock signals are generated using the voltage control signal generated from the phase synchronization circuit, and the (N-1) th clock (clock [N-1]) and the (N) signal are generated. A clock signal generator that has a delay time between the &lt; RTI ID = 0.0 &gt;

N phase control signal generation blocks, the reset signal output from the reset signal generator, a clock signal generation block [N-1] and a clock signal [N-1] output from the clock signal generation block [N]; A phase control signal generator for receiving a clock [N], generating a phase control signal PC [N] for controlling the phase of the clock [N], and inputting the clock signal to the clock signal generation block [N];

It consists of (N-1) flip-flops and uses (N-1) clocks from clock [1] to clock [N-1] to convert (N-1) parallel data into (N-1) It comprises a flip-flop unit for storing in the flip-flop.

The (N-1) parallel data stored in the flip-flop unit may be restored to N-bit parallel data by adding a first flip-flop unit which restores the N-bit parallel data together with the input data using the clock [N]. Can be.

The reset signal generation unit delays the input data by half the data bit rate, and generates a reset signal by taking XOR with the input data. The clock signal generation block [N] of the clock signal generation unit is a clock [ N-1] and the voltage control signal and the phase control signal [N] are input to generate a clock [N].

In addition, the data and clock recovery circuit according to the present invention includes a plurality of data recovery circuits including a reset signal generator, a clock signal generator, and a phase control signal generator, and one phase synchronization circuit for inputting a voltage control signal to all data recovery circuits. And a plurality of flip-flop units corresponding to the data recovery circuit, and converts a plurality of serial data input through multiple channels into parallel data.

The present invention can also be configured to insert a divider into the input portion of the serial data so as to divide the input data to change the data transition time.

Actions and Examples of the Invention

Hereinafter, the operation of each component of the data and clock recovery circuit according to the present invention will be described through specific embodiments with reference to the accompanying drawings.

2A and 2B are overall configuration diagrams of a data and clock recovery circuit according to the present invention, in which the entire circuit is a phase synchronization circuit (PLL) 50 for supplying a voltage control signal, a reset signal generator 10, and a clock signal generation. The unit 20 includes a phase control signal generator 30 and a flip-flop unit 40.

The phase synchronization circuit 50 uses a general method of multiplying the system clock. However, a clock signal generator may be used for the voltage controlled oscillator portion of the phase synchronization circuit 50.

The operation of each component is described in detail as follows.

First, the reset signal generator 10 delays the input serial data (hereinafter referred to as "input data") by half (T / 2) of the data bit rate and takes a XOR with the input data to generate a reset signal. Let's do it. 3 shows a specific configuration of the reset signal generator 10. The reset signal generator 10 generates a signal having a pulse width equal to half of the data bit rate T every time a data transition occurs.

The phase control signal generation section 30 is composed of N phase control signal generation blocks PG [1], PG [2], .... PG [N-1], PG [N]. N-th phase control signal generation block (phase control signal generation block [N]). The phase control signal generation block [N] is the reset signal generated by the reset signal generator 10 and the N-1 th clocks (clocks [N-1], CLK [N]) and N generated by the clock signal generator 20. The second clock (clocks [N], CLK [N]) as an input. The two signals, clock [N] and clock [N-1], are taken XOR, and the reset signal is ANDed again to generate a phase control signal [N]. The phase control signal [N] is a signal for controlling the phase of the Nth clock.

The clock signal generator 20 is composed of N clock signal generator blocks CG [1], CG [2], .... CG [N-1], CG [N], and FIG. The clock signal generation block (clock signal generation block [N]) is shown. The delay time between the clock [N-1] and the clock [N] is equal to the data bit rate (T).

The phase control signal [N] is a selection signal of two MUXs (MUX1 and MUX2). MUX1 has a signal ck10 whose clock [N-1] is delayed by half the data bit rate and a non-inverting signal ck11 of clock [N-1] as inputs. MUX2 has as inputs a signal ck30 delayed by half the data bit rate of MUX1 and an inverted signal ck31 of clock [N-1].

When the phase control signal [N] is logic '0', MUX1 and MUX2 select the ck10 and ck30 signals, respectively. Therefore, the signal of clock [N-1] is transferred to clock [N] after a time equal to the data bit rate. When the phase control signal [N] is a logic '0', the clock signal generator 20 forms a ring structure to serve as a voltage controlled oscillator in a general phase synchronization circuit. However, when the phase control signal [N] has a pulse width equal to half the data bit rate, the ck2 signal has a non-inverting signal of the clock [N-1] by using MUX1 and MUX2. The N] signal has an inverting signal to control the phase of the clock [N].

FIG. 2A shows a signal relationship between the N clock signal generation blocks of FIG. 5 having a ring structure and the N phase control signal blocks. Each phase control signal generation block receives the clock output of the clock signal generation block as an input and outputs the phase control signal to the output. These phase control signals control the phase of the output clock of each clock signal generation block.

Fig. 6A shows the input data and the clock signals (clock [1], clock [2], ..., clock [N-1], clock [N]) that are outputs of the reset signal and the clock signal generator 20. Fig. 6b shows the phase state of the clock when serial input data is applied.

First, the reset signal rises when the transition of the input data occurs and generates a reset signal equal to half the data bit rate. The same happens when the data falls. If the reset signal is generated between the clock [N-1] and the clock [N] (Fig. 6B), the reset signal enters the input of the phase control signal generation block [N], and the clock [N-1] and the clock [ A phase control signal [N] is generated through the AND of the XOR signal of N].

When the phase control signal [N] becomes logic '1', the clock [N-1] signal is selected as the output of MUX1, and the output of MUX2 becomes the inverted value of the clock [N-1]. The value (logic '0') at the rising point of the phase control signal [N] is maintained. Thereafter, when the phase control signal [N] falls, when the selection signal SELN1 of MUX1 is logic '0', the output of MUX1 becomes the value of clock [N-1], and the selection signal SELN2 of MUX2 becomes logic '0. ', The output of MUX2 becomes the value of clock [N-1], the output of MUX1. Therefore, the clock [N] has the value of the clock [N-1] at the falling time of the phase control signal [N].

If jitter occurs due to an external or internal environment in the serial input data, the phase of the data changes. This change results in a phase change at the time of transition of the data.

FIG. 6C illustrates a case where the transition of data occurs earlier by the phase of d than when the jitter of the input data causes a change in the phase of the data and there is no jitter of the data. In this case as well, the circuit performs the same operation as in Fig. 6B. When the input data transition occurs, the reset signal rises to generate the phase control signal [N] in the corresponding clock range (between clock [N-1] and clock [N]). This phase control signal [N] outputs the signal of clock [N-1] to the output through MUX1 in advance, while MUX2 maintains the inverted value of clock [N-1].

Therefore, the clock [N] maintains the value at the rising point of the phase control signal [N]. After the data transition, the phase control signal falls after T / 2. SELN2, which is the select signal of MUX2, becomes a logic '0', and the output of MUX2 is transmitted with the output value of MUX1, so the value of clock [N] that is the output of MUX2 becomes the value of clock [N-1]. In the case of FIG. 6C, even if the data transition occurs earlier than the case where there is no jitter of the input data, the clock [N] signal rises after half a period (T / 2) after the data transition. It will provide a suitable recovery clock.

6D shows a case where data transition occurs later than when there is no jitter in the input data. In this case, the reset signal rises at the time of data transition, and the output of MUX1 is transferred with the value of clock [N-1]. However, the output of MUX2 maintains the inverted value of clock [N-1] to maintain the value at the time of rising of the phase control signal. When the phase control signal falls, the value of clock [N] is converted to the value of MUX1, that is, the state of clock [N-1]. Therefore, even if the transition point of the data occurs later than the jitter free state, the clock [N] is increased after T / 2, which is a half cycle after the data transition, to provide an optimal recovery clock. As a result, as shown in FIGS. 6B, 6C, and 6D, the recovery clock rises by half a period after the data transition point in both cases with and without input data jitter to restore the optimal data through the flip-flop.

FIG. 2B shows a circuit for converting serial input data into N parallel data using N clocks which are outputs of each block of the serial input data and the clock signal generator 20. FIG. 2N-1 flip-flops are used. First, N-1 parallel data is stored in N-1 flip-flops using N-1 clocks from clock [1] to clock [N-1] signals, and then clock N again. N-1 parallel data (PRD (1) to PRD (N-1)) and input data are restored using N flip-flops.

Accordingly, the serial input data includes N parallel data RD (1), RD (2), ..., RD (N-1), RD (N) synchronized with the clock [N] serving as the system clock. You can see that it is restored to). This simultaneously performs the function of an elastic buffer for converting the restored clock and the restored data back into data synchronized with the system clock. A detailed timing diagram for this is shown in FIG. 6E.

Fig. 7 is a circuit diagram for the case of having multi-channel serial input data. As shown in the figure, it is possible to reduce the area of chip fabrication because only one phase synchronization circuit can process serial data of multiple channels.

In the data and clock recovery circuit according to the present invention, as shown in Fig. 8, by inserting a divider in the serial input data portion, the input data can be divided to change the transition time of the data.

According to the data and clock recovery circuit according to the present invention, the following effects are obtained.

First, high speed serial input data can be converted into N parallel data without additional serial-to-parallel converter circuit.

Secondly, an additional circuit with the function of an elastic buffer can output data synchronized with the system clock without the need for additional circuitry.

Third, since only one phase synchronization circuit can have serial data of multiple channels as inputs, the area can be reduced during chip fabrication.

Fourth, the clock signal generator and the phase synchronizing circuit recover the data using a clock that is as much as N times slow without processing the high speed data. There is no need for circuits such as pumps, voltage controlled oscillators and flip-flops.

Claims (7)

A reset signal is generated using the voltage control signal generated by the phase synchronization circuit PLL, and the reset signal is a pulse of 1/2 of the data bit rate every time a transition of the input serial data (hereinafter, “input data”) occurs. A reset signal generator having a width, N clock signals are generated, and N clock signals are generated using the voltage control signal generated from the phase synchronization circuit, and the (N-1) th clock (clock [N-1]) and the (N) signal are generated. A clock signal generator that has a delay time between the &lt; RTI ID = 0.0 &gt; N phase control signal generation blocks, the reset signal output from the reset signal generator, a clock signal generation block [N-1] and a clock signal [N-1] output from the clock signal generation block [N]; A phase control signal generator for receiving a clock [N], generating a phase control signal PC [N] for controlling the phase of the clock [N], and inputting the clock signal to the clock signal generation block [N]; It consists of (N-1) flip-flops and uses (N-1) clocks from clock [1] to clock [N-1] to convert (N-1) bits of parallel data (N-1). And a data recovery clock circuit comprising a flip-flop unit for storing two flip-flops. The method of claim 1, And a second flip-flop portion configured to restore (N-1) parallel data and input data stored in the flip-flop portion to N-bit parallel data using a clock [N]. The method of claim 1, And the reset signal generator generates a reset signal by delaying the input data by half of the data bit rate, and then taking an XOR with the input data. The method of claim 1, The clock signal generation block [N] of the clock signal generation unit generates a clock [N] by inputting the clock [N-1] and the voltage control signal and the phase control signal [N]. Circuit. A phase synchronization opportunity for inputting a voltage control signal to a plurality of data recovery circuits and all data recovery circuits comprising a reset signal generator, a clock signal generator and a phase control signal generator according to claim 1 or 3 or 4. And a plurality of flip-flop units corresponding to the data recovery circuit, and converting a plurality of serial data input through multiple channels into parallel data. The method according to any one of claims 1 to 4, And a data divider for modifying the data transition time by inserting a divider in the input portion of the serial data to divide the input data. The method of claim 5, A data and clock recovery circuit, characterized in that the data transition time is modified by dividing the input data by inserting a divider in the input portion of the serial data.