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KR100403359B1 - Method for manufacturing semiconductor package - Google Patents

Method for manufacturing semiconductor package Download PDF

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Publication number
KR100403359B1
KR100403359B1 KR1019970075221A KR19970075221A KR100403359B1 KR 100403359 B1 KR100403359 B1 KR 100403359B1 KR 1019970075221 A KR1019970075221 A KR 1019970075221A KR 19970075221 A KR19970075221 A KR 19970075221A KR 100403359 B1 KR100403359 B1 KR 100403359B1
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South Korea
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film
substrate
bump
metal
bump metal
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KR1019970075221A
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Korean (ko)
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KR19990055289A (en
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홍성학
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

본 발명은 기판의 하면에 솔더볼 대신 금속 범프를 구비하여 박리현상을 방지할 수 있는 반도체 패키지의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor package that can prevent the peeling phenomenon by providing a metal bump instead of a solder ball on the lower surface of the substrate.

본 발명에 따른 반도체 패키지의 금속 범프는, 기판의 하면 상에 상기 기판의 소정 부분을 노출시키는 마스크 패턴을 형성하고, 상기 노출된 기판 및 상기 마스크 패턴의 측벽 상에 제 1 범프용 금속막을 형성한 다음, 상기 제 1 범프용 금속막의 표면 상에 제 2 범프용 금속막을 형성한 후, 상기 마스크 패턴을 제거함으로써 형성한다. 또한, 마스크 패턴을 제거한 후 상기 금속 범프의 상부 및 측부 표면이 노출되도록 상기 기판 전면에 보호막을 형성한다. 여기서, 상기 노출된 기판의 폭은 약 15 내지 25㎛이고, 상기 제 1 범프용 금속막은 Au 막으로 형성하고, 상기 제 2 범프용 금속막은 Ti막, Cu막, Pd막, W막, Pt막, 또는 Sn막/Ni막 중 선택되는 하나의 막으로 형성한다. 바람직하게, 상기 제 1 범프용 금속막은 Au 막으로 형성하고, 상기 제 2 범프용 금속막은 Sn막/Ni막으로 형성한다. 이때, 상기 제 2 범프용 금속막은 약 50 내지 150㎛의 두께로 형성한다.In the metal bump of the semiconductor package according to the present invention, a mask pattern exposing a predetermined portion of the substrate is formed on a lower surface of the substrate, and a first bump metal film is formed on sidewalls of the exposed substrate and the mask pattern. Next, after forming the 2nd bump metal film on the surface of the said 1st bump metal film, it forms by removing the said mask pattern. In addition, after removing the mask pattern, a protective film is formed on the entire surface of the substrate so that the upper and side surfaces of the metal bumps are exposed. Here, the exposed substrate has a width of about 15 to 25 μm, wherein the first bump metal film is formed of an Au film, and the second bump metal film is a Ti film, a Cu film, a Pd film, a W film, or a Pt film. Or a Sn film / Ni film. Preferably, the first bump metal film is formed of an Au film, and the second bump metal film is formed of a Sn film / Ni film. At this time, the second bump metal film is formed to a thickness of about 50 to 150㎛.

Description

반도체 패키지의 제조방법Manufacturing method of semiconductor package

본 발명은 반도체 패키지의 제조방법에 관한 것으로, 특히 기판의 하면에 금속 범프를 구비한 반도체 패키지의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor package, and more particularly, to a method for manufacturing a semiconductor package having a metal bump on a lower surface of a substrate.

도 1은 종래의 볼 그리드 어레이(Ball Grid Array ; BGA) 패키지를 나타낸 단면도이다.1 is a cross-sectional view illustrating a conventional ball grid array (BGA) package.

도 1을 참조하면, 소정의 회로 패턴(미도시)이 형성된 기판(1)의 상면(1a)에 반도체 칩(2)이 접착제(3)의 개재하에 부착되어 있고, 반도체 칩(2)과 기판(1)의 회로 패턴 사이에 금속 와이어(4)가 연결되어 칩(2)의 외부로의 전기적인 신호 전달 경로를 이루고 있다. 또한, 기판(1)의 하면(1b)에는 이후 실장을 위한 다수개의 솔더볼(5)이 격자 형태로 배열되도록 부착되어 있고, 기판(1)의 상부에 칩(2)을 외부 환경으로부터 보호하기 위한 에폭시 수지의 봉지체(6)가 형성되어 있다.Referring to FIG. 1, a semiconductor chip 2 is attached to an upper surface 1a of a substrate 1 on which a predetermined circuit pattern (not shown) is formed through an adhesive 3, and the semiconductor chip 2 and the substrate are provided. The metal wire 4 is connected between the circuit patterns of (1) to form an electrical signal transmission path to the outside of the chip (2). In addition, a plurality of solder balls 5 for mounting thereafter are attached to the lower surface 1b of the substrate 1 so as to be arranged in a lattice form, and to protect the chip 2 from the external environment on the upper portion of the substrate 1. The sealing body 6 of an epoxy resin is formed.

그러나, 상기한 종래의 볼 그리드 어레이 패키지는 이후 솔더볼(5)을 통하여 인쇄 회로 기판(Printed Circuit Board; PCB)에 실장되는데, 기판(1)과 솔더볼(5) 및 인쇄 회로 기판과 솔더볼(5)의 접합시 접합면에서 크랙(crack)이 발생하여, 박리현상을 유발함으로써 결국 반도체 패키지의 신뢰성을 저하시킨다. 즉, 이러한 크랙 현상은 접합 계면에서의 물질이 다르기 때문에, 기판(1)과 인쇄회로기판의 사이에 있는 솔더볼(5)이 주변 환경에 따라 전단응력(shear stress)을 가함으로써 발생한다.However, the conventional ball grid array package is mounted on a printed circuit board (PCB) through the solder ball 5, the substrate 1 and the solder ball (5) and the printed circuit board and solder ball (5) In the bonding process, cracks are generated at the bonding surface, causing peeling, which in turn lowers the reliability of the semiconductor package. That is, this crack phenomenon occurs because the solder balls 5 between the substrate 1 and the printed circuit board apply shear stress depending on the surrounding environment because the materials at the bonding interface are different.

따라서, 본 발명의 목적은 기판의 하면에 솔더볼 대신 금속 범프를 구비하여 상기한 접합 계면에서 박리현상을 방지할 수 있는 반도체 패키지의 제조방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor package that can prevent the peeling phenomenon at the bonding interface by providing metal bumps on the lower surface of the substrate instead of solder balls.

도 1은 종래의 볼 그리드 어레이 패키지를 나타낸 단면도.1 is a cross-sectional view showing a conventional ball grid array package.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 나타낸 단면도.2 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 패키지의 금속 범프 형성방법을 설명하기 위한 단면도.3A to 3C are cross-sectional views illustrating a metal bump forming method of a semiconductor package according to an embodiment of the present invention.

〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]

10 : 기판 10a, 10b : 기판의 상면 및 하면10: substrate 10a, 10b: upper and lower surfaces of the substrate

20 : 반도체 칩 30 : 접착제20 semiconductor chip 30 adhesive

40 : 금속 와이어 50 : 금속 범프40: metal wire 50: metal bump

60 : 봉지체60: sealing body

상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 반도체 패키지의 금속 범프는, 기판의 하면 상에 상기 기판의 소정 부분을 노출시키는 마스크 패턴을 형성하고, 상기 노출된 기판 및 상기 마스크 패턴의 측벽 상에 제 1 범프용 금속막을 형성한 다음, 상기 제 1 범프용 금속막의 표면 상에 제 2 범프용 금속막을 형성한 후, 상기 마스크 패턴을 제거함으로써 형성한다. 또한, 마스크 패턴을 제거한 후 상기 금속 범프의 상부 및 측부 표면이 노출되도록 상기 기판 전면에 보호막을 형성한다.In order to achieve the above object of the present invention, the metal bump of the semiconductor package according to the present invention, forming a mask pattern for exposing a predetermined portion of the substrate on the lower surface of the substrate, and of the exposed substrate and the mask pattern The first bump metal film is formed on the sidewall, and then the second bump metal film is formed on the surface of the first bump metal film, and then the mask pattern is removed. In addition, after removing the mask pattern, a protective film is formed on the entire surface of the substrate so that the upper and side surfaces of the metal bumps are exposed.

여기서, 상기 노출된 기판의 폭은 약 15 내지 25㎛이고, 상기 제 1 범프용 금속막은 Au 막으로 형성하고, 상기 제 2 범프용 금속막은 Ti막, Cu막, Pd막, W막, Pt막, 또는 Sn막/Ni막 중 선택되는 하나의 막으로 형성한다. 바람직하게, 상기 제 1 범프용 금속막은 Au 막으로 형성하고, 상기 제 2 범프용 금속막은 Sn막/Ni막으로 형성한다. 이때, 상기 제 2 범프용 금속막은 약 50 내지 150㎛의 두께로 형성한다.Here, the exposed substrate has a width of about 15 to 25 μm, wherein the first bump metal film is formed of an Au film, and the second bump metal film is a Ti film, a Cu film, a Pd film, a W film, or a Pt film. Or a Sn film / Ni film. Preferably, the first bump metal film is formed of an Au film, and the second bump metal film is formed of a Sn film / Ni film. At this time, the second bump metal film is formed to a thickness of about 50 to 150㎛.

상기한 본 발명에 의하면, 종래의 솔더볼 대신에 기판의 하면에 강한 결정구조의 합금으로 금속 범프를 형성하여, 접합시 기판과의 계면 및 인쇄회로기판과의 계면에서의 박리현상을 방지함으로써, 반도체 패키지의 신뢰성을 향상시킨다. 또한, 범프의 폭을 약 15 내지 25㎛ 정도로 형성하여, 동일 패키지내에 많은 수의 핀을 장착할 수 있는 효과가 있다.According to the present invention described above, instead of the conventional solder ball, metal bumps are formed on the lower surface of the substrate by a strong alloy of crystal structure, thereby preventing the peeling phenomenon at the interface with the substrate and the interface with the printed circuit board during bonding. Improve the reliability of the package. In addition, the width of the bump is formed to about 15 to 25㎛, there is an effect that a large number of pins can be mounted in the same package.

(실시예)(Example)

이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

도 2는 본 발명의 실시예에 따른 반도체 패키지를 나타낸 단면도이다.2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.

도 2를 참조하면, 소정의 회로 패턴(미도시)이 형성된 기판(10)의 상면(10a)에 반도체 칩(20)이 접착제(30)의 개재하에 부착되어 있고, 반도체 칩(20)과기판(10)의 회로 패턴 사이에 금속 와이어(40)가 연결되어 칩(20)의 외부로의 전기적인 신호 전달 경로를 이루고 있다. 또한, 기판(10)의 하면(10b)에는 이후 실장을 위한 다수개의 금속 범프(50)가 격자 형태로 배열되어 형성되어 있고, 기판(10)의 상부에 칩(20)을 외부 환경으로부터 보호하기 위한 에폭시 수지의 봉지체(60)가 형성되어 있다. 여기서, 금속 범프(50)는 그의 높이가 50 내지 150㎛이고, 그의 폭은 약 15 내지 25㎛ 이며, Ti막, Cu막, Pd막, W막, Pt막, 또는 Sn막/Ni막 중 선택되는 하나의 막과, Au막으로 이루어진다. 바람직하게, 금속 범프(50)는 Sn/Ni막과 Au막으로 이루어진다.Referring to FIG. 2, a semiconductor chip 20 is attached to an upper surface 10a of a substrate 10 on which a predetermined circuit pattern (not shown) is formed through an adhesive 30, and the semiconductor chip 20 and the substrate are provided. The metal wire 40 is connected between the circuit patterns of 10 to form an electrical signal transmission path to the outside of the chip 20. In addition, a plurality of metal bumps 50 for mounting thereafter are formed on the lower surface 10b of the substrate 10 in a lattice form, and the chip 20 is protected on the upper surface of the substrate 10 from an external environment. The sealing body 60 of the epoxy resin for this is formed. Here, the metal bump 50 has a height of 50 to 150 mu m and a width of about 15 to 25 mu m, and the metal bump 50 is selected from a Ti film, a Cu film, a Pd film, a W film, a Pt film, or a Sn film / Ni film. It consists of one film and an Au film. Preferably, the metal bump 50 is made of a Sn / Ni film and an Au film.

즉, 본 발명에서는 종래의 솔더볼(도 1참조) 대신에, 기판(10)의 하면(10b)에 금속 범프(50)를 부착함으로써, 기판(10)과의 박리현상 및 이후 인쇄회로기판과의 접합시의 접합면에서의 박리현상이 방지된다.That is, in the present invention, the metal bump 50 is attached to the lower surface 10b of the substrate 10 instead of the conventional solder ball (refer to FIG. 1), thereby peeling from the substrate 10 and then with the printed circuit board. Peeling on the joining surface at the time of joining is prevented.

이어서, 기판(10)의 하면(10b)에 금속 범프(50)를 형성하는 방법을, 도 3a 내지 도 3c를 참조하여 설명한다. 여기서, 도 3a 내지 도 3c는 하나의 금속범프에 대해서만 도시하였다.Next, the method of forming the metal bump 50 in the lower surface 10b of the board | substrate 10 is demonstrated with reference to FIGS. 3A-3C. 3A to 3C show only one metal bump.

도 3a를 참조하면, 레진(resin)으로 이루어진 최하단부 기판(10)의 하면(10b) 상에 레지스트막을 약 50 내지 100㎛의 두께로 도포하고, 포토리소그라피로 노광 및 현상하여, 금속 범프 예정영역의 기판(10)을 노출시키는 마스크 패턴(11)을 형성한다. 이때, 노출되는 기판(10)의 폭이 약 15 내지 25㎛가 되도록 한다. 그런 다음, 노출된 기판(10) 및 마스크 패턴(11)의 측벽 상에 제 1 범프용 금속막으로서 Au막(12)을 이후 형성되는 금속과 금속전이가 이루어지도록 비교적얇게, 바람직하게 약 10 내지 50㎛의 두께로 형성한다. 즉, 상기한 금속전이에 의해, 이후 Au막(12) 상에 형성되는 Sn/Ni막과 Au막(12)의 계면에서 들뜸 현상이 방지된다.Referring to FIG. 3A, a resist film is applied to a thickness of about 50 to 100 μm on the bottom surface 10b of the lowermost substrate 10 made of resin, exposed and developed by photolithography, and then exposed to a metal bump planned region. The mask pattern 11 exposing the substrate 10 is formed. At this time, the width of the exposed substrate 10 is about 15 to 25㎛. Then, on the sidewalls of the exposed substrate 10 and the mask pattern 11, the metal film formed as the first bump metal film 12 is formed relatively thinly, preferably from about 10 to about 10 to be formed. It is formed to a thickness of 50 μm. That is, the above-described metal transition prevents the lifting phenomenon at the interface between the Sn / Ni film and the Au film 12 formed on the Au film 12 afterwards.

도 3b를 참조하면, Au막(12)의 표면 상에 제 2 범프용 금속막으로서, Ti막, Cu막, Pd막, W막, Pt막, 또는 Sn막/Ni막 중 선택되는 하나의 막, 바람직하게 Sn/Ni막(13)을 이후 솔더링 시 최소한의 높이 확보를 위하여 비교적 두껍게, 바람직하게 약 50 내지 150㎛의 두께로 형성한다. 이에 따라, 이후 인쇄회로기판에 실장시, 불량률이 감소됨과 더불어 열방출이 방지된다.Referring to FIG. 3B, one film selected from among Ti film, Cu film, Pd film, W film, Pt film, or Sn film / Ni film as the metal film for the second bump on the surface of the Au film 12 Preferably, the Sn / Ni film 13 is formed relatively thick, preferably about 50 to 150 μm, in order to ensure a minimum height during soldering. Accordingly, when mounted on the printed circuit board, the defective rate is reduced and heat dissipation is prevented.

도 3c를 참조하면, 공지된 방법으로 마스크 패턴(11)을 제거하여, Au막(12) 및 Sn/Ni막(13)으로 이루어지고, 약 15 내지 25㎛의 폭과 약 50 내지 150㎛의 높이를 갖는 금속 범프(50)를 형성한다. 기판 전면에 보호막으로서 폴리이미드막(14)을 약 4 내지 6㎛ 두께로 형성한다. 이때, 폴리이미드막(14)은 스핀 코팅방식으로 도포한 후 약 4 내지 6㎛의 두께가 되도록 경화시켜 형성한다. 그런 다음, 금속 범프(50)의 표면이 노출되도록 건식식각으로 제거한다.Referring to FIG. 3C, the mask pattern 11 is removed by a known method, and is made of the Au film 12 and the Sn / Ni film 13, and has a width of about 15 to 25 μm and about 50 to 150 μm. A metal bump 50 having a height is formed. A polyimide film 14 is formed to a thickness of about 4 to 6 mu m as a protective film on the entire substrate. At this time, the polyimide film 14 is formed by applying a spin coating method and curing it to a thickness of about 4 to 6 μm. Then, it is removed by dry etching so that the surface of the metal bump 50 is exposed.

한편, 와이어 본딩시 기판(10)에 열이 가해지는데, 이때 Au막(12)의 원자들이 Sn/Ni막(13)으로 이동해가서 합금을 형성함으로써, 단단한 결합구조를 이룬다.Meanwhile, heat is applied to the substrate 10 during wire bonding. At this time, atoms of the Au film 12 move to the Sn / Ni film 13 to form an alloy, thereby forming a rigid bonding structure.

상기한 본 발명에 의하면, 종래의 솔더볼 대신에 기판의 하면에 강한 결정구조의 합금으로 금속 범프를 형성하여, 접합시 기판과의 계면 및 인쇄회로기판과의 계면에서의 박리현상을 방지함으로써, 반도체 패키지의 신뢰성을 향상시킨다. 또한, 범프의 폭을 약 15 내지 25㎛ 정도로 형성하여, 동일 패키지내에 많은 수의 핀을 장착할 수 있는 효과가 있다.According to the present invention described above, instead of the conventional solder ball, metal bumps are formed on the lower surface of the substrate by a strong alloy of crystal structure, thereby preventing the peeling phenomenon at the interface with the substrate and the interface with the printed circuit board during bonding. Improve the reliability of the package. In addition, the width of the bump is formed to about 15 to 25㎛, there is an effect that a large number of pins can be mounted in the same package.

또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.

Claims (4)

기판의 하면상에 상기 기판의 소정 부분을 노출시키는 마스크 패턴을 형성하는 단계;Forming a mask pattern on a lower surface of the substrate to expose a predetermined portion of the substrate; 상기 노출된 기판 및 상기 마스크 패턴의 측벽상에 Au으로 구성된 제 1 범프용 금속막을 형성하는 단계;Forming a first bump metal film made of Au on sidewalls of the exposed substrate and the mask pattern; 상기 제 1 범프용 금속막의 표면상에 제 2 범프용 금속막을 형성하는 단계;Forming a second bump metal film on a surface of the first bump metal film; 상기 마스크 패턴을 제거하여 제 1 및 제 2 범프용 금속막으로 이루어진 금속 범프를 형성하는 단계; 및,Removing the mask pattern to form a metal bump including a first and second bump metal layers; And, 상기 금속 범프의 상부 및 측부 표면이 노출되도록 상기 기판 전면에 폴리이미드막으로 구성된 보호막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 패키지의 제조방법.And forming a protective film made of a polyimide film on the entire surface of the substrate so that the upper and side surfaces of the metal bumps are exposed. 제 1 항에 있어서, 상기 노출된 기판의 폭은 약 15 내지 25㎛인 것을 특징으로 하는 반도체 패키지의 제조방법.The method of claim 1, wherein the exposed substrate has a width of about 15 to 25 μm. 제 1 항에 있어서, 상기 제 2 범프용 금속막은 Ti막, Cu막, Pd막, W막, Pt막, 또는 Sn막/Ni막 중 선택되는 하나의 막으로 형성하는 것을 특징으로 하는 반도체 패키지의 제조방법.The semiconductor package of claim 1, wherein the second bump metal film is formed of one of a Ti film, a Cu film, a Pd film, a W film, a Pt film, and a Sn film / Ni film. Manufacturing method. 제 1 항에 있어서, 상기 제 2 범프용 금속막은 약 50 내지 150㎛의 두께로 형성하는 것을 특징으로 하는 반도체 패키지의 제조방법.The method of claim 1, wherein the second bump metal film is formed to a thickness of about 50 μm to about 150 μm.
KR1019970075221A 1997-12-27 1997-12-27 Method for manufacturing semiconductor package Expired - Fee Related KR100403359B1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159034A (en) * 1988-12-13 1990-06-19 Nec Corp External electrode structure on semiconductor integrated circuit
JPH0574780A (en) * 1991-09-12 1993-03-26 Tanaka Kikinzoku Kogyo Kk Bump forming method
JPH05206139A (en) * 1991-11-19 1993-08-13 Nec Corp Substrate connection electrode and manufacture of the same
JPH05218047A (en) * 1992-01-31 1993-08-27 Toshiba Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159034A (en) * 1988-12-13 1990-06-19 Nec Corp External electrode structure on semiconductor integrated circuit
JPH0574780A (en) * 1991-09-12 1993-03-26 Tanaka Kikinzoku Kogyo Kk Bump forming method
JPH05206139A (en) * 1991-11-19 1993-08-13 Nec Corp Substrate connection electrode and manufacture of the same
JPH05218047A (en) * 1992-01-31 1993-08-27 Toshiba Corp Manufacture of semiconductor device

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