KR100403355B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR100403355B1 KR100403355B1 KR1019960024525A KR19960024525A KR100403355B1 KR 100403355 B1 KR100403355 B1 KR 100403355B1 KR 1019960024525 A KR1019960024525 A KR 1019960024525A KR 19960024525 A KR19960024525 A KR 19960024525A KR 100403355 B1 KR100403355 B1 KR 100403355B1
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- film
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- metal silicide
- layer
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 35
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 229920005591 polysilicon Polymers 0.000 claims abstract description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 25
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 23
- 230000001681 protective effect Effects 0.000 claims description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 229910001873 dinitrogen Inorganic materials 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 abstract 2
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 description 10
- 239000010937 tungsten Chemical group 0.000 description 10
- 239000005380 borophosphosilicate glass Substances 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- -1 tungsten nitride Chemical class 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910000510 noble metal Chemical group 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Chemical group 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
- H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
- H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
[발명의 분야][Field of Invention]
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 금속 실리사이드에 대한 보호막을 형성하는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for forming a protective film against metal silicide.
[종래기술][Private Technology]
대부분의 집적회로에서 낮은 비저항과 고온의 안정도를 가지는 금속 실리사이드가 접촉재료로서 대두되었다. 이 실리사이드는 고유의 조성과 각기의 화학적 성질을 갖는 금속-실리콘 화합물로서, 실리콘과 결합하는 금속으로는 내화성 금속족인 몰리브덴, 탄탈륨, 티타늄, 텅스텐 또는 귀금속 원자인 코발트, 니켈, 백금등과 반응한 화합물로 구성된다. 또한, 실리사이드는 낮은 비저항과 고온에서의 안정도 이외에도 양질의 실리사이드는 형성 및 에칭이 용이하고 강력한 접착력이 있으며, 산화 공정시 산화막을 형성할 수 있는 장점이 있다.In most integrated circuits, metal silicides having low resistivity and high temperature stability have emerged as contact materials. This silicide is a metal-silicon compound having an inherent composition and respective chemical properties. As a metal to be bonded with silicon, a compound reacted with molybdenum, tantalum, titanium, tungsten or noble metal atoms cobalt, nickel, platinum, etc. It consists of. In addition, in addition to low specific resistance and stability at high temperature, the silicide has an advantage of being able to easily form and etch, have strong adhesion, and form an oxide film during an oxidation process.
이러한 실리사이드는 현재의 폴리실리콘 배선 또는 게이트 전극위에 형성되어 전도성을 향상시키고, 소오스/드레인 접합 부분에 실리사이드를 부분적으로 형성시켜, 접합 영역 사이에 발생하는 접촉 저항을 감소시킴으로써, RC 지연 시간을 낮추는 역할을 한다.These silicides are formed on current polysilicon interconnects or gate electrodes to improve conductivity, and partially form silicides at the source / drain junctions, thereby reducing the contact resistance between the junction regions, thereby lowering the RC delay time. Do it.
즉, 제 1 도는 상기된 종래의 금속 실리사이드 구조의 워드 라인 형성방법을 나타낸 공정 단면도로서, 반도체 기판(1) 상부에 게이트 절연막(2)을 형성한 후, 그 상부에 폴리실리콘(3)을 증착하고, 전도성을 개선하기 위하여 불순물인 포클(POCl3) 이온을 주입하는 공정을 진행한 다음, 전체 구조 상부에 텅스텐 실리사이드막(4)을 형성한다. 그런 다음, 게이트 전극을 패턴화하기 위하여 포토리소그라피의 일련 공정 및 식각 공정으로 게이트 전극을 형성한 후, 이 게이트 전극을 이온 주입 마스크로하여 게이트 전극 양측의 소오스/드레인 영역에 저농도 이온을 주입함으로써, 저농도 불순물 영역(5)을 형성한다.1 is a cross sectional view showing a conventional method for forming a word line of a metal silicide structure, wherein a gate insulating film 2 is formed on a semiconductor substrate 1, and then polysilicon 3 is deposited thereon. Then, in order to improve conductivity, a process of injecting impurities (POCl 3 ) ions is performed, and then a tungsten silicide layer 4 is formed on the entire structure. Then, the gate electrode is formed by a series of photolithography and etching processes to pattern the gate electrode, and then low concentration ions are implanted into the source / drain regions on both sides of the gate electrode using the gate electrode as an ion implantation mask. The low concentration impurity region 5 is formed.
그 후, 전체 구조 상부에 산화막을 두껍게 증착한 다음 블랭킷 식각 방식으로 비등방성 식각하여, 게이트 양 측벽에 소정의 스페이서(6)를 형성한다. 그런 다음, 이 스페이서(6)를 이온주입 마스크로하여 소오스/드레인 영역에 고농도 이온을 주입함으로써, 고농도 불순물영역(7)을 형성한다. 이어서, 제 1 도에 도시되지는 않았지만 후속 공정시 형성될 폴리실리콘 또는 금속층과의 전기적 절연 및 평탄화를 위하여 전체구조 상부에 BPSG막(8)을 형성한다.Thereafter, a thick oxide film is deposited on the entire structure, and then anisotropically etched by a blanket etching method to form predetermined spacers 6 on both sidewalls of the gate. Then, the high concentration impurity region 7 is formed by implanting high concentration ions into the source / drain regions using the spacer 6 as an ion implantation mask. Subsequently, a BPSG film 8 is formed over the entire structure for electrical insulation and planarization with the polysilicon or metal layer to be formed in a subsequent process, although not shown in FIG.
그런데, 상기된 종래의 실리사이드 구조에 있어서는 텅스텐 실리사이드막 상부에 평탄화 절연막으로 BPSG막을 증착하게 되면, BPSG막으로부터 확산(diffusion)되어 나오는 B 및 P 이온이 텅스텐 실리사이드막으로 침투하여 저항값을 변화시키는 문제를 일으키게 된다.However, in the conventional silicide structure described above, when the BPSG film is deposited as the planarization insulating film on the tungsten silicide film, the B and P ions diffused from the BPSG film penetrate into the tungsten silicide film to change the resistance value. Will cause.
이에 대하여 종래에는 텅스텐 실리사이드막 상부에 산화막+BPSG막의 적층 구조를 평탄화 절연막으로 사용하게 되었지만, 이때에는 또한 다음과 같은 문제가 발생하게 된다.On the other hand, in the related art, a laminated structure of an oxide film + BPSG film on the tungsten silicide film is used as a planarization insulating film. However, the following problem also occurs.
즉, 텅스텐 실리사이드막의 저항을 낮추기 위하여 열공정을 진행하게 되면, 텅스텐 실리사이드막의 표면을 덮고 있는 상기 산화막으로 인하여, 텅스텐 실리사이드막의 잉여 실리콘이 충분히 소모되지 못하기 때문에 텅스텐 실리사이드막의 저항이 증가하게 된다.That is, when the thermal process is performed to lower the resistance of the tungsten silicide film, the resistance of the tungsten silicide film is increased because the excess silicon of the tungsten silicide film is not sufficiently consumed due to the oxide film covering the surface of the tungsten silicide film.
또한, 텅스텐 실리사이드막 상부에 산화막+BPSG막의 적층 구조를 가짐으로 인하여, 후속 금속 콘택 식각시 또는 금속 콘택 형성전의 클리닝 공정의 진행시에 상기 산화막과 BPSG막의 화학적 습식식각 속도의 차이로 인하여, 콘택 홀 측면에요철 구조가 발생하여 스텝 커버리지가 저하되는 문제가 발생하게 된다.In addition, due to the stacked structure of the oxide film + BPSG film on the tungsten silicide film, the contact hole due to the difference in the chemical wet etching rate of the oxide film and the BPSG film during the subsequent metal contact etching or during the cleaning process before forming the metal contact. The uneven structure is generated on the side surface, resulting in a problem that the step coverage is lowered.
이에 본 발명은 상기된 문제점을 감안하여 창출된 것으로서, 금속 실리사이드에 대한 보호막을 형성하여 금속 실리사이드막의 전도 특성을 개선함과 더불어 금속 배선형성시 스텝 커버리지를 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made in view of the above-described problems, and provides a method of manufacturing a semiconductor device capable of forming a protective film for the metal silicide to improve conduction characteristics of the metal silicide film and to improve step coverage in forming metal wiring. Has its purpose.
제 1 도는 종래의 금속 실리사이드 구조의 워드라인 형성방법을 나타낸 공정 단면도.1 is a cross-sectional view showing a conventional method for forming a word line of a metal silicide structure.
제 2 도는 본 발명의 일실시예에 따른 금속 실리사이드 보호막이 적용된 금속 실리사이드 구조의 워드라인 형성방법을 나타낸 공정 단면도.2 is a cross-sectional view illustrating a method of forming a word line of a metal silicide structure to which a metal silicide protective film is applied according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
11 : 반도체 기판 12 : 절연막11 semiconductor substrate 12 insulating film
13 : 폴리실리콘 14 : 텅스텐 실리사이드막13: polysilicon 14: tungsten silicide film
15 : 텅스텐 질화막 16 : 실리콘 질화막15 tungsten nitride film 16 silicon nitride film
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 폴리실리콘 상부에 금속 실리사이드막이 형성된 반도체 소자의 제조방법에 있어서, 상기 금속 실리사이드막 상부에 금속 실리사이드에 대한 보호막을 형성하는 단계를 포함하는 것을 특징으로 하고, 또한 상기 보호막은 금속 질화막과 실리콘 질화막인 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the step of forming a protective film for the metal silicide on the metal silicide film in the method of manufacturing a semiconductor device formed with a metal silicide film on the polysilicon. In addition, the protective film is characterized in that the metal nitride film and silicon nitride film.
상기 구성으로 된 본 발명에 의하면, 금속 실리사이드에 대한 보호막을 형성함으로써 금속 실리사이드막의 전도 특성을 개선함과 더불어 이후의 금속 배선 형성시 스텝 커버리지를 향상시킬 수 있게 된다.According to the present invention having the above structure, by forming a protective film for the metal silicide, it is possible to improve the conduction characteristics of the metal silicide film and to improve the step coverage in the subsequent formation of the metal wiring.
[실시예]EXAMPLE
이하, 첨부된 도면을 참조하여 본 발명의 일 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
제 2A 도 내지 제 2C 도는 본 발명의 일 실시예에 따른 금속 실리사이드 보호막이 적용된 금속 실리사이드 구조의 워드라인 형성방법을 나타낸 공정 단면도로서, 도면부호 11은 반도체 기판, 12는 절연막, 13은 도핑된 폴리실리콘, 14는 텅스텐 실리사이드막, 15는 텅스텐 질화막, 16은 실리콘 질화막이다.2A through 2C are cross-sectional views illustrating a method of forming a word line of a metal silicide structure to which a metal silicide protective film is applied according to an embodiment of the present invention, wherein reference numeral 11 is a semiconductor substrate, 12 is an insulating film, and 13 is a doped poly Silicon, 14 is a tungsten silicide film, 15 is a tungsten nitride film and 16 is a silicon nitride film.
먼저 제 2A 도에 도시된 바와 같이, 반도체 기판(11) 상부에 절연막(12)을 형성한후, 그 상부에 폴리실리콘(13)을 증착하고 전도성을 개선하기 위하여 불순물을 주입하는 포클 공정을 진행한 다음, 전체 구조 상부에 텅스텐 실리사이드막(14)을 증착한다.First, as shown in FIG. 2A, an insulating film 12 is formed on the semiconductor substrate 11, and then, a polysilicon 13 is deposited on the semiconductor substrate 11, and a fockle process of implanting impurities to improve conductivity is performed. Then, a tungsten silicide film 14 is deposited over the entire structure.
그런 다음 제 2B 도에 도시된 바와 같이, 포토리소그라피의 일련 공정 및 식각공정을 통하여 도핑된 폴리실리콘(13)/텅스텐 실리사이드막(14)의 적층 구조를 패턴화함으로써, 도핑된 폴리실리콘(13)/텅스텐 실리사이드막(14) 구조의 워드라인을 형성한다.Then, as shown in FIG. 2B, the doped polysilicon 13 is patterned by patterning the stacked structure of the doped polysilicon 13 / tungsten silicide layer 14 through a series of photolithography and etching processes. The word line of the tungsten silicide film 14 structure is formed.
그 후, 질소 가스 분위기에서 RTP(Rapid Thermal Process) 처리를 650 내지 1100℃의 온도에서 실시하게 되면, 어닐링에 의해 상기 증착 상태에서의 텅스텐 실리사이드막(14)이 재결정화 되면서, 실리콘/텅스텐의 조성비가 감소함으로써, 잉여 실리콘이 텅스텐 실리사이드막(14) 표면으로 외방 확산(out-diffusion) 된다.Subsequently, when the RTP (Rapid Thermal Process) treatment is performed at a temperature of 650 to 1100 ° C. in a nitrogen gas atmosphere, the composition ratio of silicon / tungsten is recrystallized while the tungsten silicide film 14 in the deposited state is recrystallized by annealing. By decreasing, excess silicon is out-diffused to the surface of the tungsten silicide film 14.
예컨대, 상기 증착 상태에서의 텅스텐 실리사이드막(14)의 실리콘/텅스텐의 조성비가 약 2.4 내지 2.6인 경우, 어닐링 후재결정화가 이루어지면 실리콘/텅스텐의 조성비가 약 2.1 내지 2.2로 변화하게 된다.For example, when the composition ratio of silicon / tungsten of the tungsten silicide layer 14 in the deposition state is about 2.4 to 2.6, the composition ratio of silicon / tungsten is changed to about 2.1 to 2.2 when recrystallization is performed after annealing.
여기서, 상기 RTP 온도를 650℃ 이상에서 실시하는 것은 텅스텐 실리사이드막(14)이 약 550 내지 600℃의 온도에서 구조 변화를 일으켜 막의 스트레스를 증가시키는 것을 방지하기 위함이다.Here, the RTP temperature is performed at 650 ° C. or higher to prevent the tungsten silicide film 14 from causing a structural change at a temperature of about 550 to 600 ° C. to increase stress of the film.
이어서, 상기 RTP 처리시 주입된 질소 가스는 제 2C 도에 도시된 바와 같이, 텅스텐 실리사이드막(14)의 텅스텐과 반응하여 텅스텐 실리사이드막(14) 표면에 텅스텐 질화막(15)을 형성하게 된다.Subsequently, the nitrogen gas injected during the RTP treatment reacts with the tungsten of the tungsten silicide film 14 to form a tungsten nitride film 15 on the surface of the tungsten silicide film 14.
또한 이 텅스텐 질화막(15)의 형성과 동시에, 상기 질소 가스는 상기 외방 확산된 잉여 실리콘과 결합하게 하여, 얇은 실리콘 질화막(16)을 형성하게 된다. 그 후, 제 2 도에 도시되지는 않았지만 워드라인 형성을 위한 후속 공정을 진행하게 된다.At the same time as the formation of the tungsten nitride film 15, the nitrogen gas is combined with the outwardly diffused excess silicon to form a thin silicon nitride film 16. Thereafter, although not shown in FIG. 2, a subsequent process for word line formation is performed.
즉, 상기 실시예에 의하면 팅스텐 실리사이드막의 잉여 실리콘을 충분히 소모시킴으로써, 텅스텐 실리사이드막의 저항이 감소된다. 또한, RTP 처리시 형성되는 텅스텐 질화막/실리콘 질화막이 후속 공정에 사용되는 BPSG막으로부터 침투하는 B, P 이온에 대한 보호막 역할을 함으로써, 텅스텐 실리사이드막의 저항값 변화를 방지할 수 있게 됨에 따라 텅스텐 실리사이드막의 전도 특성을 개선할 수 있게 된다.That is, according to the above embodiment, the excess silicon of the tinsten silicide film is sufficiently consumed, so that the resistance of the tungsten silicide film is reduced. In addition, since the tungsten nitride film / silicon nitride film formed during the RTP treatment serves as a protective film for B and P ions penetrating from the BPSG film used in the subsequent process, the resistance value change of the tungsten silicide film can be prevented. It is possible to improve the conduction characteristics.
뿐만 아니라, 반도체 제조 공정시 통상적으로 사용되는 산화막+BPSG막의 적층구조를 형성할 필요가 없게 됨에 따라, 금속배선의 스텝 커버리지를 향상시킬 수 있게 된다.In addition, since it is not necessary to form a laminated structure of an oxide film + BPSG film which is commonly used in the semiconductor manufacturing process, it is possible to improve the step coverage of the metal wiring.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
즉, 본 발명에서는 워드라인의 형성방법에 대하여 국한하여 설명하였지만, 비트 라인 및 그 밖의 텅스텐 실리사이드가 형성되는 공정에는 모두 적용되며, 또한 텅스텐 실리사이드 이외에도 금속 실리사이드가 형성되는 공정에 적용할 수 있다.That is, in the present invention, the word line forming method is limited to the above description, but it is applicable to all of the processes for forming bit lines and other tungsten silicides, and also to the processes for forming metal silicides in addition to tungsten silicides.
이상 설명한 바와 같이 본 발명에 의하면, 금속 실리사이드막에 대한 보호막을 형성하여 금속 실리사이드막의 전도 특성을 개선함과 더불어 스텝 커버리지를 향상시킬 수 있는 반도체 소자의 제조방법을 실현할 수 있다.As described above, according to the present invention, a method for manufacturing a semiconductor device capable of forming a protective film for the metal silicide film to improve the conduction characteristics of the metal silicide film and to improve step coverage.
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| KR1019960024525A KR100403355B1 (en) | 1996-06-27 | 1996-06-27 | Method for manufacturing semiconductor device |
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| KR1019960024525A KR100403355B1 (en) | 1996-06-27 | 1996-06-27 | Method for manufacturing semiconductor device |
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