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KR100403322B1 - Method of manufacturing semiconductor device and exposure apparatus used therefor - Google Patents

Method of manufacturing semiconductor device and exposure apparatus used therefor Download PDF

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KR100403322B1
KR100403322B1 KR1019960023221A KR19960023221A KR100403322B1 KR 100403322 B1 KR100403322 B1 KR 100403322B1 KR 1019960023221 A KR1019960023221 A KR 1019960023221A KR 19960023221 A KR19960023221 A KR 19960023221A KR 100403322 B1 KR100403322 B1 KR 100403322B1
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exposure
photoresist
semiconductor device
exposure apparatus
energy
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KR980003854A (en
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김정회
한상준
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주식회사 하이닉스반도체
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    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/708Construction of apparatus, e.g. environment aspects, hygiene aspects or materials
    • G03F7/7085Detection arrangement, e.g. detectors of apparatus alignment possibly mounted on wafers, exposure dose, photo-cleaning flux, stray light, thermal load
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/7055Exposure light control in all parts of the microlithographic apparatus, e.g. pulse length control or light interruption
    • G03F7/70558Dose control, i.e. achievement of a desired dose

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  • Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

본 발명은 반도체소자의 제조방법 및 그에 사용되는 노광장치에 관한 것으로서, 축소노광장치에 FT-IR을 결합시킨 노광장치를 사용하여 일정 에너지로 일차 노광한 감광막의 감광제의 변화되는 성분을 FT-IR로 측정하여 노광영역의 감광막 저면에서의 완전 노광 여부를 파악하고, 그 결과에 따라 재노광 에너지를 결정하여 이차 노광을 실시하였으므로, 노광과 동시에 노광 에너지의 과다 여부를 알수가 있어 적정 노광에너지의 결정이 용이하고, 실험에 필요한 시간 및 노력이 절감되고, 실험에 소요되는 웨이퍼의 소모가 없어져 수율이 향상되며, 감광막의 위치에 따른 두께차도 보상할 수 있어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method of manufacturing a semiconductor device and an exposure apparatus used therefor, wherein a changed component of a photosensitizer of a photoresist film exposed to a primary energy at a constant energy using a FT- It is possible to determine whether the exposure energy is excessive or not at the same time as the exposure and the exposure energy are determined at the same time as determining the appropriate exposure energy since the secondary exposure is performed by determining whether the exposure area is completely exposed at the bottom of the photosensitive film, It is possible to reduce the time and effort required for the experiment, to eliminate the consumption of wafers consumed in the experiment, to improve the yield, to compensate the thickness difference according to the position of the photoresist film, and to improve the process yield and reliability of the device operation have.

Description

반도체소자의 제조방법 및 그에 사용되는 노광장치Method of manufacturing semiconductor device and exposure apparatus used therefor

본 발명은 반도체소자의 제조방법 및 그에 사용되는 노광장치에 관한 것으로서, 특히 FT-IR을 이용하여 노광시 변화되는 감광제의 성분을 분석하여 적정 노광에너지를 결정하여 검사에 따른 수율 저하나 감광막 두께에 따른 노광량 변화를 용이하게 검사하여 공정 수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 제조방법 및 그에 사용되는 노장장치에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device and an exposure apparatus used therefor. More particularly, the present invention relates to a method of manufacturing a semiconductor device and a method of manufacturing the same, Which can improve the process yield and the reliability of the device operation by easily examining a change in exposure amount according to the exposure amount of the semiconductor device.

최근 반도체 장치의 고집적화 추세는 미세 패턴 형성기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막 패턴의 미세화가 필수요건이다.In recent years, the trend toward higher integration of semiconductor devices has been greatly influenced by the development of fine pattern forming technology, and it is an essential requirement to miniaturize the photoresist pattern widely used in masks such as etching or ion implantation processes in the manufacturing process of semiconductor devices.

상기 감광막패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정변수(k)에 비례하고, 노광 장치의 렌즈구경(numerical aperture; NA)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength lambda of the light source of the reduction exposure apparatus and the process variable k and is inversely proportional to the numerical aperture NA of the exposure apparatus.

여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7, 0.5㎛ 정도가 한계이다.In this case, the wavelength of the light source is reduced in order to improve the optical resolving power of the reduction exposure apparatus. For example, the G-line and i-line reduction exposure apparatuses with wavelengths of 436 and 365 nm have process resolutions of about 0.7 and 0.5 μm Is the limit.

따라서 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 DUV, 예를들어 파장이 248nm인 KrF 레이저나 193nm인 ArF 레이저를 광원으로 사용하는 노광 장치를 이용하거나, 이미지 콘트라스트를 향상시킬 수 있는 별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; 이하 CEL이라 칭함) 방법 또는 위상 반전 마스크를 사용하기도 하지만, 장비의 광원을 미세 파장으로 바꾸는 데에도 한계가 있으며, 상기 CEL 방법은 공정이 복잡하고, 수율이 떨어진다.Therefore, in order to form a fine pattern of 0.5 탆 or less, an exposure apparatus using a DUV having a small wavelength, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm as a light source may be used or a separate (CEL) method for forming a thin film on a wafer or a phase inversion mask, but there is also a limit to changing the light source of the device into a minute wavelength, and the CEL method The process is complicated, and the yield is low.

또한 종래 기술의 다른 실시예로서, 단층 레지스트 방법보다는 두개의 감광막 사이에 중간층을 개재시킨 삼층 레지스트(Tri layer resister; 이하 TLR이라 칭함) 방법은 공정 변수가 작아 단층 감광막 방법에 비해 약 30% 정도 분해능이 향상되어 0.25㎛ 정도의 미세 패턴 형성이 가능하나, 256M나 1G DRAM 이상의 고집적 반도체 소자에서 필요한 0.2㎛ 정도의 패턴 형성 이 어려워 소자의 고집적화에 한계가 있다.Further, as another example of the prior art, a tri-layer resist (TLR) method in which an intermediate layer is interposed between two photoresist layers rather than a single-layer resist process has a process variable of about 30% It is possible to form a fine pattern of about 0.25 탆. However, it is difficult to form a pattern of about 0.2 탆 required for a highly integrated semiconductor device of 256M or 1G DRAM or more, and there is a limit to high integration of devices.

또한 이러한 한계를 극복하기 위하여 감광막의 상측에 선택적으로 실리콘을 주입시키는 실리레이션 공정을 이용하는 방법 등이 개발되어 분해능 한계치를 낮추고 있으나, 공정이 복잡하고, 재현성이 떨어진다.In order to overcome these limitations, a method using a silylation process in which silicon is selectively implanted on the upper side of the photoresist layer is developed to lower the resolution limit, but the process is complicated and the reproducibility is low.

종래 기술에 따른 감광막 패턴의 제조 공정을 살펴보면 다음과 같다.The manufacturing process of the photoresist pattern according to the prior art will be described below.

먼저, 소정의 하부구조가 형성되어 표면이 굴곡진 패턴을 형성하고자 하는 반도체기판상에 감광제 및 수지(resin) 등이 용재인 솔밴트에 일정 비율로 용해되어 있는 포토레지스트을 도포하여 감광막을 형성한 후, 투명기판상에 상기 감광막에서 패턴으로 예정되어 있는 부분에 대응되는 위치에 광차단막 패턴이 형성되어 있는 노광 마스크를 사용하여 빛을 예정된 에너지로 선택 조사하여 패턴으로 예정된 부분을 중합시킨다. 여기서 상기 노광 에너지는 웨이퍼의 어느 위치에서나 같은 노광량을 유지하기 위하여 노광 장치의 렌즈로부터 나오는 빛의 노광에너지량을 샤터 속도-오픈 시간-로 조절한다.First, a photoresist, in which a predetermined substructure is formed and a surface of which is curved, is coated with a photoresist dissolved in a solvent in a solvent such as a photosensitive agent and a resin to form a photoresist , The light is selectively irradiated with a predetermined energy using an exposure mask having a light blocking film pattern formed on a transparent substrate at a position corresponding to a portion expected to be a pattern in the photosensitive film to polymerize a predetermined portion in a pattern. Wherein the exposure energy adjusts the exposure energy amount of light emitted from the lens of the exposure apparatus to a shutter speed-open time to maintain the same exposure amount at any position of the wafer.

이때 상기의 중합 반응은 감광제(Photo Active Compound; 이하 PAC라 칭함)가 제 1 도에 도시되어 있는 바와 같이, 에스테르결합(=O)에서 노광된 후에는 케톤결합(C=O)으로 변화되거나,노광전에 PAC 내의 N2성분이 노광후 제거되는 반응이 일어나고,At this time, in the polymerization reaction, the photoactive compound (hereinafter referred to as PAC) is changed to a ketone bond (C = O) after being exposed at an ester bond (= O) Before the exposure, a reaction occurs in which the N 2 component in the PAC is removed after exposure,

그다음 상기 노광 공정을 진행한 웨이퍼를 열처리 장치에서 80∼120℃의 온도로 60∼120초간 소프트 베이크 열처리 공정을 실시한 후, TMAH(tetra methylammonium hydroxides)를 주원료로 하는 약알카리성 현상액을 사용하여 상기 감광막의 노광/비노광 영역들을 선택적으로 제거하고, 상기 웨이퍼를 탈이온수로 세척한 후, 건조시켜 감광막패턴을 형성한다.Then, the wafer subjected to the exposure process is subjected to a soft baking heat treatment at a temperature of 80 to 120 DEG C for 60 to 120 seconds in a heat treatment apparatus, and then a weak alkaline developer having tetramethylammonium hydroxides (TMAH) The exposed / unexposed regions are selectively removed, the wafer is washed with deionized water, and then dried to form a photoresist pattern.

그후, 상기와 같이 형성된 감광막 패턴을 시각 검사 장비인 씨.디(critical dimension) SEM을 사용하여 검사하여 적절한 노광 에너지의 수준을 측정하여 공정 조건을 설정하게 된다.Then, the photoresist pattern formed as described above is inspected using a critical dimension SEM, which is a visual inspection equipment, and the level of appropriate exposure energy is measured to set process conditions.

상기와 같은 종래 기술에 따른 반도체소자의 제조방법은 일정한 노광 에너지로 감광막패턴을 형성한 후, 시각 검사장치인 CD SEM을 이용하여 감광막 패턴의 이상 유무를 확인하는 방법을 사용하므로 써, 새로운 소자의 경우에는 적절한 공정 조건을 찾기 위해서는 다수번의 실험을 거쳐야 하고, 실험에 사용된 웨이퍼는 다시 사용할 수 없으며, 감광막의 부위별 두께 차에 대한 보상이 어려워 공정수율이 떨어지고, 제조 시간이 오래 걸려 납기 조절이 어려워지는 문제점이 있다.The method of manufacturing a semiconductor device according to the related art uses a method of forming a photoresist pattern with a predetermined exposure energy and then checking the presence or absence of a photoresist pattern using a CD SEM which is a visual inspection apparatus, It is difficult to compensate for the difference in thickness of the photoresist film, so that the yield of the process is lowered and the manufacturing time is long. There is a problem that it becomes difficult.

본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 감광막 노광 공정시 노광 부분에서의 감광막 계면의 감광제의 성분 변화를 FT-IR로 지속적으로 측정하거나, 감광제 내의 질소 성분 소모량을 측정하여 적정 노광량을 용이하게 하나의 웨이퍼만의 실험으로 결정할 수 있고, 이러한 측정값은 감광막의 부위별 두께 차에 대한 보상을 할수 있어 공정수율이 향상되고, 납기 단축에도 유리한 반도체소자의 제조방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a method and apparatus for continuously measuring the change in the component of the photosensitizer at the photosensitive film interface in the exposed portion in the photoresist film exposure process, Thus, the present invention provides a method of manufacturing a semiconductor device, which can improve the process yield and shorten the delivery time because it is possible to compensate for the difference in thickness of the photoresist layer by site. .

또한 축소노광장치와 FT-IR이 결합되어 있어 노광과 동시에 노광에너지량의 적정 유무를 알 수 있어 공정수율을 향상시킬 수 있는 노광 장치를 제공함에 있다.Also, it is an object of the present invention to provide an exposure apparatus capable of improving the process yield because the FT-IR is combined with the miniaturized exposure apparatus so that the exposure energy amount can be known at the same time as the exposure.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자 제조방법의 특징은,According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device,

임의의 구조의 반도체기판상에 형성되어있는 하부 층상에 감광제를 포함하는 감광막을 도포하는 공정과,A step of applying a photosensitive film containing a photosensitive agent on a lower layer formed on a semiconductor substrate having an arbitrary structure,

상기 감광막을 선택 노광하되, 노광되는 부분에서의 감광제의 성분 변화를 FT-IR로 측정하여 노광 부분의 감광막의 하부층과의 계면에서의 감광제가 변화되는 에너지로 노광하는 공정과,Exposing the photoresist film to light with energy that changes the photosensitizer at the interface with the lower layer of the photoresist film in the exposed portion by measuring the change in the component of the photosensitizer in the exposed portion with FT-IR;

상기 감광막을 현상하여 감광막 패턴을 형성하는 공정을 구비함에 있다.And developing the photoresist layer to form a photoresist pattern.

다른 목적을 달성하기 위한 본 발명에 따른 노광 장치의 특징은,According to another aspect of the present invention,

웨이퍼를 선택 노광하는 축소노광장치부와,A shaded area for selectively exposing the wafer,

상기 웨이퍼의 감광제의 성분 변화를 파악하는 FT-IR부와,An FT-IR unit for sensing a change in the component of the photosensitive agent of the wafer,

상기 FT-IR부의 분석 데이타를 분석하여 적정 속도로 상기 축소노광장치의 샤터를 조절하는 데이타 처리부를 구비함에 있다.And a data processing unit for analyzing the analysis data of the FT-IR unit and adjusting the shade of the reduction exposure apparatus at a proper speed.

이하, 본 발명에 따른 반도체소자의 제조방법 및 그에 사용되는 노광장치에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method for manufacturing a semiconductor device and an exposure apparatus used therefor according to the present invention will be described in detail with reference to the accompanying drawings.

제 2 도는 본 발명에 따른 반도체소자 제조에 사용되는 노광장치를 설명하기 위한 개략도이다.FIG. 2 is a schematic view for explaining an exposure apparatus used for manufacturing a semiconductor device according to the present invention. FIG.

먼저, 본 발명에 따른 반도체소자의 제조방법에 사용되는 노광장치는 축소노광장치(10) 뿐만 아니라, 노광되는 웨이퍼에서의 성분 변화를 측정할 수 있는 FT-IR(20) 및 데이터 처리부(30)와도 결합되어 있는 장비를 사용하게 된다.The exposure apparatus used in the method of manufacturing a semiconductor device according to the present invention includes not only a reduction exposure apparatus 10 but also an FT-IR 20 and a data processing unit 30 capable of measuring changes in components in exposed wafers, And will use equipment that is also coupled to.

상기의 장비는 축소노광장치(10) 부분은 웨이퍼(11)가 탑재되는 스테이지(도시되지 않음)와, 상기 웨이퍼(11)에 선택적으로 빛을 조사하기 위한 광원(13)-노광 마스크(15)-샤터(17)-대물렌즈(19)로 구성되며, 상기 샤터(17)의 속도 조절부(18)를 구비한다.The apparatus includes a stage (not shown) on which the wafer 11 is mounted, a light source 13 for selectively irradiating the wafer 11 with an exposure mask 15, A shutter 17, and an objective lens 19. The speed controller 18 of the shutter 17 is provided.

상기 FT-IR(20)은 노광된 웨이퍼(11) 부분에 적외선을 쪼이는 적외선 발광부(21)와, 조사되어 투과된 적외선을 검출하여 분석하여 검출하고자 하는 성분의 량을 계산하는 검출부(23)로 구성되는 광학계(25)를 구비하며, 상기 데이타 처리부(30)는 상기 축소노광장치(10)의 샤터 속도 조절부(18)와 연결되는 중앙처리장치(31)와, 상기 검출부(25) 및 전단계에서의 자료와 샤터속도등의 데이타를 보관하는 타임디레이 버퍼(time delay buffer; 33)로 구성된다.The FT-IR 20 includes an infrared ray emitting portion 21 for irradiating infrared rays to a portion of the exposed wafer 11, a detecting portion 23 for detecting an infrared ray transmitted and analyzing the infrared ray, The data processing unit 30 includes a central processing unit 31 connected to the shutter speed control unit 18 of the enlarged exposure apparatus 10, And a time delay buffer 33 for storing data such as data and shutter speed in the previous stage.

상기 장치를 사용한 반도체소자의 제조방법에 관하여 살펴보면 다음과 같다.A method of manufacturing a semiconductor device using the above apparatus will be described below.

먼저, 웨이퍼(11)상에 감광막(도시되지 않음)을 도포하고, 상기 노광장치의 스테이지 상에 탑재한 후, 일차로 조정된 샤터 속도(v1)로 노광하고, 상기 웨이퍼의 노광된 부분을 FT-IR(20)의 발광부(21)에서 조사하고, 검출부(23)로 데이타를 검출 분석하여 감광막에서의 감광제의 성분 변화를 검출하고, 감광막 바닥에서의 감광제가 변화되어 있는 지의 여부를 확인한 후에 다시 중앙처리장치(31)에서 나머지 노광량을 계산하여 샤터 속도 조절부(18)를 통하여 이차로 V2의 노광 속도로 노광한다.First, a photoresist film (not shown) is coated on the wafer 11, the wafer W is mounted on the stage of the exposure apparatus, exposed at a first-adjusted shutter speed v1, Irradiates the light-emitting portion 21 of the light-emitting device 20, detects and analyzes data with the detection portion 23, detects a change in the component of the photosensitive agent in the photosensitive film, confirms whether or not the photosensitive agent at the bottom of the photosensitive film is changed The central processing unit 31 again computes the remaining exposure amount and exposes it through the shutter speed control unit 18 at an exposure speed of V2 secondarily.

그다음 다시 상기 FT-IR(20)의 광학계(25)가 바닥 부분에서의 감광막의 변화 여부를 감지하여 후속 노광 여부를 결정하며, 후속 공정이 불필요한 경우에는 상기의 V1, V2에 의해 노광량을 알 수 있다.Then, the optical system 25 of the FT-IR 20 detects whether the photoresist film is changed in the bottom portion to determine whether or not the subsequent exposure is to be performed. If a subsequent process is unnecessary, the exposure amount is determined by V1 and V2 have.

상기에서는 노광 및 FT-IR(20)에 의한 스캔닝을 단계별로 실시하였으나, 노광 중간에도 연속적으로 FT-IR(20)에 의한 스캔닝을 실시할 수도 있다.In the above description, the exposure and the scanning by the FT-IR 20 are performed step by step, but the scanning by the FT-IR 20 can be continuously performed even during the exposure.

상기 감광제의 노광에 의한 변화는 감광제에 포함되어 있는 에스테르 결합이 노광되면, 케톤결합으로 변화되는 것을 이용하여 각각의 량을 측정하면 노광량을 결정할 수 있다.The amount of exposure of the photosensitive agent by exposure can be determined by measuring the amount of the ester bond contained in the photosensitive agent, which is changed into a ketone bond.

또한 감광제에 포함되어 있는 질소 성분이 노광 후에는 외부로 방출되므로 이를 검사하여도 적정 노광량을 결정할 수 있다.Also, since the nitrogen component contained in the photosensitizer is released to the outside after exposure, an appropriate exposure amount can be determined even by inspecting the nitrogen component.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 제조 방법 및 그에 사용되는 노광장치는 축소노광장치에 FT-IR을 결합시킨 노광장치를 사용하여 일정 에너지로 일차 노광한 감광막의 감광제의 변화되는 성분을 FT-IR로 측정하여 노광 영역의 감광막 저면에서의 완전 노광 여부를 파악하고, 그 결과에 따라 재노광 에너지를 결정하여 이차 노광을 실시하였으므로, 노광과 동시에 노광에너지의 과다 여부를 알 수가 있어 적정 노광 에너지의 결정이 용이하고, 실험에 필요한 시간 및 노력이 절감되고, 실험에 소요되는 웨이퍼의 소모가 없어져 수율이 향상되며, 감광막의 위치에 따른 두께 차도 보상할 수 있어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the method of manufacturing a semiconductor device and the exposure apparatus used therefor according to the present invention can be applied to a method of manufacturing a semiconductor device, in which a changed component of a photosensitizer of a photoresist film exposed by a constant energy primary exposure using a FT- Was measured by FT-IR to determine whether the exposure was complete or not at the bottom of the photoresist film, and the re-exposure energy was determined in accordance with the result of the measurement. As a result, secondary exposure was performed. It is possible to easily determine the exposure energy, to reduce the time and effort required for the experiment, to eliminate the consumption of wafers consumed in the experiment, to improve the yield, to compensate the thickness difference according to the position of the photosensitive film, There is an advantage that it can be improved.

제 1 도는 일반적인 포토레지스트의 노광전.후의 성분 구성도.FIG. 1 is a compositional view of a general photoresist before and after exposure. FIG.

제 2 도는 본 발명에 따른 반도체소자 제조에 사용되는 노광장치를 설명하기 위한 개략도.FIG. 2 is a schematic view for explaining an exposure apparatus used for manufacturing a semiconductor device according to the present invention; FIG.

※ 도면의 주요부분에 대한 부호의 설명[Description of Drawings]

10 : 축소노광장치 11 : 웨이퍼10: reduction exposure apparatus 11: wafer

13 : 광원 15 : 노광 마스크13: Light source 15: Exposure mask

17 : 샤터 18 : 샤터속도 조절부17: the shutter 18: the shutter speed control section

19 : 대물렌즈 20 : FT-IR19: Objective lens 20: FT-IR

21 : 적외선 발광부 23 : 검출부21: Infrared light emitting part 23:

25 : 광학계 30 : 데이터 처리부25: Optical system 30: Data processing unit

31 : 중앙처리장치 33 : 타임디레이 버퍼31: central processing unit 33: time delay buffer

Claims (2)

임의의 구조의 반도체기판상에 형성되어 있는 하부층상에 감광제를 포함하는 감광막을 도포하는 공정과,A step of applying a photosensitive film containing a photosensitive agent on a lower layer formed on a semiconductor substrate having an arbitrary structure, 상기 감광막을 선택 노광하되, 노광되는 부분에서의 감광제의 성분 변화를 FT-IR로 측정하여 노광 부분의 감광막의 하부층과의 계면에서의 감광제가 변화되는 노광에너지로 노광하는 공정과,Exposing the photoresist film to exposure with exposure energy at which the photoresist is changed at the interface with the lower layer of the photoresist film of the exposed portion by measuring the change in the component of the photoresist at the exposed portion with FT-IR; 상기 감광막을 현상하여 감광막 패턴을 형성하는 공정을 구비하는 반도체소자의 제조방법.And developing the photoresist film to form a photoresist pattern. 웨이퍼를 선택 노광하는 축소노광장치부와,A shaded area for selectively exposing the wafer, 상기 웨이퍼의 감광제의 성분 변화를 파악하는 FT-IR부와,An FT-IR unit for sensing a change in the component of the photosensitive agent of the wafer, 상기 FT-IR부의 분석 데이타를 분석하여 적정 속도로 상기 축소노광장치의 샤터를 조절하는 데이터 처리부를 구비하는 노광장치.And a data processing unit for analyzing the analysis data of the FT-IR unit and adjusting the shade of the reduction exposure apparatus at an appropriate speed.
KR1019960023221A 1996-06-24 1996-06-24 Method of manufacturing semiconductor device and exposure apparatus used therefor Expired - Lifetime KR100403322B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100818424B1 (en) 2006-12-28 2008-04-01 동부일렉트로닉스 주식회사 Automatic exposure energy adjustment

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JPH06177230A (en) * 1992-12-09 1994-06-24 Nippon Bio Ratsudo Lab Kk Noncontact type positioning conveyor
JPH0749312A (en) * 1991-04-30 1995-02-21 Kyushu Electron Metal Co Ltd Wafer positioning method and device for infrared absorption measuring apparatus
JPH0855770A (en) * 1994-08-11 1996-02-27 Toshiba Corp Semiconductor manufacturing device
JPH08111376A (en) * 1994-10-07 1996-04-30 Shin Etsu Handotai Co Ltd Mask aligning method

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JPH0749312A (en) * 1991-04-30 1995-02-21 Kyushu Electron Metal Co Ltd Wafer positioning method and device for infrared absorption measuring apparatus
JPH06177230A (en) * 1992-12-09 1994-06-24 Nippon Bio Ratsudo Lab Kk Noncontact type positioning conveyor
JPH0855770A (en) * 1994-08-11 1996-02-27 Toshiba Corp Semiconductor manufacturing device
JPH08111376A (en) * 1994-10-07 1996-04-30 Shin Etsu Handotai Co Ltd Mask aligning method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100818424B1 (en) 2006-12-28 2008-04-01 동부일렉트로닉스 주식회사 Automatic exposure energy adjustment

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