KR100393959B1 - Uart - Google Patents

Abstract

PURPOSE: A UART(Universal Asynchronous Receiver/Transmitter) is provided to largely reduce a chip size by commonly using a board generator, a modem, and an interrupter while making two UARTs used in a PC into one block. CONSTITUTION: A receiving part(31) comprising the first and the second receiver sends data to a data bus buffer(30) by having two input ports. A transmitting part(34) comprising the first and the second transmitter receives the data from the data bus buffer and output the data to the outside by including two output ports. A line control register(32) controls receiving/transmitting part by each port. A line status register(33) is controlled to each port by the receiving/transmitting part. A FIFO(First Input First Output) controller(38) controls the FIFO of the receiving/transmitting part. The board generator(35) is operated by receiving a data signal from the data bus buffer. The modem(36) transmits/receives the data by deciding a transmitting/receiving status by checking the inputted signal. The interrupter(37) generates an interrupt when an interrupt occurs at the inside.

Description

Asynchronous transmit and receive apparatus {UART}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to data transmission and reception apparatuses, and more particularly, to asynchronous transmission and reception apparatuses with reduced chip area.

Hereinafter, a conventional asynchronous transmission and reception apparatus will be described with reference to the accompanying drawings.

Figure 1 is a schematic block diagram of a conventional asynchronous transmit and receive device (UART).

FIG. 2 is a detailed block diagram of a conventional asynchronous transmitting and receiving device (UART).

The first asynchronous transmission and reception apparatus and the second asynchronous transmission and reception apparatus are constituted as shown in FIG. 1 which shows a schematic block diagram of a conventional asynchronous transmission and reception apparatus.

The first asynchronous transmission and reception apparatus 2 includes a first input signal SIN1 for receiving a signal, a first output signal SOUT1 for outputting a signal, a first clock signal RCLK1 clocked together with an input signal, , A frequency generation signal (BAUDOUT) for generating a frequency, a modem signal (Modem) for checking the state of the modem signal input from the outside and transmitting / receiving data by checking the state to be internally transmitted and received, and an interrupt Signal and is connected to the data bus buffer unit 1 via a data bus line, respectively.

Like the first asynchronous transmitting and receiving apparatus 2, the second asynchronous transmitting and receiving apparatus 3 also receives the second input signal SIN2, the second output signal SOUT2 and the second clock signal RCLK2 A frequency generation signal BAUDOUT, a modem signal Modem and an interrupt signal and is connected to the data bus buffer unit 1 via a data bus line.

Next, a detailed block diagram of a conventional asynchronous transmitting and receiving apparatus is shown. As shown in FIG. 2, the first mobile transmitter / receiver apparatus 2 receives data and sends it to the data bus buffer unit 1 A first transmitter block 4 and a first transmitter block 8 for receiving and transmitting data from the data bus buffer unit 2 and a first transmitter block 4 A first line control register 5 controlled by the first receiver block 4 and the first transmission block 8 and a second line control register 7 controlled by the first receiver block 4 and the first transmission block 8, A first modem unit 9 for generating a frequency and a first modem unit 9 for receiving and transmitting data from a modem signal received from the outside in a state for internally transmitting and receiving data and a first interruption unit (10), a first receiver block (4) and a first receiver block A first first-in, first-out for controlling the first-in first-out of the lances meter block (8) was composed of elected control register (fifo control resister) (11) was connected to the respective data bus lines to a data bus buffer unit (1).

The second asynchronous transmission and reception apparatus 3 includes a second receiver block 12 for receiving data and sending the data to the data bus buffer unit 1 and a second receiver block 2 for receiving data from the data bus buffer unit 1 A second line control register 13 for controlling the second receiver block 12 and the second transmitter block 16 and a second receiver block 16 for controlling the second receiver block 12 A second line status register 15 controlled by the second transmitter block 12 and a second transmitter block 16, a second board generator 14 for generating a clock frequency, A second interrupt unit 18 for internally interrupting data transmission and reception, and a second modem unit 17 for transmitting and receiving data through the second receiver unit 12 and the second transmission unit 16, A second first-in-first-out control register (fifo control (19), which are connected to the data bus buffer unit (1) via data bus lines, respectively. The two asynchronous transmit and receive devices operate as a serial port.

However, such a conventional asynchronous transmission and reception apparatus has the following problems.

Since two asynchronous transmitting and receiving devices are used for transmitting and receiving data, the chip generator area, the modem part and the interrupt block are overlapped to increase the chip area.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to facilitate an internal shared interface and reduce a chip area.

According to an aspect of the present invention, there is provided an asynchronous transmission and reception apparatus including first and second receiver units having two input signal stages and transmitting data to a data bus buffer unit, A line control section for controlling the receiver section and the transmitter section for each port, and a control section for controlling each port by the receiver section and the transmitter section, A first input / output control unit for controlling input / output of a receiver unit and a transmitter unit, a board generator unit for receiving a data signal from the data bus buffer unit, A modem unit for determining a state and transmitting and receiving data, and a modem unit for interrupting an interrupt Including parts interrupt is characterized by consisting of a single transmit and receive device.

Hereinafter, an asynchronous transmission and reception apparatus according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 (a) - (e) are partial block diagrams of an asynchronous transmit and receive unit (UART) of an embodiment of the present invention.

FIG. 4 is a block diagram of a configuration of an asynchronous transmission and reception apparatus (UART) according to an embodiment of the present invention.

3 (a) shows a partial block diagram of a partial configuration block of an asynchronous transmission and reception device (UART) according to an embodiment of the present invention. The receiver section 31 includes a first receiver 31a receiving a first input signal SIN1 And the second receiver 31b receiving the second input signal SIN2 receive the common clock signal RCLK.

3 (b) shows the line control register 32. The line control register 32 includes a first line control register 32a having an output terminal for controlling the receiver unit 31 and a transmitter unit 34 respectively, And the register 32b.

3 (c) shows the transceiver 34, which includes a first transceiver 34a having an output terminal for receiving data from the data bus buffer 30, and a second transceiver 34b FIG.

3 (d) shows a line status register 33, which includes a first line status register 33a having a control input connected to the receiver unit 31 and a control unit 34, And a two-line status register 33b.

3E shows a first-in-first-out control register 38 and a first-in-first-out control register (not shown) having a control output for checking the first-in first-out of the receiver unit 31 and the transmitter unit 34 38a and a second first-in-first-out control register 38b.

Referring to FIG. 4, there is shown an overall block diagram of an asynchronous transmission and reception apparatus according to an embodiment of the present invention. In FIG. 4, two input signals are received in serial and a clock signal (RCLK) A receiver unit 31 configured by first and second receivers 31a and 31b for sending data to the bus buffer unit 30 and a second receiving unit 31 for receiving data from the data bus buffer unit 30 and selectively transmitting data to two output terminals The first and second receivers 31a and 31b of the receiver unit 31 and the transmitter unit 34 and the first and second receivers 31a and 31b of the receiver unit 31 and the first and second transmitters 31a and 31b, A line control register 32 composed of first and second line control registers 32a and 32b for controlling the first and second transmitters 34a and 34b, 1 and the first and second receivers 31a and 31b and the first and second transmitters 34a and 34b, A line status register 33 composed of line status registers 33a and 33b and first and second receivers 31a and 31b of the receiver section 31 and the transmitter section 34 and first and second receivers 31a and 31b, A modem unit 36 for controlling the transmitters 34a and 34b and using the clock frequency in common, a modem unit 36 for transmitting and receiving data by checking the modem signal received from the outside in a state for internally transmitting and receiving data, An interrupt unit 37 for interrupting the interrupts generated by the first and second receivers 31a and 31b and the first and second receivers 31a and 31b of the receiver unit 31 and the transmitter unit 34, (Universal Asynchronous Receiver Transmitter) as a FIFO control register 38 for checking and controlling the first-in first-out selection of the first and the second control circuits 34a and 34b.

The above-described asynchronous transmission and reception apparatus of the embodiment of the present invention has the following effects.

Since the two asynchronous transmission and reception devices used in the personal computer (PC) are made into one block, the board generator portion, the modem portion, and the interrupt portion are commonly used, so that the chip size can be greatly reduced.

Figure 1 is a schematic block diagram of a conventional asynchronous transmitting and receiving device (UART)

FIG. 2 is a detailed block diagram of a conventional asynchronous transmitting and receiving apparatus (UART)

Figure 3 is a partial block diagram of an asynchronous transmit and receive unit (UART) of one embodiment of the present invention.

FIG. 4 is a block diagram of a configuration of an asynchronous transmission and reception apparatus (UART) according to an embodiment of the present invention;

DESCRIPTION OF THE REFERENCE NUMERALS

30: Data output buffer unit 31: Receiver unit

31a: first receiver 31b: second receiver

32: line control register 32a: first line control register

32b: second line control register 33: line status register

33a: first line status register

33b: second line status register

34: Transmitting section 34a: First transmission

34b: second transistor 35: board generator section

36: Modem part 37: Interrupt part

38: First-in-first-out control unit

38a: first first-in-first-out control register

38b: second first-in-first-out control register

Claims (7)

First and second receiver units having two input signal stages and sending data to the data bus buffer unit, A first and a second transmission unit having two output terminals and receiving data from the data bus buffer unit and transmitting the data to the outside, A line control unit for controlling the receiver unit and the transmitter unit for each port, A line status section that is controlled for each port by the receiver section and the transmitter section, A first-in-first-out control unit for controlling the first-in first-out of the receiver unit and the transmitter unit, A board generator unit for receiving the data signal from the data bus buffer unit, A modem unit for checking a signal coming in from the modem and determining a state to be internally transmitted and received and transmitting and receiving data, And an interrupt unit capable of interrupting an interrupt when an internal interrupt is generated. The method according to claim 1, The asynchronous transmitting and receiving apparatus according to any one of claims 1 to 3, wherein the board generator unit, the modem unit, and the interrupt unit are commonly used by the transmitting and receiving apparatuses. The method according to claim 1, Wherein the receiver section is in a block where the first receiver and the second receiver are in one block. The method according to claim 1, Wherein the first and second transmitters are in one block. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 1, Wherein the first line control and the second line control are in one block. The method according to claim 1, The asynchronous transmission and reception apparatus according to claim 1, wherein the first line status and the second line status are in one block. The method according to claim 1, Wherein the first-in-first-out control unit comprises a first first-in-first-out control unit and a second first-in-first-out control unit in one block.