KR100390984B1 - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device that significantly reduces current consumption and noise. The present invention uses a global address line only for an externally input command and operates an input signal within each bank when a predetermined number of internal signals are operated. By increasing the address by counting directly at, access is done in-house without the use of global address lines, thereby reducing the burden of long lines and large capacitances, reducing power consumption, as well as reducing the signal within the bank. It is possible to deliver a stable circuit design.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a device for generating an internal address in a semiconductor memory device having a plurality of banks.

1 is a block diagram of a semiconductor memory device having a conventional internal address generator, which includes a plurality of banks 1, 2, 3, and 4. As shown in FIG. Predecoders 5, 6, 7, and 8 which output signals for selecting the banks are located in the respective banks 1, 2, 3, and 4, and each of the banks 1, 2, 3, and 4 Interconnected by global address lines 10. The address generated by the internal address generator 9 is loaded on the global address line 10.

According to the above configuration, in the SDRAM, the column address is input from the outside together with the read / write command, and the continuous clock continues to operate the predetermined number internally even without the external command signal and the address input. do.

That is, when the external address GA is input to the address multiplexer of FIG. 2, the external signal GA is accepted by the discrimination signal INTAp12 when the external address GA is received, and the internal address BN is sequentially received by the counter of FIG. Create a contiguous address.

When performing a continuous operation, the first address (GAt20 in FIG. 5) accesses all banks 1, 2, 3, 4 through the global address line 10 with external commands, and also sequentially created internally. The internal address (GAt20 in FIG. 5) is also loaded on the global address line 10 to access all banks 1, 2, 3 and 4.

Thus, the global address (GAt20 in FIG. 5) is input to the predecoder of FIG. 4, and when the external address, the control signal EXTYAp20 turns on the NMOS transistors N1 and N2 to generate column addresses Yadd_H and Yadd-L. On the other hand, if it is an internal address, the control signal INTYAp20 turns on the NMOS transistors N3 and N4 to generate column addresses Yadd-H and Yadd-L.

In a conventional configuration that operates as described above, a signal must be loaded on the global address line every operation. The global address line has a long length and a large capacitance, which consumes a lot of electricity, and needs to transmit a signal far from the bank. Problems arise in the back.

In addition, since the global address line is commonly used for the external address and the internal address, if the column address is input externally during the column operation, the conventional DRAM will use the internal address during the burst operation every time the external address is input. Current consumption is high because all banks are accessed.

Accordingly, the present invention has been made in view of the above-described conventional circumstances, and an object of the present invention is to provide a semiconductor memory device which significantly reduces current consumption and noise.

In order to achieve the above object, a semiconductor memory device according to an exemplary embodiment of the present invention includes two or more banks interconnected by global address lines that receive external addresses through an input buffer during a read / write operation. And a predecoder to decode an address signal from the global address line and select a corresponding bank.

It is characterized in that an internal address generating means for generating an internal address is provided in each of the banks to sequentially increase an address in each bank during a burst operation.

1 is a block diagram of a semiconductor memory device having a conventional internal address generator;

2 is a circuit diagram of a conventional address multiplexer;

3 is a conventional counter circuit diagram.

4 is a circuit diagram of a conventional predecoder;

5 is a timing diagram illustrating conventional internal address generation;

6 is a block diagram of a semiconductor memory device according to an embodiment of the present invention;

7 is a circuit diagram of a predecoder employed in an embodiment of the present invention;

8 is a timing diagram illustrating internal address generation according to an embodiment of the present invention;

9 is a block diagram of a semiconductor memory device according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

Banks 1, 2, 3, 4, 20, 21, 22, 23, 40, 41, 42, 43

5, 6, 7, 8, 24, 25, 26, 27, 44, 45, 46, 47: Predecoder

9, 28, 29, 30, 31, 48, 49, 50, 51: Internal address generator

10, 32: global address line

52: global counter

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram of a semiconductor memory device according to an exemplary embodiment of the present invention, wherein reference numerals 20 to 23 denote banks in which memory elements are embedded, and 24 to 27 denote respective banks 20, 21, 22, 23 is a one-to-one correspondence and is a predecoder having a function of selecting a corresponding bank.

The predecoder 24, 25, 26, 27 decodes an address input through a global address line 32 commonly connected to each of the banks 20, 21, 22, and 23 to select a corresponding bank.

The internal circuit of the predecoder 24, 25, 26, 27 is configured as illustrated in FIG. That is, almost the same as in Fig. 4 except that the NMOS transistors N5 and N6 are respectively provided between the source and the ground terminals of the NMOS transistors N3 and N4, and the NMOS transistors N5 and N6 are internal addresses. The on / off operation is opposed to each other by successive addresses Ycnt sequentially created by the generator.

Reference candidates 28 to 31 are internal address generators that are installed in each of the banks 20, 21, 22, and 23 one-to-one and generate internal addresses used when performing continuous access operations (burst operations).

In an embodiment of the present invention, when an external input command is received through the global address line only, and when the internal number is operated by a predetermined number, that is, when the internal address is used, the internal address generating means is operated to increase the address. .

In the above-described embodiment, a counter as shown in FIG. 3 is provided inside the internal address generators 28 to 31, and an internal counter is provided for each bank 20, 21, 22, and 23, thereby providing a corresponding internal counter. The operation is performed by the local address generated by the address generators 28 to 31, but only a part of the address bits (e.g., addresses 0, 1, and 2) are inputted to the respective banks. The internal address generation unit may be provided, and the remaining address bits may not be provided.

The operation of the semiconductor memory device according to the embodiment of the present invention configured as described above will be described with reference to the timing diagram of FIG. 8.

About burst operation In SDRAM, the read / write command and the column address are input externally, and in the continuous clock, the predetermined number is continuously operated without an external command signal and address input. For this operation, an internal address generator 28, 29, 30, 31 is provided for each bank 20, 21, 22, 23, and an address is sequentially formed from an input address signal. The address signals thus generated sequentially select column addresses within each bank.

That is, when the external address GA is input from the address multiplexer (see Fig. 2), it is selected by the counter (see Fig. 3) provided in the internal address generator 28, 29, 30, 31 by the discrimination signal INTAp12. It accepts the internal address (Bn) for the bank and builds consecutive addresses sequentially.

When performing a continuous operation, the first address (GAt20 in FIG. 5) is connected to the predecoder 24, 25, 26, 27 of each bank 20, 21, 22, 23 through the global address line 32 together with an external command. ), And in the predecoder 24, 25, 26, 27, the control signal EXTAp20 turns on the NMOS transistors N1, N2 to generate column addresses (Yadd-H) and Yadd-L. On the other hand, the sequentially generated addresses Ycnt are internally input to the predecoder 24, 25, 26, and 27, and the control signal INTYAp20 turns on the NMOS transistors N3 and N4 so that the column address Yadd- H, Yadd-L).

In more detail, the banks 20, 21, 22, and 23 are used when the global address line 32 is used only when the command is input externally, and when the internal address is operated by a predetermined number, that is, when the internal address is used. Each of the internal address generators 28, 29, 30, and 31 is used.

FIG. 9 is a block diagram of a semiconductor memory device according to another embodiment of the present invention. Each bank 40, 41, 42, 43 is provided with one internal address generator 48, 49, 50, 51. Each of the internal address generators 48, 49, 50, 51 has a counter (see Fig. 3).

In this case, the counter is set for each bank for each bank so as to be operated by a local address generated by the internal address generation unit. In this case, a counter is set in each bank for addresses 0, 1, and 2, and For 3-9, you can have a common counter.

In particular, FIG. 9 continuously receives a signal for a bank operating among the signals of Counter 2 output from the banks 40, 41, 42, and 43 in a full page mode, and operates as a continuous counter. The signal of the non-bank is " L ", indicating that Global Counter 3 is connected to the No. 2 counter output (Nor Gate (NOR) output) of the bank currently being accessed.

According to the present invention as described above, the global address line is used only when the command is input from the outside, and when the predetermined number of operations are performed internally, the address is increased by counting directly in each bank, so that the global address line is not used. Access in-house, thereby reducing the burden of long lines and large capacitances, reducing electricity consumption, and allowing signals to be carried within the bank, enabling stable circuit design.

In addition, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (3)

Pre-decoder having two or more banks interconnected by a global address line that receives an external address through an input buffer during a read / write operation, wherein the bank decodes an address signal from the global address line to select a corresponding bank. A semiconductor memory device having: A semiconductor memory device characterized by providing an internal address generating means for generating an internal address in each bank to sequentially increase an address in each bank during a burst operation The method of claim 1, A semiconductor memory device, characterized in that it is received only through the global address line when an external command is input, and when the internal address is used, the internal address generating means is operated to increase the address. Two or more banks interconnected by global address lines that receive external addresses through the input buffer during read / write operations, A predecoder provided for each of the banks to decode an address signal from the global address line to select a corresponding bank; Internal address generating means provided for each of the banks and generating an internal address for the bank; A decoder which receives and decodes the output from each of the internal address generators; And a counter having an output of the decoder as an input.