KR100383571B1 - Abr service apparatus of packet switching system - Google Patents

Abstract

end. The technical field to which the invention described in the claims belongs

The present invention relates to an available bit rate service apparatus of a packet switched system.

I. The technical problem to be solved by the invention

The present invention guarantees maximum link utilization and minimum cell loss regardless of delay of round trip time of ABR closed loop, minimizes the requirement of ABR queue size by ensuring asymptotic stability of ABR queue, and uses transmission bandwidth between ABR users. By guaranteeing fairness, it guarantees maximum and minimum fairness, which is the ATM Forum standard, and can adapt quickly to changes in the network environment such as changes in the number of ABR users, changes in ABR bandwidth, and ATMs with functions such as EFCI, RR, and ER marking. It provides almost all of the features of the forum traffic management standard, and has an asymptotic stabilization operating point to enable high availability, low cell loss, maximum-minimum fairness allocation, and at multiple time scales, namely VBR and Improves responsiveness and control transient performance against changes in cell level rate of ABR VC and network load changes at cell level arrival and departure of VBR and ABR VC. When implementing a hardware ABR service algorithm that minimizes the number of operations required to compute the algorithm and reduces the complexity of the implementation to eliminate per-VC operations, including per-VC queuing, per-VC calculations, and per-VC table accesses. It not only minimizes the hardware and memory requirements, but also provides accurate computational results.

All. Summary of Solution of the Invention

A forward cell processor for generating a first start signal each time a forward resource management cell is input, and extracting a current cell rate and a minimum cell rate from the resource management cell, and the current every time the first start signal is input; Search whether the subtracted the minimum cell rate from the cell rate is smaller than the specified cell rate, and if so, determines that the input resource management cell has contributed to the number of elements, and forwards the contribution degree contributed by the resource management cell to the number of elements. The resource management cell transmission period is calculated by dividing the first period and the current cell rate by a value, and then accumulating the previous value. When the second start signal is provided, the accumulated contribution degree and the low band filtering parameter at 1 are calculated. Multiplying the subtracted value, adding the total number of elements to the previous number of elements and multiplying the low-band filtering parameter An element number estimator which calculates the number of elements and multiplies the first gain value by subtracting the previous average queue size from the average queue size whenever a third start signal is provided, and the element number estimation unit Dividing by the calculated number of elements, subtracting the target queue size from the average queue size, multiplying the period of the second gain value and the third start signal, and dividing it by the number of elements from the previous specified cell rate. An explicit cell rate calculation unit which subtracts and calculates an explicit cell rate, and an explicit cell rate calculated by the explicit cell rate calculation unit each time a reverse resource management cell is inputted, the specified cell rate and the minimum cell rate extracted from the reverse resource management cell; A reverse cell processing unit for recording and transmitting the calculated explicit cell rate to the reverse resource management cell when the sum is smaller than the sum; Each is characterized in that it comprises a timer that generates the second activation signal is provided to the source can be introduced and estimation, the service on the third start signal generated by the explicit cell rate calculating portion for every two cycles.

la. Important uses of the invention

The present invention is used in a packet switched network.

Description

Available bit rate service device for packet switched system {ABR SERVICE APPARATUS OF PACKET SWITCHING SYSTEM}

The present invention relates to a packet switched system, and more particularly, to an available bit rate (ABR) service apparatus of a packet switched system.

Packet-switched networks include an asynchronous transfer mode (hereinafter referred to as ATM) network and the Internet. In such a packet switched network, fair flow control related to the available bit rate service is a very important factor in the delivery of information on the network.

ATM typically achieves network use for information delivery through the following four service schemes. That is, a constant bit rate (CBR) service method that enables a fixed bit rate service, a variable bit rate (VBR) service method that enables a variable bit rate service while ensuring a constant cell loss rate, and an undefined bit rate (UBR). There are Unspecified Bit Rate service method and ABR service method. The ABR service scheme allows a bit rate of a source to be changed according to network conditions, and allows a source to transmit data according to an available bit rate of a network.

This ABR service method was introduced in ATM networks to support data applications that could not be efficiently supported by transport bandwidth guarantee services such as the VBR service method. These articles or materials include S.Sathaye, "ATM Forum Management Specification, Version 4.0", Feb.1996 and F.Bonomi And KWFendick, "The Rate-Based Flow Control Framework For The Available Bit Rate ATM SERVICE", IEEE Network 9 (2) (1995) p25-39, R. Jain, "Congestion Control And Traffic Management In ATM Networks: Recent Advances And Survey", Computer Network And ISDN Systems 28 (13), (1996) P1723-1738, etc. have.

While most data applications are very irregular and have no way of predicting future data traffic demands, they have definite cell loss requirements and can have tolerances for time changes and unpredictable cell delays. Due to this characteristic, most data applications can change the transmission bandwidth according to the network load. Accordingly, the concept of a traffic service that flexibly adjusts the transmission bandwidth according to the available transmission bandwidth of the network has been introduced. A representative example of such a service is the ABR service of an ATM network.

The ATM Forum adopted a closed-loop rate-based approach for flow control of ABR services. The rate-based flow control scheme uses information fed back from the network to allow each source to control the transmission bandwidth. The feedback information is delivered by a specific control cell called a resource management cell (hereinafter referred to as an RM) cell. For the rate-based flow control, information about a network congestion state should be recorded in the RM cell. The information includes explicit congestion indication (hereinafter referred to as EFCI), relative rate (RR), and explicit rate (Explicit). Rate (hereinafter referred to as ER) information.

Since the ABR service does not require complex traffic characteristic modeling and call admission control in each of the source and the switches, it is expected that the implementation of the ABR service will be easier than the transmission bandwidth guarantee service such as the CBR or VBR service. However, it was determined that the design and implementation of the switch supporting ABR service is much more difficult than expected. This difficulty was in designing scalable, stable and equitable ABR flow control algorithms, especially in the design of ER allocation algorithms in asynchronous and distributed network environments.

On the other hand, the long and varied round trip delays included in the flow control closed loop and the bottlenecks located differently between the ABR VCs make it difficult to design high-performance ER allocation algorithms. ABR queues in a network are difficult to stabilize when the transmission bandwidth of an ABR source is determined according to network state information at different points in time. In particular, when using only the binary feedback mechanism using EFCI marking or RR marking or EFCI marking and RR marking, ABR queues are continuously oscillated at steady state, and their amplitude is the product of round trip time delay and available transmission bandwidth. Increased in proportion to For details, see E. Hernandez-Valencia et al., "Rate Control Algorithms for the ATM ABR Service", European Transactions on Telecommunications 8 (1) (1997) p7-20, and F.Bonnomi, D.Mitra and JB. Serry, "Adaptive Algorithms for Feedback-Based Flow Control in High-Speed, Wide-Area ATM Networks, IEEE J. Select. Areas on Communications 13 (7) (1995) p1267-1283, and KKRatmarkrishnan and Jain," A Binary Feedback Sheme for Congestion Avoidance in Computer Networks with a Connectionless Network Layer, Proc. ACM SIGCOMM'88 (1988) 303-313 et al.

This continuous vibration of the ABR queues causes periodic buffer overflows and underflows, increasing the likelihood of cell loss or the low utilization of the link, which is responsible for the continuous vibrations of the ABR queues generated by this binary feedback mechanism. In order to stabilize gradually, ER flow control method through ER marking was introduced. However, it was still difficult to design a simple form of the ER allocation algorithm that asymmetrically stabilizes the ABR queue, which, in terms of mathematics, resulted in a time-delayed feedback control problem.

In order to guarantee the asymptotic stability and to allow arbitrary control of the closed loop performance, an ER allocation algorithm has been proposed by L. Benmohanmed and S.M.Meerkov who formulate the rate-based flow control problem as a discrete-time feedback control problem. The papers of L. Benmohanmed and S.M.Meerkov for which the ER algorithm is proposed are described in L. Benmohamed and S.M.Meerkov, "Feedback Control of Congestion in Packet Switching Networks: The Case of Single Congested Node", IEEE / ACM Trans. on Networking 1 (6) (1993) p693-708, and L.Benmohamed and SMMeerkov, "Feedback Control of Congestion in Packet Switching Networks: The Case of Multiple Congested Nodes", International Journal of Communication Systems, 10 (5) ( 1997) p227-246 and the like.

The ER allocation algorithm proposed by L. Benmohanmed and S.M. Meerkov is given by Equation 1 below.

In Equation 1, r [k] is ER calculated by the switch at the discrete time k, q [k] is the ABR queue length at the discrete time k, Is the target queue length. And Is the controller gain, Is the maximum round trip time delay for ABR VC Is any constant greater than "0". This algorithm, despite the theoretical basis described in the above paper, was very complex in its implementation and limited in practical use.A.Kolarov and G.Ramamurthy, "A Control Theoretic Approach to the Design of close Loop Rate Based Flow Control for High Speed ATM Networks, Proc. IEEE INFOCOM'97 1 (1997), p293-301, describes this difficulty, ie the ER allocation algorithm described above To time (j = 0 to We have to maintain the value of the ER term and have to perform a large number of floating point multiplications in every discrete time slot.

Whereas S.Chong, "Second-Order Rate-Based Flow Control with Dynamic Queue Threshold for High-Speed Wide-Area ATM Networks", preprint 1997, and A.Elwalid, "Analysis of Adaptive Rate-Based Congestion Control for High" Speed Wide-Area Networks, Proc. IEEE ICC'95 (1995) P1948-1953 proposed another ER allocation algorithm based on control theory in a simpler form as shown in Equation 2 below.

In S. Chong's paper, the proposed algorithm proposes a sufficient and sufficient condition for the closed-loop system to be gradually stabilized when the algorithm of Equation 2 is applied. It extends to the general case with round trip time delay.

S.Chong, R. Nagarajan and YTWang, in the paper "Designing Stable ABR Flow Control with Rate Feedback and Open-Loop Control: First-Order Control Case", Performance Evaluation 34 (4), We proposed a much simpler ER allocation algorithm.

Here, [x] ⁺ = max [x, 0], which means to select a larger value between "x" and "0".

In S. Chong's paper relating to Equation 2, two different stabilization conditions are derived. One of them is sufficient condition for the general case with heterogeneous round trip time delay, and the other is necessary sufficient condition for special case with homogeneous round trip time delay.

Compared with Equation 1, a common drawback of the ER allocation algorithm disclosed in Equations 2 and 3 is that the controller gain and queue length thresholds are available for the transmission bandwidth and remote bottleneck VCs available for ABR traffic. The ABR queue length may undesirably converge to "0" because the link is not sufficiently available at the equilibrium point if it is not properly selected according to instantaneous recognition at the fraction of the transmission bandwidth.

Remote bottleneck VCs on a link are VCs that cannot be divided equally on that link because bottlenecks occur on other links in the path unless their transmission rate is limited by their Peak Cell Rate (PCR). Conversely, if you apply an algorithm like Equation 1, there is no such thing as the undesirable equilibrium point mentioned above.

Accordingly, Applicant guarantees maximum link utilization and minimum cell loss regardless of delay of round trip time of ABR closed loop, minimizes the requirement of ABR queue size by ensuring asymptotic stability of ABR queue, and transfers between ABR users. By ensuring fairness of bandwidth utilization, it guarantees maximum and minimum fairness, which is an ATM forum standard, and adapts quickly to changes in the network environment such as changes in the number of ABR users and changes in ABR bandwidth. It also provides functions such as EFCI, RR, and ER marking. It provides almost all of the features of the ATM Forum traffic management standards, including asymptotic stabilization operating points, which enable high availability, low cell loss, and maximum-minimum fair rate allocations. Responsiveness and control transients for cell-level rate change of VBR and ABR VC and network load change at cell level arrival and departure of VBR and ABR VC ABR service algorithms that increase performance, minimize the number of operations required to compute algorithms, and reduce implementation complexity and scalability to eliminate per-VC operations, including per-VC queuing, per-VC calculations, and per-VC table accesses. Patent Application No. 60 / 157,420 filed in the United States of America on October 2, 1999, after the invention of the present inventors, et al., Et al. Is disclosed.

However, it was required to implement the patented algorithm in hardware as described above, and in the implementation it was required to minimize the amount of hardware or memory requirements. It was also required that the calculation be accurate when calculating the algorithm.

As described above, the present applicant guarantees maximum link utilization and minimum cell loss regardless of delay of round trip time of ABR closed loop, and minimizes the requirement of ABR queue size by ensuring asymptotic stability of ABR queue. By ensuring the fairness of the transmission bandwidth utilization between the two, it guarantees the maximum and minimum fairness, which is the ATM forum standard, and can adapt quickly to the change of the network environment such as the change of the number of ABR users and the change of the ABR bandwidth, and the like, such as EFCI, RR, ER marking. Almost all of the features set forth in the ATM Forum traffic management standards, including those available, provide an asymptotic stabilization operating point that enables high availability, low cell loss, maximum-minimum fairness allocation, and multiple time scales. In other words, responsiveness and response to changes in cell level rate of VBR and ABR VC and network load change on arrival and departure of cell level of VBR and ABR VC An ABR service algorithm that improves transient performance, minimizes the number of operations required to compute the algorithm, and reduces the complexity of the implementation and eliminates the scalability of implementations, including per-VC queuing, per-VC calculations, and per-VC table accesses. The patent application has been required to implement such an ABR service algorithm in hardware, and the implementation was required to minimize the hardware or memory requirements. In addition, the calculation of the ABR service algorithm is required to be accurate.

Accordingly, an object of the present invention is to provide an ABR apparatus of a packet switching system capable of providing accurate calculation results as well as minimizing hardware or memory requirements when implementing the ABR service algorithm in hardware.

1 is a block diagram of a packet switched network according to a preferred embodiment of the present invention;

2 is a configuration diagram of an input / output card of the exchanger of FIG. 1;

3 is a block diagram of an ABR service apparatus according to a preferred embodiment of the present invention;

4 is a configuration diagram of an RM cell;

5 is a configuration diagram of a forward cell processor of FIG. 3;

6 is a configuration diagram of a forward cell decoder of FIG. 5;

7 is a configuration diagram of a cell element count unit of FIG. 6;

8 and 9 illustrate a cell buffering process;

10 is a configuration diagram of an EFCI marking unit of FIG. 6,

11 is of FIG. 3 Configuration diagram of the estimator,

12 is a flowchart illustrating processing of the δ calculation unit and the δ operation unit of FIG. 11;

13 is of FIG. 11 A drawing showing the operation procedure of the calculation unit,

14 is a configuration diagram of the ER engine of FIG.

15 is a configuration diagram of a gain selector of FIG. 14;

16 is a processing flowchart of the gain selector of FIG. 14;

FIG. 17 is a view illustrating an operation procedure of the ER engine of FIG. 3;

18 is a configuration diagram of a reverse cell processor of FIG. 3;

19 is a configuration diagram of a reverse cell decoder of FIG. 18;

20 is a configuration diagram of an N _T correction unit.

The present invention for achieving the above object is a forward cell processing unit for generating a first start signal every time the forward resource management cell is input, and extracts the current cell rate and the minimum cell rate from the resource management cell, Each time a start signal is input, it is searched whether the subtraction of the minimum cell rate from the current cell rate is smaller than a specified cell rate. In this case, it is determined that the input resource management cell has contributed to the number of elements. The contribution amount contributed to the number of elements is calculated by dividing the forward resource management cell transmission period by the value multiplied by the first period and the current cell rate, and then accumulating the previous value, and accumulating the accumulated value every time the second start signal is provided. Multiplying the contribution and subtracting the low pass filtering parameter from 1, adding the total number of elements to the previous number of elements and the An element number estimator which calculates the number of elements by multiplying the inverse filtering parameters and multiplies the first gain by subtracting the previous average queue size from the average queue size whenever a third start signal is provided; Dividing this by the number of elements calculated by the element number estimator, subtracting the target queue size from the average queue size, multiplying the period of the second gain value and the third start signal and returning the result to the element number The divided cell rate is calculated by subtracting from the previous specified cell rate an explicit cell rate calculating unit, and the explicit cell rate calculated by the explicit cell rate calculating unit each time a reverse resource management cell is inputted from the reverse resource management cell. If the sum of the extracted explicit cell rate and the minimum cell rate is smaller, the calculated explicit cell rate is recorded in the uplink resource management cell and transferred. A reverse cell processor for transmitting and generating the second start signal for each of the first periods, and providing the second number of start signals to the element number estimator; It characterized in that it comprises a timer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. While many specific details are set forth in the following description and in the accompanying drawings, to provide a more general understanding of the invention, these specific details are illustrated for the purpose of illustrating the invention and are not meant to limit the invention thereto. And a detailed description of known functions and configurations that may unnecessarily obscure the subject matter of the present invention will be omitted.

ABR service apparatus employing the ABR service algorithm will be described.

First, referring to FIG. 1, which illustrates a packet switched network configuration for explaining an ABR service scheme according to a preferred embodiment of the present invention, the packet switched network includes a plurality of interconnected switches E1 to E3. Each of the exchangers E1 to E3 is connected to a plurality of sources. In FIG. 1, the first to Nth sources S1 to SN are connected to the first switch E1, and the M to the second switch E2. To Lth sources SM to SL are connected. Each of the sources transmits and receives data through corresponding exchanges. The data sent to the source includes a number of nodes and is delivered to the destination via a path called a VC path.

Typically, the ABR service uses an RM cell to inform the source of the available transmission bandwidth to the network, and the RM cell is generated at the source or switch. In the preferred embodiment of the present invention, the RM cell is used to process the RM cell generated at the source. Explain only. In addition, the RM cell generated at the source is transmitted to the destination via the VC path, and the cell transmission direction is referred to as a forward. In addition, the destination transmits the received RM cell back to the source and transmits the cell in a backward direction. In the RM cell transmitted in the reverse direction, the exchanges record the information of the transmission bandwidth allowable to the source and transmit the information to the source, and the source appropriately adjusts the amount of information transmitted to the destination by referring to the information on the transmission bandwidth. The information on the transmission bandwidth includes an explicit cell rate (hereinafter referred to as ER), which is information on available transmission bandwidth, a congestion indication (hereinafter referred to as CI) indicating that congestion has occurred, There is a no increase (hereinafter referred to as NI) that does not increase the transmission bandwidth further. EFCI also shows congestion in data cells.

As described above, each exchange calculates the available transmission bandwidth for the ABR service, records it in the reverse RM cell, and transmits it to the source side. An ABR service device that performs this function is provided in the input / output port card of each exchange.

Referring to FIG. 2 illustrating the configuration of the input / output port card, the input / output port card 100 includes an input / output buffer manager 102, an ABR service engine 104, and an output interface 106. The input / output buffer management unit 102 is connected to the switch and manages input / output queuing. In addition, the queue input signal is provided to the ABR service engine 104 at the time of queue writing and queue reading. Provides a cue signal to the ABR service engine 104. The ABR service engine 104 batch processes an ABR algorithm and related functions for an ABR service according to a preferred embodiment of the present invention based on various parameters provided by the microprocessor 108. The output interface 106 also performs a user network interface function of the ATM layer.

Referring to FIG. 3 illustrating a block diagram of the ABR service engine 104 as described above, the forward cell processor 200 of the ABR service engine 104 receives a forward cell, and the cell is a forward RM cell. Generated from source, if no CRC error, cardinality The first start signal is provided to the estimator 202. In addition, the forward cell processor 200 extracts a current cell rate (hereinafter referred to as a CCR) and a minimum cell rate (hereinafter referred to as an MCR) from the input forward RM cell. The estimation unit 202 is provided. Also, when the EFCI congestion occurs, the forward cell processor 200 may mark and output the EFCI region of the data cell among the input forward cells.

remind The estimator 202 indicates that each time the forward cell processor 200 provides the first start signal, the received RM cell To determine whether the reverse RM cell When δ is calculated, the δ, which is the degree of contribution, is calculated, and δ is accumulated until a second start signal periodically provided by the timer 210 is generated. Used for estimation. remind The estimator 202 according to the second start signal Is estimated and provided to the ER engine 208. remind In the estimation of The estimator 202 uses δ and the KER value provided by the ER engine 208.

The ER engine 208 calculates the ER according to the third start signal periodically provided by the timer 210 and provides the ER to the reverse cell processing unit 212, so that the reverse cell processing unit 212 provides the RM cell in the reverse cell. Allows you to record the calculated ER.

The queue counter 206 uses the queue write signal and the queue read signal provided by the input / output buffer manager 102 to provide the ER engine unit 208 with the queue change count, which is information on the current queue size and the number of times the queue has been changed. do. In addition, the queue counter 206 provides the forward cell processor 200 with information about the queue size so that the forward cell processor 200 detects EFCI congestion and marks the EFCI. And the queue counter 206 is information about the queue size so that the reverse cell processing unit 212 can detect the congested state and very congested state for the RR service and accordingly mark NI, CI in the RM cell of the reverse cell May be provided to the reverse cell processing unit 212.

The reverse cell processing unit 212 receives a reverse cell and if the reverse cell is an RM cell, searches whether the ER calculated by the ER engine is smaller than the sum of the ER and MCR included in the provided RM cell. The ER calculated by the ER engine is recorded in the RM cell. In addition, the reverse cell processor 212 receives a queue size to detect a congestion state and a very congestion state, and thus marks NI and CI on the reverse RM cell. In addition, when the ER recording and the NI and CI marking are completed as described above, the reverse cell processing unit 212 recalculates the CRC for the corresponding RM cell, records the result, and outputs the result.

The timer 210 generates the second start signal every predetermined first period to In addition to the estimator 202, a third start signal is generated every predetermined second period and provided to the ER engine unit 208.

In addition, the microprocessor interface 204 may use various parameters provided by the microprocessor 108. The estimation unit 202 and the ER engine unit 208 are provided. Various parameters provided as described above are latched to a register or the like, which is already a commonly used technique, and thus a detailed description thereof will be omitted.

Now, each configuration of the ABR service engine 104 configured as described above will be described in more detail. First, referring to FIG. 4 illustrating the structure of the RM cell, the RM cell includes an ATM cell header, a protocol identifier, a message type, an ER, a CCR, an MCR, a queue length, It consists of a sequence number and a CRC. The ATM cell header includes a Payload Type Identifier (PTI) that defines a payload type, one bit of the PTI being used as an EFCI. The message type includes a DIR (direction) indicating whether the cell is in a forward direction, that is, a forward cell or a reverse cell, a BN cell indicating whether the cell is generated from a source or a destination, and a congestion identification. And NI indicating to suppress further increase in transmission bandwidth. The CCR is a transmission bandwidth recorded when the source first generates an RM cell. The MCR is the minimum transmission bandwidth of each VC recorded when the source generates an RM cell. The ER is the available transmission bandwidth recorded by the ABR service engine of each exchange when the RM cell in which the source generated the RM cell is transmitted in the reverse direction. The ER recording method stores the newly calculated available transmission bandwidth only when the available transmission bandwidth calculated by the ABR service engine is smaller than the previously available available bandwidth. The source is thus informed of the smallest available transmission bandwidth in the VC path.

Referring to FIG. 5, which shows the configuration of a forward cell processor 200 that processes a RM cell among the forward cells, the UTOPIA interface 300 of the forward cell processor 200 provides a UTOPIA interface. The forward cell decoder 302 receives a start of cell (SOC) signal, which is a signal for starting a cell, and a forward cell from the UTOPIA interface 300, and searches whether the cell is a data cell or an RM cell. If it is a cell, search whether the RM cell is generated from the source. If the RM cell is generated from the source, search whether the RM cell has a CRC error, and generate a first start signal when there is no CRC error. In addition to the estimation unit 202 and extracts the CCR and MCR included in the RM cell The estimation unit 202 is provided. The RM cell decoder 302 also marks the EFCI on the input forward data cell when the congestion detector 306 provides the congestion signal. The CRC detector 304 receives the forward cell, searches for the CRC error, and provides the result to the RM cell decoder 302. And the congestion detector 306 compares the current queue length and congestion thresholds g EFCI _EFCI the current queue length is greater than g _EFCI EFCI generating a congestion signal to provide the forward cell decoder 302.

The configuration and operation of the forward cell decoder 302 will be described in more detail with reference to FIG. 6, which shows a detailed configuration diagram of the forward cell decoder 302. The cell element counting unit 400 counts the forward clock from the time when the SOC is generated and outputs the cell count. The cell element counting unit 400 is reset according to a reset signal generated whenever the cell count corresponds to the entire RM cell. In this case, a 4 or 5 byte header may be added at the beginning of the cell. Even though the header is added, the cell count may correspond to the PTI position, DIR and BN position, CCR position, and MCR position in the RM cell exactly. In order to ensure that the cell element count unit 400 subtracts the cell type / 2 from the cell count, the cell element multiplexer 414 aligns the input forward cells.

Referring to FIG. 7, which shows a detailed configuration diagram of the cell element counting unit 400, an input terminal D of a flip-flop D is connected to a power source, an SOC is input to a clock, and the reset signal is a reset terminal. Is entered. Accordingly, the flip-flop D generates a cell start signal that becomes high when the SOC is input and becomes low when the reset signal is input. The cell start signal and the reset signal are input to the AND gate, and the AND gate AND generates a signal for resetting the counter CNT when both signals are low at the same time. The counter CNT counts the forward clock and is reset whenever the cell start signal and the reset signal are generated at the same time. The output of the counter CNT and the cell type / 2 are input to the subtractor AD, which subtracts the cell type / 2 from the output of the counter ANT and outputs the cell count. The cell type / 2 may be provided by the microprocessor 108.

The cell count generated as described above is input to the comparator 402. The comparison unit 402 generates a PTI clock when the input cell count corresponds to a PTI position in an RM cell, generates a DIR-BN clock when corresponding to a message type position, and generates a CCR when corresponding to a CCR position. Generate a clock and generate an MCR clock when it corresponds to the MCR position. In addition, an AND clock is generated when the cell count corresponds to the length of all cells. The PTI clock, the DIR-BN clock, the CCR clock, the MCR clock, and the clock output by the comparator 402 are output in synchronization with the forward clock through the first register unit 404. The end clock synchronously outputted through the first register unit 404 is inverted through the inverter INV and provided as a reset signal of the cell enumeration counting unit 400. The PTI clock synchronously outputted through the first register unit 404 is input to the clock of the PTI register 406, the DIR-BN clock is input to the clock of the DIR-BN register 408, and the CCR. The clock is input to the clock of the CCR register 410 and the MCR clock is input to the clock of the MCR register 412.

The cell buffer multiplexer 414 reads a 16-bit cell latched to the second register 420 if the header added is 4 bytes, and 8 bits of a cell latched to the second register 420 if the header is 5 bytes. And 8 bits of the cell latched to the first register 418. The cells are sorted and output regardless of whether the added header is 4 bytes or 5 bytes.

This will be described in more detail with reference to FIGS. 8 and 9 illustrating the RM cell buffering process of the first and second registers 418 and 420. Since the RM cell is buffered in the first and second registers 418 and 420 in 16 bits by 8 bits, the first two bytes of the RM cell are aligned as shown in FIG. 6 when the additional header consists of 4 bytes. In the case where the header is added but consists of 5 bytes, as shown in Fig. 7, the first two bytes of the RM cell are shifted and buffered. Types of the added header are classified into cell types. When the 4-byte header is added, the cell type is 0100, and when the 5-byte header is added, the cell type is 0101. In other words, when looking at the LSB of the cell type, the type of the header added to the RM cell can be determined.

Accordingly, the cell buffer multiplexer 414 receives the LSB of the cell type and if the LSB is 0, reads 16 bits buffered in the second register 420 as it is and provides the second register 416 to the second register unit 416. If 1, 8 bits of the data buffered in the second register 420 and 8 bits of the data buffered in the first register 418 are read and provided to the second register unit 416.

As described above, the cell buffer multiplexer 414 aligns the RM cells and outputs them to the second register unit 416, and the second register unit 416 synchronizes the input RM cells with the forward clock to synchronize the PTI register 406. , DIR_BN register 408, CCR register 410, and MCR register 412. Each of the PTI register 406, DIR_BN register 408, CCR register 410, and MCR register 412 receives an RM cell from the second register unit 416, and includes a PTI clock, a DIR_BN clock, a CCR clock, and an MCR. Latch the data entered when the clock is generated. Accordingly, the PTI register 406, DIR_BN register 408, CCR register 410, and MCR register 412 each latch a PTI, data type, CCR, MCR from an RM cell, and the CCR and MCR It is input to the estimating unit 302.

The data type is input to the RM cell detector 428, and the RM cell detector 428 searches for DIR and BN included in the data type to detect whether the corresponding cell is a forward RM cell and originated from a source. At this time, if the corresponding cell is in the forward direction and is generated from the source, the RM start signal is generated and provided to the EFCI marking unit 430 and the AND gate. The AND gate generates a first start signal when a CRC error detection signal indicating that a CRC error is not detected and an RM start signal are simultaneously generated. The estimation unit 302 is provided.

The EFCI marking unit 430 marks the EFCI included in the PTI of the cell when the input cell is a data cell, that is, a congestion signal is generated while the RM start signal is not provided and the cell start signal is generated. However, when the header is added to the cell, the PTI part may pass through the upper 8 bits or the lower 8 bits when passing through the first to fifth registers 418 to 426. The EFCI marking unit 430 adaptively marks EFCI in this case, which will be described with reference to FIG. 10. When the 4-byte header is added to the cell, the PTI passes through the upper 8 bits when passing through the first to fifth registers 418 to 426, and the PTI when 5-byte header is added to the cell. Passes through the lower eight bits when passing through the first through fifth registers 418 through 426. The first and gate AND1 of the EFCI marking unit 430 provides 1 to the first oracle OR1 when the congestion signal and the cell type LSB are 1 at the same time. The first OR gate OR1 outputs the bit corresponding to the EFCI of the PTI and the output of the first AND gate AND1. That is, the bits corresponding to the EFCI of the PTI passing through the upper 8 bits are marked as 1 when the congestion signal and the LSB are 1 at the same time. The second and gate AND2 of the EFCI marking unit 430 provides 1 to the second oracle OR2 when the LSB of the cell type inverted by the congestion signal and the inverter INV is 1 at the same time. The second OR gate OR2 outputs the bit corresponding to the EFCI of the PTI and the output of the second AND gate AND2. That is, the bit corresponding to the EFCI of the PTI passing through the lower 8 bits is marked as 1 when the congestion signal is 1 and the LSB is 0.

The first to fifth registers 418 to 426 buffer and output the input forward cells, and buffer and output the SOC and empty signals.

Now using the first start signal and the CCR and MCR provided by the forward cell processing unit 200 To estimate The configuration and operation of the estimator 202 will be described in detail with reference to FIG.

remind The estimator 202 determines that the RM cell provided whenever the forward cell processor 200 provides the first start signal. Δ operation determining unit 500 for determining whether or not to contribute to the RM cell, If it is determined to contribute to the δ calculation unit 502 that calculates the contribution degree and accumulates in the previous value and outputs, and using the δ calculated and accumulated by the δ operation unit 502 Compute and output an estimate of It consists of arithmetic unit 504.

The δ calculation unit 500 searches whether the KER is smaller than the CCR-MCR, and if the KER is smaller than the CCR-MCR, the RM cell is determined. And a control signal S for calculating δ. The first register 506 of the δ calculation unit 500 provides the KER provided from the ER engine 208 to the water system converter 508 in synchronization with the SOC. The number system converter 508 converts the input KER into a 32-bit floating point format and inputs it to the B input terminal of the first adder 510 as ER. The first adder 510 receives MCR as the A input terminal, ER as the B input terminal, adds the MCR and ER, and outputs the MCR to the B input terminal of the comparator 512 through the C output terminal. The comparator 512 receives CCR as the A input terminal, receives the value obtained by adding MCR and ER to the B input terminal, compares the CCR with the MCR and ER, and provides the result to the AND gate 514. do. The AND gate 514 generates a high output when the first start signal is generated and the comparator 512 outputs a signal indicating that a value obtained by adding MCR and ER is less than CCR. It is input to the second register 516. The second register 516 outputs the output of the AND gate 514 as an S signal according to END_l_clk. That is, the S signal becomes 1 when the KER is smaller than the CCR-MCR and there is no CRC error in the input cell, and the S signal is input to the δ calculation unit 502.

The δ calculation unit 502 has a first period, that is, RM cells provided during the estimation period Δ, which contributed to, is calculated and accumulated according to Equation 4.

In Equation 4, N _rm is negotiated at connection establishment with a period of transmitting RM cells in a forward direction. In addition, a value obtained by dividing the cycle of N _rm first cycle of the second start signal, that is, N _rm / the first period may be provided by microprocessor 108.

The number system converter 518 of the δ operator 502 converts the CCR provided by the forward cell processor 200 into a 32-bit floating point format and inputs it to the A input terminal of the divider 520. The divider 520 receives the output of the number system converter 518 and a value for N _rm / second start signal period when the MCR clock is generated, and converts the N _rm / second start signal period to the number system conversion. The output is divided by the output of the unit 518 and output to the third register 522. The third register 522 latches the output of the divider 520 and inputs it to the B input terminal of the second adder 524 when the DONE signal, which is an operation completion signal of the divider 520, is generated. When the DONE signal of the divider 520 is input, the second adder 524 loads and adds the previous δ _prev and the output of the third register 522 to the fourth register 526. . The fourth register 526 of the second adder 524 according to the clock provided by the AND gate 528 when the DONE signal and the S signal which are the operation completion signals of the second adder 524 are 1 at the same time. The output is latched and output as δ. Δ is It is provided to the calculator 504 and is provided to the second adder 524 as δ _prev . Here, the δ operation unit 502 uses a method of outputting δ calculated according to the S signal instead of starting the calculation of δ according to the S signal, which is to implement the calculation of δ in real time.

The divider 520 and the second adder 524 are reset according to the reset signal provided by the inverter 530 and the AND gate 532 when the reset signal and the second start signal occur simultaneously. And accumulated δ is reset to zero each time the second start signal is generated.

Herein, operations of the? Operation determining unit 500 and the? Operation unit 502 of the queuing connection estimating unit 202 will be described with reference to the flowchart of FIG. 12. Whenever the RM operation unit 500 receives an RM cell, the δ operation determination unit 500 searches whether the KER is smaller than the CCR-MCR. At this time, if KER is smaller than CCR-MCR, the process proceeds to step 602, where δ operation unit 502 is calculated and accumulated δ.

Using δ calculated in the same manner as above To compute The calculation unit 504 will be described. The controller 534 according to the second start signal In addition to starting the calculation unit 504, Overall operation of the operation unit 504 is controlled. remind The 1-α operator 536 of the calculator 504 The low band filtering parameter α of the expression is input and subtracted from 1 to the register unit 538. The register unit 538 is a whole Computed values of N _T and α and 1- α Value Various operation results provided by the _prev and the second selector 546 are received and latched. The first selector 540 receives a plurality of values from the register unit 538, selects some of the values according to the control of the controller 534, and provides them to the multiplier 542 or the third adder 544. The multiplier 542 and the third adder 544 multiply or add values provided by the first selector 540 and provide a result of the calculation to the second selector 546. The second selector 526 provides the output of the multiplier 542 and the third adder 544 to the limiter 548 or the register 538 under the control of the controller 534. The limiter 548 remains as long as the value provided by the second selector 546 is greater than 0 and less than n _T. Output as, limit to 0 if less than 0 Output as, which was greater than the limit to the n _T n _T Output as. The output of the limiter 548 was previously sign _It is provided to the register part 538 as _prev .

The controller 534 is in accordance with Equation 5 The first and second selectors 540 and 546 are controlled to calculate a. This control process will be described with reference to FIG. 13.

In the first step of the calculation procedure of FIG. 13, the controller 534 is configured by n _T provided from the register unit 538 by the first selector 540. The first selector 540 is controlled to provide the third adder 544 to the multiplier 542 while providing (1-α) and δ to the multiplier 542. According to the control of the controller 534, the first selector 540 is the n _T and Is provided to the third adder 544 and (1-α) and δ are provided to the multiplier 542. The third adder 544 is equal to n _T. Is added to the second selector 546 as ①, and the multiplier 542 multiplies the value of (1-α) by δ and provides it to the second selector 546 as ②. The controller 534 controls the second selector 546 to provide ① and ② to the register unit 538.

In the second step of the calculation procedure, the controller 534 controls the first selector 540 such that the first selector 540 provides the multiplier 542 with? And? Latched by the register unit 538. According to the control, the first selector 540 provides the first and the multipliers 542, and the multiplier 542 multiplies the first and α and provides it to the second selector 546 as. The controller 534 controls the second selector 546 to provide ③ to the register unit 538.

In the third step of the calculation procedure, the controller 534 provides the first selector 540 so that the first selector 540 provides 3 and 2 latched by the register unit 538 to the third adder 544. To control. According to this control, the first selector 540 provides ③ and ② to the third adder 544, and the third adder 544 adds the ③ and ② to each other. As a second selector 546. The controller 534 is the Is controlled to output to the limiter 548.

As described above, the controller 534 is Since the calculation is not performed in real time but every first period, the third adder 544 or the multiplier 542 is used a plurality of times in accordance with the calculation procedure composed of the first to third steps in order to reduce the hardware requirement.

The limiter 548 is calculated through the above operation procedure Limit to a value between 0 and n _T to final Output as. The limiter 548 outputs Is input to the ER engine 208.

remind As the first to third adders 510, 522, and 544 and the multiplier 542 used in the estimator 202, an operator that performs floating point calculation may be used to increase the accuracy of the calculation.

now Estimator 202 provides The process of calculating the ER using the following will be described with reference to FIG. 14 which shows a configuration diagram of the ER engine 208. The numerical system converter 700 of the ER engine 208 compares the target queue size q _T provided by the microprocessor 114 with the second period Δ and ER through the microprocessor interface 204. A K is received and converted into a 32-bit floating point format and provided to the first selector 704. And the water system converter 700 Estimator 302 provides And queue the counter 206 provides a queue change count and queue size, N _T corrector (did not shown) provides input to the n _diff amount of change in the N _T received by converting the 32-bit floating-point format, the first To the selector 704.

In addition, the gain selector 702 may register g _TH , which is a queue size for gain selection provided by the microprocessor 114, and gains A ₀ , A ₁ , B ₀ , B _1, and a register part through the microprocessor interface 204. A current cue value provided through 714 is input and the g _TH and q are compared to obtain the gain A, B if q is less than g _TH and A ₁ , B ₁ has not been previously selected as gain A, B. A ₀ , B ₀ is selected and provided to the first selector 704, and if q is less than g _TH , but A ₁ , B ₁ has previously been selected as gain A, B or q is greater than g _TH , gain A A ₁ and B ₁ are selected as B and provided to the first selector 704.

The operation of the gain selector 702 will be described with reference to FIG. 15, which shows a block diagram of the gain selector 702. The adder 800 of FIG. 15 receives q and g _TH and receives q and g _TH. Is subtracted from the comparator 802. The comparator 802 searches if the subtraction result is less than zero. The comparator 802 outputs 0 when the subtraction result is less than zero, and outputs 1 when the subtraction result is greater than zero. The output of such comparator 802 is provided to flip-flop 804 as a clock. The flip-flop 804 is initially reset to output 0, and then outputs 1, which is input to the input terminal at the rising edge of the clock, to the output terminal. Since q is gradually increased from 0, the flip-flop 804 outputs 0 from the beginning until q reaches g _TH , and then outputs 1 to whatever value q has. The output of the flip-flop 804 is input to the first and second selectors 806 and 808 as selection signals. Wherein the first and the second selector 806, respectively A _0, A ₁ and enter the B _0, B ₁ receives the output of A ₀ and B ₀ when the output is 0, the flip-flop (804) A, as B, When the output of the flip-flop 804 is 1, A ₁ and B ₁ are output as A and B.

The operation of the gain selector 702 will be schematically described with reference to the flowchart of FIG. In step 900, the gain selector 702 proceeds to step 902 if q is less than g _TH , and otherwise proceeds to step 904 to select and output A ₁ and B ₁ as A and B. In step 902, the gain selector 702 searches for an initial state in which A ₁ and B ₁ are not selected as A and B previously. In this case, the gain selector 702 proceeds to step 906 and selects and outputs A ₀ and B ₀ as A and B.

As described above, the use of different gains in the initial and non-initial states allows the ER values to quickly converge to a stable ER value in an unstable initial state, and once the ER values converge to a stable ER value, This is to minimize the vibration of the value.

In FIG. 14, the first selector 704 converts q _T , Δ, , The number of cue changes, the queue size, n _diff and the gains A and B provided by the gain selector 702 and some of the calculation results provided by the register unit 714 to control the ER engine controller 730. The multiplier 706, the divider 708, and the adder 710 are provided. The multiplier 706, the divider 708, and the adder 710 each multiply, divide, and add values provided by the first selector 704, and output the operation result to the second selector 712. The second selector 712 provides the register unit 714 with operation results of the multiplier 706, the divider 708, and the adder 710 under the control of the ER engine controller 730. The register unit 714 includes a first register unit 716, a second register unit 722, and a third register unit 728. The first register unit 716 includes a second selector 712. The first register 718 for latching q, which is the average queue size, to be provided to the first selector 704 and the gain selector 702, and q _prev , which is the previous q, is latched to the first selector 704. It consists of a second register 720 for providing. The second register unit 722 feeds back the various calculation results provided by the second selector 712 to the first selector 704. The third register 728 latches the ER provided by the second selector 712 to the first selector 704, and the ER latched by the third register 724. Is composed of a fourth register 726 which provides the first selector 704 to ER _{prev which} is the previous ER.

The ER engine controller 730 controls the first selector 704 and the second selector 712 so that the multiplier 706, the divider 708, and the adder 710 calculate the ER according to Equation 6.

The ER engine controller 730 controls the first selector 704 and the second selector 712 so that the multiplier 706, the divider 708, and the adder 710 calculate an ER according to Equation 3 above. The process will be described according to the calculation procedure shown in FIG.

In the first step of the calculation procedure of FIG. 17, the ER engine controller 730 provides the divider 708 with the number of queue changes and the queue size provided by the water system converter 700. And control the first selector 704 to provide n _diff to the adder 710. Accordingly, the first selector 704 provides the divider 708 with the number of cue changes and the queue size. And n _diff to adder 710. Accordingly, the divider 708 divides the queue size by the number of cue changes and provides it to the second selector 712 as q, and the adder 710 adds the queue. Corrected by adding and n _diff As a second selector 712. The ER engine controller 730 feeds back the output q of the divider 708 to the first selector 704 through the first register 714 of the first register 722 and the adder 710. Calibrated output of The second selector 712 is controlled to feed back to the first selector 704 through the second register unit 722. Here, q is provided to the gain selector 702 so that the gain selector 702 can select A and B by comparing q with g _TH .

In the second step of the calculation procedure, the ER engine controller 730 provides the multiplier 706 with a? Value provided by the numerical system converter 700 and a gain B selected and output by the gain selector 702. The first selector 704 is controlled. According to the control, the first selector 704 provides the Δ value and the gain B to the multiplier 706, and the multiplier 706 multiplies the Δ value and the gain B to obtain a result of the calculation as (1). 2 selector 712 is provided. The ER engine controller 730 controls the second selector 712 so that the second selector 712 feeds back the operation result (1) to the first selector 704 through the second register unit 722. .

In the third step of the calculation procedure, the ER engine controller 730 provides the adder 710 with q latched by the first register 718 and q _prev latched by the second register 720. Result (1) and corrected above The first selector 704 is controlled to provide a to the divider 708. The first selector 704 provides the q and q _prev to the adder 710, and the calculation result (1) and the corrected To the divider 708. Accordingly, the adder 710 subtracts q _prev from q and provides it to the second selector 712 as the calculation result (2). The divider 708 corrects the operation result (1). It is divided into and provided to the second selector 712 as the calculation result (5). The ER engine controller 730 controls the second selector 712 to feed back the calculation result 2 to the first selector 704 through the second register unit 722.

Here, the operation time of the divider 708 is longer than the operation time of the adder 710, so that when the qq _prev operation of the adder 710 is completed, the divider 708 continues to calculate and the operation procedure is left as it is. Proceed to step 4.

In the fourth step of the calculation procedure, the ER engine controller 730 provides the adder 710 with q, which the first register 718 latches, and q _T provided by the water system converter 700. The selector 704 is controlled. According to the control, the first selector 704 subtracts q _T from q and provides the result to the second selector 712 as an operation result (3). The ER engine controller 730 controls the second selector 712 to feed back the calculation result (3) to the first selector 704 through the second register unit 722.

In the fifth step of the calculation procedure, the ER engine controller 730 supplies the multiplier 706 with the calculation result 2 latched by the second register part 722 and the gain A provided by the gain selector 702. The first selector 704 is controlled to provide. The first selector 704 multiplies the calculation result (2) by the gain A and provides it to the second selector 712 as the calculation result (4). The ER engine controller 730 controls the second selector 712 to feed back the calculation result 4 to the first selector 704 via the second register unit 722.

Here, the divider 708 is corrected in (1) during the second to fifth steps of the calculation procedure. Is divided and output as the calculation result (5), which is provided to the second selector (712). The ER engine controller 730 controls the second selector 712 to feed back the calculation result 5 to the first selector 704 via the second register unit 722.

In the sixth step of the calculation procedure, the ER engine controller 730 provides the multiplier 706 with the calculation result (3) and the calculation result (5) from the second register unit 722 and the second register. Compensated with the calculation result (4) from the section 722 The first selector 704 is controlled to provide a to the divider 708. The first selector 704 provides the arithmetic result (3) and the arithmetic result (5) to the multiplier 706 and corrects the arithmetic result (4) according to the control. To the divider 708. The multiplier 706 multiplies the calculation result (3) by the calculation result (5) and provides it to the second selector 712 as the calculation result (6), and the divider 708 provides the calculation result (4). Calibrated above It is divided into and provided to the second selector 712 as the calculation result (7).

The ER engine controller 730 controls the second selector 712 to feed back the calculation result 6 and the calculation result 7 to the first selector 704 through the second register unit 722.

In the seventh step of the calculation procedure, the ER engine controller 730 provides the first selector 704 to provide the adder 710 with the calculation result 6 and the calculation result 7 from the second register unit 722. To control. The first selector 704 provides the calculation result 6 and the calculation result 7 to the adder 710 according to the control. The adder 710 adds the calculation result 6 and the calculation result 7 and provides it to the second selector 712 as the calculation result 8. The ER engine controller 730 controls the second selector 712 to feed back the calculation result 8 to the first selector 704 via the second register unit 722.

In the eighth step of the calculation procedure, the ER engine controller 730 adds the calculation result 8 from the second register unit 722 and the previous ER ER _prev latched by the fourth register 728. To control the first selector 704. The first selector 704 provides the operation result 8 and ER _prev to the adder 710 according to the control. The adder 710 subtracts the calculation result 8 from the ER _prev and provides it to the second selector 712 as ER. The ER engine controller 730 controls the second selector 712 to feed back the ER to the first selector 704 through the third register 726.

In the ninth step of the calculation procedure, the ER engine controller 730 provides the first selector 704 to provide the multiplier 706 with the ER from the third register 726 and the K provided by the water system converter 700. ). The first selector 704 provides the ER and K to a multiplier 706 according to the control. The multiplier 706 converts the ER, which was the 32-bit floating point format, into a 16-bit integer form by adding the ER and K, and outputs it to the outside through the second register unit 722 as KER. Herein, the KER becomes the final ER output from the ER engine 208.

As described above, the ER operation is not performed in real time but is performed every second period, so that the multiplier 706, the divider 708, and the adder according to the operation procedure composed of the first to ninth steps to reduce the hardware requirement. 710) many times.

In addition, the multiplier 706, the divider 708, and the adder 710 use an arithmetic operator that performs floating point arithmetic to increase the accuracy of the calculation.

The configuration and operation of the reverse cell processor 212 will now be described with reference to FIG. 5, which shows a block diagram of the reverse cell processor 212 that is responsible for processing the RM cells in the reverse cell. The UTOPIA interface 1000 of the reverse cell processor 212 provides a UTOPIA interface. The reverse cell decoder 1002 receives an SOC and a reverse cell from the UTOPIA interface 1000 and searches whether the reverse cell is an RM cell and generated at the source, and if the cell is an RM cell and generated at the source, the RM cell. The ER and MCR recorded in the cell are read and provided to the ER recording judgment unit 1008. In addition, when the ER write determiner 1008 provides the ER, the reverse cell decoder 1002 records the received ER in the received RM cell. In addition, the reverse cell decoder 1002 marks NI or CI on the received RM cell according to the NI and CI provided by the congestion detector 1006. In addition, the reverse cell decoder 1002 receives a CRC for the RM cells marked with the ER, NI, and CI from the CRC detection and generation unit 1004, and records the CRC in the RM cell and outputs the CRC. The CRC detection and generation unit 1004 not only detects a CRC error for the input reverse RM cell but also generates a CRC for the RM cell marking ER, NI, and CI and provides the reverse cell decoder 1002. . The congestion detection unit 1006 receives the high threshold q _HT of the queue and q _LT of the low threshold of the queue from the microprocessor 108 and enters the congestion state when the queue size is larger than q _LT and smaller than q _HT . Judge and provide information of NI = 1, CI = 0 to reverse cell decoder 1002, and if the queue size is larger than q _HT , it is determined to be very congested and reverse information of NI = 1, CI = 1 When the queue size is smaller than q _LT , the cell decoder 1002 is determined not to be congested, and the information is provided to the reverse cell decoder 1002 with NI = 0 and CI = 0. The ER recording determining unit 1008 adds the MCR from the received RM cell provided by the reverse cell decoder 1002 and the ER provided by the ER engine 208 to be smaller than the ER from the received RM cell. Search and provide the reverse cell decoder 1002 with the ER provided by the ER engine 208 when the addition is less than the ER from the received RM cell.

Referring to FIG. 19 illustrating a configuration diagram of the reverse cell decoder 1002, the cell element counting unit 1100 counts the reverse clock and outputs the cell count from the time when the SOC is generated, and the cell count is RM. It is reset in accordance with the reset signal generated every time corresponding to the entire cell. The cell count is input to the comparator 1102. The comparison unit 1102 generates a PTI clock when the input cell count corresponds to a PTI position in an RM cell, generates a DIR-BN clock when corresponding to a message type position, and generates an ER when corresponding to an ER position. Generate a clock and generate an MCR clock when it corresponds to the MCR position. In addition, an AND clock is generated when the cell count corresponds to the length of all cells. The PTI clock, the DIR-BN clock, the ER clock, the MCR clock, and the clock output by the comparator 1102 are output in synchronization with the reverse clock through the first register unit 1104. The end clock synchronously outputted through the first register unit 1104 is inverted through the inverter INV and provided as a reset signal. The PTI clock synchronously outputted through the first register unit 1104 is input to the clock of the PTI register 1106, and the DIR-BN clock is input to the clock of the DIR-BN register 1108. The clock is input to the clock of the ER register 1110 and the MCR clock is input to the clock of the MCR register 1112.

The cell buffer multiplexer 1114 reads a 16-bit cell latched to the second register 1120 when the header added is 4 bytes, and 8 bits of a cell latched to the second register 1120 when the header is 5 bytes. And 8 bits of the cell latched in the first register 1118 are aligned to provide the input reverse cell to the second register unit 1116. The second register unit 1116 provides the input RM cell to the PTI register 1106, the DIR_BN register 1108, the ER register 1110, and the MCR register 1112 in synchronization with a reverse clock. The PTI register 1106, the DIR_BN register 1108, the ER register 1110, and the MCR register 1112 each receive an RM cell from the second register unit 1116 and include a PTI clock, a DIR_BN clock, an ER clock, and an MCR. Latch the data entered when the clock is generated. Accordingly, the PTI register 1106, the DIR_BN register 1108, the ER register 1110, and the MCR register 1112 each latch a PTI, a data type, an ER, and an MCR from an RM cell. The PTI and data type are provided to the RM cell detector 1132 to determine whether the received reverse cell is a reverse RM cell generated from a source. The ER and MCR are provided to an ER recording determination unit 1008 that determines whether to record the ER calculated by the ER engine 204 in the received RM cell.

The RM cell detector 1132 searches for DIR and BN included in the PTI and data type to find out whether the corresponding cell is a reverse RM cell and is generated from a source. At this time, if the corresponding cell is a reverse RM cell and is generated from a source, an RM start signal is generated.

The first to fifth registers 418 to 426 buffer and output the input forward cells, and buffer and output the SOC and amplifier signals as SOC and enable signals.

An NI and CI marking unit 1124 is positioned between the third register 1122 and the fourth register 1126, and the NI and CI marking unit 1124 includes NI and CI provided by the congestion detection unit 1006. Is marked in the NI and CI regions of the RM cell buffered between the third register 112 and the fourth register 1126. An ER recording unit 1128 is positioned between the fourth register 1126 and the fifth register 1130, and the ER recording unit 1128 provides the ER when the ER recording determination unit 1008 provides the ER. Writes in the ER area of the RM cell buffered between the register 1126 and the fifth register 1130. As described above, marking NI and CI on the RM cell and writing a new ER are already widely used techniques, and thus detailed description thereof will be omitted.

As described above, the reason for recording the ER in the RM cell buffered between the fourth register 1126 and the fifth register 1130 is as shown in FIG. 4 even though the position of the ER in the RM cell is earlier than the position of the MCR. Since the ER should be recorded after the MCR is read, the RM cell is buffered while the ER is recorded. As described above, in the preferred embodiment of the present invention, the received reverse RM cell is buffered using a few registers, thereby preventing unnecessary memory usage.

The N _T because it is subject to change without notice by the microprocessor 108, a change in the N _T is the N _T correction adding the ABR service engine 104 to correct the N _T since exert a great influence on each operation It may be added, by referring to the N _T correction diagram shown in Figure 20 a explains the N _T calibration process. The first register 1200 is provided with N _T and latched to provide it to the second register 1202 and the subtractor 1204. The second register 1202 is provided to the subtracter 1204 to latch the N _T N _T as previously provided by the first register (1200). The subtracter 1204 subtracts the N _T provided by the second resistor (1200,1202) from the N _T for providing the first register 1200, and calculates the change amount of the N _T N _diff. The N _diff is provided to the ER engine 208 to correct for N _T , which may have changed in the ER operation. And N _diff is input to the comparator 1206, where the comparator 1206 searches if the N _diff is zero. Comparator 1206 when the N _diff is not zero will be output to the correction by adding the N _T N N _{T diff} previously to enable the adder 1208. The corrected N _T output by the adder 1208 is provided to the adder 1208 as the previous N _T through the third register 1210. N _T corrected as above To be used for estimation The estimation unit 202 is provided.

As described above, the ABR service apparatus of the present invention guarantees maximum link utilization and minimum cell loss regardless of delay of round trip time of the ABR closed loop, and minimizes the requirement of ABR queue size by ensuring asymptotic stability of the ABR queue. By ensuring fairness of transmission bandwidth utilization among ABR users, it guarantees maximum and minimum fairness, which is the ATM forum standard, and can adapt quickly to changes in the network environment such as changes in the number of ABR users and changes in ABR bandwidth, and EFCI, RR, It provides almost all of the features of the ATM Forum traffic management standard, including features such as ER marking, and allows for the presence of asymptotic stabilization operating points to enable high availability, low cell loss, and maximum-minimum fairness allocation. Regarding the change in cell level rate at multiple time scales, that is, the cell level rate of VBR and ABR VC, and the network load change at cell level arrival and departure of VBR and ABR VC Improves responsiveness and control transient performance, minimizes the number of operations required to compute algorithms, and reduces the complexity of implementation and scalability to eliminate per-VC operations, including per-VC queuing, per-VC calculations, and per-VC table accesses. The ABR service algorithm is implemented in hardware.

In the ABR service device of the present invention Estimation and ER calculations are not performed in real time, but at predetermined intervals. Like this periodically As the estimation or ER operation is performed, the control becomes easier. Also as above As the estimation or ER operation is performed periodically, the ABR service apparatus of the present invention minimizes the hardware requirements by reusing various operators. In addition, the present invention improves the accuracy of various calculation results by performing a floating point operation internally using a floating point calculator.

In addition, the ABR service apparatus of the present invention adopts a method of buffering the received reverse RM cell using a predetermined number of registers and determining whether to record an ER in the RM cell, thereby storing the received reverse RM cell. Eliminate the need This minimizes the use of memory.

As described above, the present invention has advantages in that the ABR service algorithm is implemented in hardware, which is easy to control, increases the accuracy of various calculation results, minimizes hardware requirements, and minimizes memory usage.

Claims (22)

An available bit rate service apparatus of a packet switched system, A forward cell processor for generating a first start signal whenever a forward resource management cell is input, and extracting a current cell rate and a minimum cell rate from the forward resource management cell; Each time the first start signal is input, it is searched whether the subtracted minimum cell rate from the current cell rate is smaller than a specified cell rate. In this case, it is determined that the input resource management cell has contributed to the number of elements. The amount of contribution of the management cell to the number of elements is calculated by dividing the forward resource management cell transmission period by a value obtained by multiplying the first period and the current cell rate, and then accumulating the previous value, whenever the second start signal is provided. Calculating the number of elements by adding up the accumulated contribution and subtracting the low-band filtering parameter from 1, adding the total number of elements to the previous number of elements and multiplying the low-band filtering parameter. An element count estimator, Whenever a third start signal is provided, the previous average queue size is subtracted from the average queue size by multiplying by the first gain and dividing the result by the number of elements calculated by the element number estimator, An explicit cell rate calculating unit that calculates the specified cell rate by subtracting the target queue size from the previous gain cell rate by multiplying the period of the second gain value and the third start signal and dividing it by the number of elements again; , Each time a reverse resource management cell is input, the explicit cell rate calculator calculates whether the explicit cell rate is smaller than the sum of the specified cell rate and the minimum cell rate extracted from the reverse resource management cell. A reverse cell processing unit for recording and transmitting a specified cell rate to the reverse resource management cell; And a timer for generating the second start signal for each of the first periods and providing the number of elements to the element number estimator, and for generating the third start signal for every second period and providing the third start signal to the specified cell rate calculator. Available bit rate service apparatus of a packet switching system. The method of claim 1, wherein the forward cell processing unit, And the first start signal is generated only when there is no error in the input forward resource management cell. 2. The apparatus of claim 1, wherein a header of a first size or a second size is added to the resource management cell. The method of claim 3, wherein the forward cell processing unit, And a cell buffer multiplexer for aligning the forward resource management cells to which the first size or second size header is added and outputting the start of the forward resource management cells at the same time. Service device. The method of claim 1, A packet switching system comprising a queue counter by generating a queue change signal and a queue read signal generated during queue read from an input / output buffer management unit that manages input / output queuing and generating a queue change count and a queue size. Available Bit Rate Service Device. The method of claim 5, wherein the forward cell processing unit, And receiving the queue size from the queue counter and marking and outputting an explicit congestion identification region of a forward data cell if the queue size is larger than a predetermined congestion threshold for explicit congestion identification. Available Bit Rate Service Device. The method of claim 6, wherein the forward cell processing unit, And a plurality of registers for extracting a current cell rate and a minimum cell rate from the provided forward resource management cell and buffering the forward resource management cell while marking the explicit congestion identification area. Available bit rate service device. The method of claim 1, wherein the forward cell processing unit, A cell element counting unit for counting the forward clock and outputting a cell count; The first clock is generated when the cell count corresponds to the position of the forward resource management cell in which the information indicating whether the cell count is generated from the source and the direction information is located, and the cell count is the forward resource management cell in which the current cell rate is located. A second clock is generated when the cell count corresponds to the position of, and a third clock is generated when the cell count corresponds to the position of the forward resource management cell in which the minimum cell rate is located. The cell count is located at the last position of the forward resource management cell. A comparator for generating a signal for resetting the cell element count unit if it corresponds; A first register for latching a portion of the forward cell passing when the first clock is provided; A second register for latching a part of the forward cells passing when the second clock is provided and outputting the current cell rate; A third register for latching a part of the forward cells passing when the third clock is provided and outputting the minimum cell rate; And a detection unit configured to refer to a part of the forward cell latched by the first register to detect whether the forward cell is a resource management cell and to be generated from a source, and if so, to generate a first start signal. Available Bit Rate Service Device. The method of claim 3, wherein the reverse cell processing unit, And a cell buffer multiplexer for aligning reverse resource management cells to which the first size or second size header is added and outputting a start portion of the reverse resource management cell at the same time point. Service device. The method of claim 5, wherein the reverse cell processing unit, Receiving the queue size from the queue counter and searching whether the queue size is greater than a predetermined congestion threshold or greater than a congestion threshold; and if the queue size is greater than the congestion threshold and less than the congestion threshold, the reverse resource management And marking and outputting a no-increment region of the cell, and marking and outputting a no-increment region and a congestion identification region of the reverse resource management cell if it is greater than the congestion threshold and the very congestion threshold. An available bit rate service apparatus of a packet switched system. The method of claim 10, wherein the reverse cell processing unit, Extracting an explicit cell rate from the provided backward resource management cell, marking a no-critical region and a congestion identification region, and having a plurality of registers buffering the reverse resource management cell while recording the calculated explicit cell rate; And an available bit rate service apparatus of a packet switched system. The method of claim 1, wherein the reverse cell processing unit, A cell element counting unit for counting reverse clocks and outputting cell counts; The first clock is generated when the cell count corresponds to the position of the uplink resource management cell in which the specified cell rate is located, and the second clock is generated when the cell count corresponds to the position of the uplink resource management cell in which the minimum cell rate is located. A comparison unit generating a signal for resetting the cell element count unit when the cell count corresponds to a last position of a reverse resource management cell; A first register for latching a part of the reverse cell passing when the first clock is provided and outputting the cell at a specified cell rate; A second register for latching a part of the reverse cell passing when the second clock is provided and outputting the minimum cell rate; If the explicit cell rate received by the backward resource management cell and calculated by the explicit cell rate calculator is less than the specified cell rate latched by the first register and the minimum cell rate latched by the second register, the reverse cell rate is reversed; And a specified cell rate recording unit for recording in a specified cell rate region of a resource management cell. The method of claim 12, wherein the reverse cell processing unit, The packet exchange system further comprises an error detection and generation unit for receiving the reverse cell to search for an error and generating and adding an error correction code to the reverse resource management cell in which the specified cell rate is recorded. Available Bit Rate Service Device. The method of claim 1, And a microprocessor for providing various parameters for use in estimating the number of elements and calculating the specified cell rate. The method of claim 1, wherein the element number estimation unit, Each time the first start signal is input, the specified cell rate is converted into a floating point format, the minimum cell rate and the floating point number are added, and the addition is compared with the current cell rate, so that the current cell rate is higher than the added value. A determination unit for determining that the input resource management cell contributes to the number of elements if the size is small Converts the current cell rate into a floating point format, divides the converted cell into the first period by dividing the forward resource management cell transmission period by the first period, adds the division result and the previous element number to the floating point number, A contribution degree calculation unit for outputting the sum as a contribution degree when the determination unit determines that the input resource management cell has contributed to the number of elements; Whenever the second start signal is provided, the contribution degree calculated by the contribution degree calculation unit is output, and the contribution degree is subtracted from the low band filtering parameter by 1, and the floating point multiplier is increased. And an element number calculation unit for calculating an element number by adding a floating point number and a floating point multiplier of the low band filtering parameter. The method according to claim 15, wherein the element number calculation unit, An operation unit which subtracts and outputs the low band filtering parameter from 1; A register for latching the contribution degree provided by the contribution degree calculation unit, the output of the calculation unit, the low band filtering parameter, the total circle introduction number, the previous circle introduction number, and various calculation results; A first selector for selecting and outputting some of the values latched by the first register unit; A multiplier multiplying a floating point by receiving some of the values selected and output by the first selector; An adder which receives a floating point number and receives some of values selected and output by the first selector; A limiter for limiting and outputting the number of elements calculated as the value between the total circle number and zero, A second selector which receives the output of the multiplier and the addition and selectively provides the multiplier and the output to the limiter or the register unit; Each time the second start signal is provided, the previous number of elements and the total number of elements among the values latched by the first register unit are provided to the adder, and the output of the operation unit and the degree of contribution are provided to the multiplier. Controlling the first selector to control the second selector to feed back the outputs of the adder and the multiplier to the register as a first operation result and a second operation result, and then filtering the first operation result and the low band filtering. Controlling the first selector to provide a parameter to the multiplier and controlling the second selector to feed the multiplier's output back to the register as a third operation result, the second operation result and the third operation The first selector is controlled to provide a result to the adder, and the second selector is controlled to output the output of the adder to the limiter. Available bit rate service device of a packet switching system comprising the controller. The method of claim 15, And a correction unit for correcting the amount of change in the total source introduction water. The method of claim 5, wherein the specified cell rate calculation unit, And calculating the average queue size by dividing the queue size by the number of queue changes, and latching the average queue size as a previous average queue size. The method of claim 5, wherein the specified cell rate calculation unit, A numerical system converter for converting the target queue size, the second period, the number of elements, the number of queue changes, and the queue size into a floating point format; A first selector for selecting and outputting various parameters from the numerical system converter and a part of the first and second gains; A multiplier configured to receive a part of the output of the first selector and multiply floating point; A divider which receives a part of the output of the first selector and divides the floating point; An adder which receives a part of the output of the first selector and adds a floating point number; A second selector which receives the calculation result of the multiplier, the divider and the adder and selects and outputs an output path thereof; A first latch unit which receives and latches an average queue size among the calculation results output by the second selector and latches as the previous average queue size; A second latch unit which receives and latches a specified cell rate among the operation results output by the second selector and latches the previous cell rate; A third latch unit configured to receive and latch an operation result output from the second selector; Each time the third start signal is provided, the second selector controls the first selector to provide the queue size and the number of queue changes to the divider, and provides the average queue size, which is the result of division, to the first latch unit. After controlling, after controlling the first selector to provide the second gain and the second period to the multiplier, and after controlling the second selector to provide the first operation result which is the multiplication result to the third latch unit, The first selector to provide the adder with the average queue size latched by the first latch portion and the previous average queue size to subtract the previous average queue size from the average queue size and provide the first operation result and the number of elements to the divider After controlling the second selector to provide the second calculation result, which is the result of the subtraction, to the third latch unit, the average queue size and the target queue size are provided to the adder, thereby providing a target at the average queue size. After controlling the second selector to subtract the size and to provide the third operation result, which is the result of the subtraction, to the third latch unit, the first selector is controlled to provide the second operation result and the first gain to the multiplier. The second selector is controlled to provide a third latching unit with a fourth operation result which is the multiplication result and a fifth operation result that is the division result of the divider, and then the third operation result and the fifth operation result are stored. Providing a multiplier and controlling the first selector to provide the fourth operation result and the number of elements to the divider, and providing the third operation result of the sixth operation result and the seventh operation result of the division result to the third latch unit. After controlling the second selector to control the first selector to provide the sixth and seventh operation results to the adder, and to provide the addition result to the second latch unit as an explicit cell rate. To control After control, the first latch is controlled to subtract the specified cell rate from the previous specified cell rate by providing an adder with the previous specified cell rate and the specified cell rate latched by the second latch unit, and the specified cell as the subtraction result. And a control unit for controlling the second selector to output a rate. The method of claim 19, wherein the specified cell rate calculation unit, And a predetermined parameter multiplied by a predetermined cell rate for outputting the available bit rate service apparatus. The method of claim 19, wherein the specified cell rate calculation unit, The available bit rate service apparatus of the packet switched system according to claim 1, wherein the total source introduction number used during the calculation is corrected by adding a change amount of the total source introduction number to the total source introduction number. The method of claim 19, wherein the specified cell rate calculation unit, Receiving a third and fourth gain that can be used as the first gain and a fifth and sixth gain that can be used as the second gain, such that the average queue size is less than or equal to a predetermined threshold If not, the third gain is used as the first gain and the fifth gain is used as the second gain, and if the average queue size is greater than a predetermined threshold or greater than the threshold before, the first gain is used. And a gain selector for selecting to use the fourth gain as the first gain and the sixth gain as the second gain.