KR100380148B1 - Method of forming a isolation layer in a semiconductor device - Google Patents

Abstract

The present invention relates to a method of forming a device isolation layer of a semiconductor device, and in the process of patterning a pad nitride layer and a pad oxide layer by etching during a process of forming a device isolation layer by filling an insulating material into the trench after forming the trench. By minimizing the transient etching process and shallowly etching the semiconductor substrate at a gentle angle using a mixed gas having a high etching selectivity with the semiconductor substrate, the semiconductor substrate is etched to the same depth regardless of the pattern spacing to maintain the trench etching depth the same. Then, an element isolation film forming method of a semiconductor device capable of simultaneously obtaining an active area corner rounding effect of a semiconductor substrate is disclosed.

Description

Method of forming a isolation layer in a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a device isolation layer of a semiconductor device, and more particularly, to a method of forming a device isolation layer of a semiconductor device in which an isolation material is formed by filling an insulating material into a trench after forming a trench.

As the semiconductor manufacturing process reduces the circuit line width of the device, the forming process is also very difficult and complicated. Among these, the device isolation process is the first process in the semiconductor device formation process and is a technology for electrically insulating two devices by forming an insulating film between the transistor and the transistor. Currently, a shallow trench isolation (STI) process is used as a device isolation technology. The trench etching process for forming an STI includes two processes of etching a pad nitride layer and a pad oxide layer, and etching a semiconductor substrate. Here, the process of etching the pad nitride film and the pad oxide film mainly uses a CF-based gas for etching the insulating film. In this case, the etching rate is changed according to the shape of the pattern.

Referring to FIG. 1, after forming the pad oxide film 2 and the pad nitride film 3 on the semiconductor substrate 1, the pad nitride film 3 and the pad oxide film 2 are patterned by an etching process. At this time, the etching speed of the region A in which the spacing between the patterns is narrow is lower than that in the region B where the spacing between the patterns is wide. Therefore, even after the pad nitride film 3 of the wide area B is removed, the pad nitride film 3a still remains in the narrow area A, thereby acting as an etch stop layer during subsequent silicon etching.

Referring to FIG. 2, in order to solve the problem in FIG. 1, overetch is sufficiently performed to remove all of the pad nitride film 13 in the narrow area A. When all of 13) is removed, etching damage appears in the semiconductor substrate 11 that is the lower layer in the wide area B.

In this case, since the semiconductor substrate 11 is already etched in the wide area B, the difference (C) of the trench etching depth may occur even when there is no pattern dependence of the etching rate when the semiconductor substrate 11 is etched. The difference (C) of the trench etch depth causes a difference in insulation ability between devices, which ultimately degrades device characteristics. In addition, since the active region corner D of the semiconductor substrate 11 is vertically formed due to the excessive etching of the pad nitride layer 13 in the wide region B, the etching gas is used to smooth the etching. This is useless. Therefore, it is difficult to reduce the Hump phenomenon in which the double current saturation curve appears due to the shape of the vertical semiconductor substrate and the reverse narrow width effect (RNWE) in which the transistor operating voltage decreases depending on the size of the active region. It becomes difficult to show characteristics.

Therefore, in order to solve the above problems, the present invention minimizes the excessive etching process of the pad nitride layer during the trench etching process for forming the STI, and smoothes the semiconductor substrate using a mixed gas having a high etching selectivity with the semiconductor substrate. By shallowly etching at an angle, the semiconductor substrate is etched to the same depth irrespective of the pattern spacing to maintain the trench etch depth the same, and to simultaneously obtain the active area corner round effect of the semiconductor substrate. The purpose is to provide.

1 and 2 are cross-sectional views of a device shown to explain a method of forming a device isolation film of a conventional semiconductor device.

3A to 3D are cross-sectional views of devices sequentially shown to explain a method of forming a device isolation film of a semiconductor device according to the present invention.

<Description of the symbols for the main parts of the drawings>

1, 11: semiconductor substrate 2, 12: pad oxide film

21a: trench 3, 13: pad nitride film

3a: residual pad nitride film 24: device isolation film

A: narrow pattern area B: wide pattern area

C: difference in trench etch depth D: corner of active area

In the method of forming a device isolation layer of a semiconductor device according to the present invention, a method of sequentially forming a pad oxide layer and a pad nitride layer on a semiconductor substrate may be performed by etching predetermined regions of the pad nitride layer and the pad oxide layer, but having a wide pattern gap. Performing a primary etching process until the semiconductor substrate is completely removed; etching the semiconductor substrate to completely remove the pad nitride film and the pad oxide film remaining in the narrow region of the pattern while the etching depth of the wide region and the narrow region is the same. Performing a secondary etching process so that the corners of the active regions are rounded, and performing a tertiary etching process of etching the semiconductor substrate to a target depth by forming the trenches at the same depth as those of the wide region and the narrow region. Filling the inside of the trench with an insulating material, Removing and planarizing the pad nitride film, the pad oxide film, and the insulating material.

The primary etching process uses CF ₄ gas as an etching gas. The secondary etching process uses a mixed gas of CHF ₃ gas and CH ₄ gas as an etching gas, and forms a polymer in the active corner region using CHF ₃ gas to etch the active corner region in a round shape. . At this time, the mixing of the CHF ₃ gas and the CH ₄ gas is a ratio of 6: 4 to 8: 2 :, ideally mixed in a ratio of 7: 3. In addition, the etching of the active corner region is performed to a depth of 300 to 400 kPa.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail.

3A to 3D are cross-sectional views of devices sequentially illustrated to explain a method of forming a device isolation film of a semiconductor device according to the present invention.

Referring to FIG. 3A, a pad oxide film 22 and a pad nitride film 23 are sequentially formed on a semiconductor substrate 21, and a device isolation region is defined by a photoresist pattern (not shown), followed by primary using CH ₄ gas. An exposed region of the pad nitride layer 23 and the pad oxide layer 22 is etched and patterned by an etching process.

The pad oxide film 22 is formed to a thickness of 100 to 150 kPa, and the pad nitride film 23 is deposited to a thickness of 1000 to 1500 kPa. As the etching gas used to etch the pad nitride film 23 and the pad oxide film 22, CF-based and CHF-based gases are generally used. In the present invention, the etching end point is determined by EPD (End Point Detection), which is an etch stop time, using CF ₄ gas, which is a relatively small polymer generation gas, or Ar gas, which is an inert gas. In this case, the pad nitride film 23 remains to some extent not only in the region A having a narrow pattern spacing but also in the region B having a large spacing. Therefore, in order to remove this, the over etching is performed, and the over etching is stopped at the time when the pad nitride film 23 and the pad oxide film 22 are completely removed in the region B of a wide interval. In this case, both the pad nitride film 23 and the pad oxide film 22 are removed in the pattern of the wide area B, but remain in the pattern of the narrow area A. FIG.

Referring to FIG. 3B, the etch depth of the narrow region A and the wide region B may be etched by using the mixed gas in which the CHF ₃ gas and the CF ₄ gas are mixed as an etching gas by etching the semiconductor substrate 21. At the same time, the secondary etching process is performed such that the active area corner D of the semiconductor substrate 21 is formed in a gentle inclination or round shape.

The secondary etching process is performed using a CHF ₃ gas having a high etching selectivity between the pad nitride film 23 and the semiconductor substrate 21. The first etching process is performed because the etching selectivity between the pad nitride film 23 and the semiconductor substrate 21 is high. When CHF ₃ gas is used, a large amount of polymer is generated especially in the pattern of the wide area (B), so that the difference in the pattern size of the narrow area (A) and the pattern size of the wide area (B) is severely generated. Becomes difficult. Therefore, when the etching process is performed using a certain ratio of CHF ₃ / CF ₄ mixed gas, the semiconductor layer is patterned in the wide area B while the pad nitride film 23 and the pad oxide film 22 are etched in the narrow area A. The substrate 21 is etched. At this time, the mixing ratio of the CHF ₃ gas and the CF ₄ gas is about 6: 4 to 8: 2, ideally mixing in a ratio of 7: 3.

In more detail, as described with reference to FIG. 3A, since a large amount of polymer is formed in the pattern of the wide area B as compared to the pattern of the narrow area A, the depth at which the semiconductor substrate 21 is etched may be CF ₄ gas. This is considerably lower than when used. When the pad nitride layer 23 and the pad oxide layer 22 are etched in the pattern of the narrow region B, the semiconductor substrate 21, which is the lower layer, is etched. In this case, the etching process using the CHF ₃ gas is performed. By the polymer generated at the edges of the exposed semiconductor substrate 21, etching proceeds while the semiconductor substrate 21 is not etched vertically while maintaining a gentle angle. In the case of the narrow region A pattern, since the polymer is less generated and the etching effect by the vertically incident ions is large, the etching speed of the semiconductor substrate 21 is faster than that of the pattern of the large region B. By using this effect, the semiconductor substrate 21 is etched to about 300 to 400Å.

By the above process, the etching of the semiconductor substrate 21 is performed in the wide area B first, but since the etching in the narrow area A proceeds faster, when the etching is performed to a certain depth, the narrow area A and the wide area are etched. The etching depth of (B) becomes the same. In addition, a polymer is generated in the active region corner D, which is an edge of the exposed semiconductor substrate 21, to prevent etching, thereby automatically forming a round shape.

Referring to FIG. 3C, when the etching depths of the narrow region A and the wide region B become equal, the etching speeds of the narrow region A and the wide region B may be kept constant by a commonly known etching process. The difference etching process is performed to form trenches 21a having a target depth.

When the process up to FIG. 3B is completed, since the etching depth of the semiconductor substrate 21 is similar regardless of the pattern spacing, the pattern dependency of the etching rate occurring in the etching process of removing the pad nitride layer 23 is removed. Therefore, if the semiconductor substrate etching speed is kept constant, the change in the trench depth according to the pattern spacing can be considerably alleviated.

Referring to FIG. 3D, after removing impurities and embedding the buried material in the trench 21a, the pad nitride film 22, the pad oxide film 21, and the buried material on the semiconductor substrate 21 are removed, and then planarized. 24).

In the above process, the CHF ₃ / CF ₄ ratio is kept constant along with the reduction in the pattern dependency of the nitride film etch to form the etch angle smoothly rather than vertically during etching of the semiconductor substrate, thereby forming an active region corner round. As a result, the silicon corner is smoothed while the insulation characteristics are prevented from being degraded due to the trench etch depth unevenness, thereby significantly reducing the hum and RNWE phenomena, thereby ensuring stable device characteristics.

As described above, the present invention can significantly reduce the pattern dependence of the etching rate and can gently etch the silicon corners, thereby preventing the deterioration of electrical characteristics including the insulating properties due to the change of the trench etching depth, and also the semiconductor substrate. The active area rounding effect can eliminate the Hump phenomenon, which results in a double saturation current curve, and significantly reduce the RNWE, a phenomenon in which the transistor operating voltage decreases as the active pattern size changes. Has the effect of improving.

Claims (5)

Sequentially forming a pad oxide film and a pad nitride film on the semiconductor substrate; Etching a predetermined region of the pad nitride layer and the pad oxide layer, but performing a first etching process until the pad nitride layer and the pad oxide layer having a large pattern interval are completely removed; While removing the pad nitride film and the pad oxide film remaining in the narrow region of the pattern, the semiconductor substrate is etched so that the etching depth of the wide region and the narrow region is the same. Carrying out the process; Performing a tertiary etching process of forming a trench by etching the semiconductor substrate to a target depth at the same etching rate between the wide region and the narrow region; And filling the inside of the trench with an insulating material, and then removing and planarizing the pad nitride film, the pad oxide film, and the insulating material on the semiconductor substrate. The method of claim 1, The first etching process is a device isolation film forming method of a semiconductor device, characterized in that using the CF ₄ gas as an etching gas. The method of claim 1, The secondary etching process uses a mixed gas of a mixture of CHF ₃ gas and CH ₄ gas as an etching gas, and generates a polymer at the corner of the active region using CHF ₃ gas to etch the active corner region in a round shape. A device isolation film forming method of a semiconductor device. The method of claim 3, wherein The CHF ₃ gas and the CH ₄ gas is mixed in a ratio of 6: 4 to 8: 2, and ideally in a ratio of 7: 3. The method of claim 3, wherein And etching the active corner region to a depth of about 300 to about 400 microns.