KR100378092B1 - Flip chip bonding method - Google Patents
Flip chip bonding method Download PDFInfo
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- KR100378092B1 KR100378092B1 KR10-1999-0020941A KR19990020941A KR100378092B1 KR 100378092 B1 KR100378092 B1 KR 100378092B1 KR 19990020941 A KR19990020941 A KR 19990020941A KR 100378092 B1 KR100378092 B1 KR 100378092B1
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 44
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910000679 solder Inorganic materials 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 3
- 230000004907 flux Effects 0.000 claims description 2
- 239000007788 liquid Substances 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 반도체 칩을 기판(Substrate)상에 회로부가 아래로 향하도록 뒤집어서 실장하는 플립 칩(Flip Chip) 기술로서, 미리 기판 상에 금속범프를 형성하고, 이 금속범프에 반도체칩을 플립 칩 본딩 하도록 된 것으로, 그 구체적인 플립 칩 본딩 방법은, 표면에 회로패턴이 형성되고, 이 회로패턴을 보호하도록 커버코트(cover coat)가 코팅된 기판에 반도체칩 상의 칩패드가 위치되는 영역에 금속범프를 형성하고, 이 금속범프에 반도체칩 상의 칩패드가 부착되도록 상기 반도체칩을 뒤집어서 실장하는 것이다.The present invention is a flip chip technology in which a semiconductor chip is inverted and mounted on a substrate so that a circuit part faces downward, and a metal bump is formed on a substrate in advance, and the semiconductor chip is flip chip bonded to the metal bump. In this specific flip chip bonding method, a circuit pattern is formed on a surface, and a metal bump is applied to an area where a chip pad on a semiconductor chip is located on a substrate coated with a cover coat to protect the circuit pattern. The semiconductor chip is formed upside down so that a chip pad on the semiconductor chip is attached to the metal bumps.
Description
본 발명은 반도체 칩을 기판(Substrate)상에 회로부가 아래로 향하도록 뒤집어서 실장하는 플립 칩(Flip Chip) 기술로서, 기판에 미리 금속범프를 형성하고, 이 금속범프에 바로 반도체 칩을 실장하도록 함으로서, 제조 공정의 단순화 및 생산성을 향상시킬 수 있도록 된 것이다.The present invention is a flip chip technology in which a semiconductor chip is inverted and mounted on a substrate so that a circuit part faces downward, and the metal chip is formed on the substrate in advance, and the semiconductor chip is directly mounted on the metal bump. This simplifies the manufacturing process and improves productivity.
일반적으로 플립 칩 본딩 방법은, 반도체 칩을 기판 상에 회로부가 아래로 향하도록 뒤집어서 실장하는 기술로서, 상기 기판에 반도체칩을 본딩하기 위하여 먼저 반도체칩의 패드에 범프를 직접 형성하여 반도체 칩을 기판에 실장하는 것이다.In general, a flip chip bonding method is a technique in which a semiconductor chip is mounted upside down with a circuit part facing down on a substrate. In order to bond the semiconductor chip to the substrate, first, bumps are formed directly on a pad of the semiconductor chip to form a substrate. To be mounted on.
이러한 플립 칩 본딩 방법은, 먼저 반도체칩 상의 패드에 범프를 형성하고, 상기 범프가 형성된 반도체칩을 기판 위에 뒤집어서 붙이는 것에 의해 이루어지는 것이 보통이다.Such a flip chip bonding method is usually performed by first forming a bump on a pad on a semiconductor chip, and then attaching the bump with the semiconductor chip on the substrate.
그러나, 이와 같은 통상의 플립 칩 본딩방법은, 반도체칩의 패드에 직접 범프를 형성하여야 하는데, 이와 같이 범프를 형성하기 위한 공정이 매우 난이함으로 많은 불량이 발생될 뿐만 아니라, 제작비용 및 작업 시간이 많이 소요되는 등의 문제점이 있었다. 또한, 상기 반도체칩의 패드에 직접 범프를 형성함으로서, 반도체칩의 패드가 손상되는 경우가 빈번하였다.However, in the conventional flip chip bonding method, bumps must be formed directly on the pads of the semiconductor chip. Thus, the process for forming the bumps is very difficult, and not only many defects are generated, but also manufacturing cost and work time are increased. There was a problem such as a lot of consumption. Also, by forming bumps directly on the pads of the semiconductor chip, the pads of the semiconductor chip are frequently damaged.
본 발명의 목적은 이와 같은 문제점들을 해결하기 위하여 발명된 것으로서, 반도체 칩 상의 패드에 범프를 형성하는 기존의 플립 칩 본딩 방법과는 전혀 다른 방법으로서, 반도체칩이 부착될 기판에 미리 범프를 형성하고, 이 범프에 반도체 칩 상의 패드를 안착시키는 것에 의해 간단하게 플립 칩 본딩을 할 수 있도록 된 것으로, 이와 같은 본딩방법은 반도체칩 상의 패드를 손상시키지 않고, 또 기판에 범프를 형성함으로서 반도체칩 상의 패드에 형성하는 것 보다 훨씬 간편하게 범프를 형성할 수 있음으로서, 작업 공정의 단순화를 도모할 수 있도록 된 플립 칩 본딩 방법을 제공함에 있다.An object of the present invention is to solve such problems, and is a method different from the conventional flip chip bonding method of forming a bump on a pad on a semiconductor chip, and the bump is formed in advance on the substrate to which the semiconductor chip is attached. By flipping the pads on the semiconductor chip on the bumps, flip chip bonding can be performed easily. Such a bonding method does not damage the pads on the semiconductor chip and forms bumps on the substrate to form pads on the semiconductor chip. The present invention provides a flip chip bonding method that enables bumps to be formed much more easily than forming them, thereby simplifying the work process.
도 1은 플립 칩 본딩 방법에 의해 형성된 반도체 패키지의 일 예를 나타낸 도면1 illustrates an example of a semiconductor package formed by a flip chip bonding method.
도 2는 본 발명에 따른 금속범프를 형성하는 방법을 나타낸 도면2 is a view showing a method of forming a metal bump according to the present invention;
도 3은 본 발명의 실시예에 의한 플립 칩 본딩 방법의 순서를 나타낸 도면3 is a flowchart illustrating a flip chip bonding method according to an embodiment of the present invention.
도 4는 본 발명의 다른 실시예에 의한 플립 칩 본딩 방법의 순서를 나타낸 도면4 is a flowchart illustrating a flip chip bonding method according to another embodiment of the present invention.
도 5는 본 발명의 또 다른 실시예에 의한 플립 칩 본딩 방법의 순서를 나타낸 도면5 is a flowchart illustrating a flip chip bonding method according to another embodiment of the present invention.
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 - 기판 11 - 회로패턴10-Board 11-Circuit Pattern
12 - 커버코트(Cover coat) 12' - 상부층12-Cover coat 12 '-Top layer
12" - 하부층 20 - 금속범프12 "-Bottom Layer 20-Metal Bump
30 - 반도체칩 31 - 침패드30-Semiconductor Chip 31-Needle Pad
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 의한 플립 칩 본딩 방법은, 표면에 회로패턴(11)이 형성되고, 이 회로패턴(11)을 보호하도록 커버코트(12)(cover coat)가 코팅된 기판(10)에서, 반도체칩(30) 상의 칩패드(31)와 대응되는 영역의 커버코트(12)를 식각하여 오프닝을 형성하는 단계와, 상기 반도체칩(30) 상의 칩패드(31)와 대응되는 기판(10)의 커버코트(12)의 오프닝을 통해 노출된 회로패턴(11)에 금속범프(20)를 형성하는 단계와, 상기 금속범프(20)에 반도체칩(30) 상의 칩패드(31)가 부착되도록 상기 반도체칩(30)을 뒤집어서 실장하는 단계로 이루어져 있다.In the flip chip bonding method according to the present invention, a circuit pattern 11 is formed on a surface thereof, and a semiconductor chip is provided on a substrate 10 coated with a cover coat 12 to protect the circuit pattern 11. Etching the cover coat 12 in a region corresponding to the chip pad 31 on the substrate 30 to form an opening, and covering the substrate 10 corresponding to the chip pad 31 on the semiconductor chip 30. Forming a metal bump 20 on the circuit pattern 11 exposed through the opening of the coat 12, and attaching the chip pad 31 on the semiconductor chip 30 to the metal bump 20. It consists of a step of mounting the chip 30 upside down.
여기서, 상기 기판(10)에 코팅되는 커버코트(12)는 상부층(12')과 하부층(12")으로 이루어지도록 두 번에 걸쳐 코팅하고, 이 기판(10)에 금속범프(20)를 형성한 다음에, 상기 상부층(12')의 커버코트(12)를 제거하면, 금속범프(20)의 높이를 상대적으로 높일 수 있다.(도 2)In this case, the cover coat 12 coated on the substrate 10 is coated twice so that the upper layer 12 ′ and the lower layer 12 ″ are formed, and the metal bumps 20 are formed on the substrate 10. Then, by removing the cover coat 12 of the upper layer 12 ′, the height of the metal bumps 20 can be relatively increased (FIG. 2).
즉, 상기 기판(10)에 형성되는 커버코트(12)가 처음에는 두 개의 층으로 이루어짐으로서 비교적 높은 두께를 유지하고 있다가, 금속범프(20)를 형성한 다음에 상기 상부층(12')의 커버코트(12)를 제거하면, 상기 커버코트(12)는 그 두께가 얇아짐으로서, 금속범프(20)의 높이가 높아지는 효과를 얻을 수 있는 것이다.That is, the cover coat 12 formed on the substrate 10 maintains a relatively high thickness by initially forming two layers, and then forms the metal bumps 20 and then forms the upper layer 12 '. When the cover coat 12 is removed, the cover coat 12 may be thinner, whereby the height of the metal bumps 20 may be increased.
여기서, 상기 상부층(12')과 하부층(12")으로 이루어지는 커버코트(12)는 서로 그 성분이 차이가 있는 것을 사용하면, 간단하게 하나의 층만을 제거할 수 있다. 예를 들면, 빛의 세기에 의해서 그 반응하는 속도가 서로 다르면 간단히 하나의 층만을 제거할 수 있는 것이다.물론, 상기 금속범프(20)가 형성되는 회로패턴(11)의 상면에 형성된 일정 영역의 커버코트(12)는 식각 공정에 의해 미리 제거되고, 그 이후에 금속범프(20)가 형성된다.Here, the cover coat 12 composed of the upper layer 12 ′ and the lower layer 12 ″ may simply remove only one layer if the components thereof are different from each other. If the reaction rates are different according to the intensity, only one layer can be removed. Of course, the cover coat 12 of a predetermined region formed on the upper surface of the circuit pattern 11 on which the metal bumps 20 are formed is It is removed in advance by the etching process, after which the metal bumps 20 are formed.
또한, 상기에 있어서, 금속범프(20)는 스크린 프린팅 방법에 의해 형성할 수 있다. 즉, 기판(10)의 금속범프(20)가 형성되는 위치와 대응하는 위치에 구멍(61')이 형성된 스크린판(61)을 상기 기판(10)위에 올려놓은 후, 액상의 솔더(63)를 블레이드(62)로 밀어서 상기 스크린판(61)의 구멍(61')을 통해 액상의 솔더(63)가 상기 기판(10)의 금속범프(20)가 형성될 위치에 솔더(63)가 채워지도록 한 다음, 상기 스크린판(61)을 제거한 후, 노에서 상기 솔더(63)를 리플로우하면 금속범프(20)가 형성된다.(도 3)In addition, in the above, the metal bumps 20 can be formed by a screen printing method. That is, after placing the screen plate 61 having the holes 61 'formed on the substrate 10 at a position corresponding to the position where the metal bumps 20 of the substrate 10 are formed, the liquid solder 63 is formed. To the blade 62 so that the solder 63 is filled in the position where the metal solder 20 of the substrate 10 is to be formed through the hole 61 ′ of the screen plate 61. After removing the screen plate 61, the metal bump 20 is formed by reflowing the solder 63 in a furnace (FIG. 3).
또한, 상기 금속범프(20)는 솔더도금에 의한 방법으로 형성할 수 있다. 즉, 상기 기판(10)의 금속범프(20)가 형성되는 위치에 전해도금에 솔더(71)를 위치시킨 다음, 상기 솔더(71)를 노에서 리플로우하면 금속범프(20)가 형성된다.(도 4)In addition, the metal bumps 20 may be formed by solder plating. That is, when the solder 71 is placed in the electroplating at the position where the metal bumps 20 of the substrate 10 are formed, the metal bumps 20 are formed by reflowing the solder 71 in the furnace. (Figure 4)
또한, 상기 금속범프(20)는 구형의 솔더볼(81)을 안착시켜서 형성할 수 있다. 즉, 상기 기판(10)의 금속범프(20)가 형성되는 위치에 플럭스(82)를 도포한 후, 그 위에 구형의 솔더볼(81)을 안착시킨 다음, 노에서 리플로우하면 금속범프(20)가 형성된다.(도 5)In addition, the metal bumps 20 may be formed by mounting a spherical solder ball 81. That is, after the flux 82 is applied to a position where the metal bumps 20 of the substrate 10 are formed, the solder balls 81 of a spherical shape are seated thereon, and the metal bumps 20 are reflowed in a furnace. Is formed (FIG. 5).
이와 같은 방법에 의해 이루어지는 플립 칩 본딩 방법은, 반도체칩(30)이 부착될 기판(10) 상에 미리 금속범프(20)를 형성하고, 이 금속범프(20)에 반도체칩(30) 상의 칩패드(31)를 안착시키는 것에 의해 간단하게 플립 칩 본딩을 할 수 있음으로, 반도체칩(30)상의 칩패드(31)를 손상시킬 염려가 없다.In the flip chip bonding method, the metal bump 20 is formed on the substrate 10 to which the semiconductor chip 30 is to be attached, and the chip on the semiconductor chip 30 is formed on the metal bump 20. Since the flip chip bonding can be performed simply by mounting the pad 31, there is no fear of damaging the chip pad 31 on the semiconductor chip 30.
또, 기판(10)에 금속범프(20)를 형성함으로서 반도체칩(30)의 칩패드(31)에범프를 형성하는 것 보다 훨씬 간편하게 금속범프(20)를 형성할 수 있음으로서, 작업 공정의 단순화를 도모할 수 있다.Also, by forming the metal bumps 20 on the substrate 10, the metal bumps 20 can be formed more easily than the bumps formed on the chip pads 31 of the semiconductor chip 30. Simplification can be achieved.
이와 같은 플립 칩 본딩 방법에 의해 형성된 반도체 패키지는, 통상의 플립 칩 본딩 방법에 의해 형성된 반도체 패키지와 동일한 구성을 갖는 것으로, 도 1에 도시된 바와 같이, 전자회로가 집적되어 있고, 이 전자회로의 신호를 인출하기 위한 칩패드(31)가 일면에 형성되어 있는 반도체칩(30)과, 상기 반도체칩(30)의 칩패드(31)가 부착되는 금속범프(20)가 상면에 구비된 기판(10)과, 상기 반도체칩(30)의 칩패드(31)와 상기 기판(10)의 금속범프(20)의 사이에는 외부의 산화 및 부식으로부터 보호하도록 코팅된 에폭시(40)와, 상기 기판(10)의 저면에 융착되어 반도체칩(30)의 신호를 외부로 인출하는 입출력단자(50)로 이루어진다.A semiconductor package formed by such a flip chip bonding method has the same configuration as a semiconductor package formed by a conventional flip chip bonding method. As shown in FIG. 1, an electronic circuit is integrated, and A substrate having a semiconductor chip 30 having a chip pad 31 for extracting a signal on one surface thereof, and a metal bump 20 to which the chip pad 31 of the semiconductor chip 30 is attached. 10) between the chip pad 31 of the semiconductor chip 30 and the metal bumps 20 of the substrate 10, an epoxy 40 coated to protect against external oxidation and corrosion, and the substrate ( It is made of an input and output terminal 50 is fused to the bottom surface of the 10 to draw the signal of the semiconductor chip 30 to the outside.
여기서, 상기 반도체칩(30)의 칩패드(31)가 형성된 반대면을 외부로 완전히 노출시키면, 즉 반도체칩(30)의 칩패드(31)가 형성되지 않은 면은 에폭시(40)로 봉지하지 않으면, 반도체칩(30)의 회로 동작시 발생되는 열을 효과적으로 방출할 수 있는 장점도 있다.Here, when the opposite surface on which the chip pad 31 of the semiconductor chip 30 is formed is completely exposed to the outside, that is, the surface on which the chip pad 31 of the semiconductor chip 30 is not formed is not sealed with the epoxy 40. Otherwise, the heat generated during the circuit operation of the semiconductor chip 30 can be effectively released.
이상의 설명에서 알 수 있듯이 본 발명의 플립 칩 본딩 방법에 의하면, 플립 칩 본딩을 하기 위한 금속범프를 기판 상에 미리 형성하고, 상기 기판 상에 형성된 금속범프에 플립 칩 본딩을 함으로서, 제조 공정의 단순화 및 생산성을 향상시킬 수 있는 이점이 있다.As can be seen from the above description, according to the flip chip bonding method of the present invention, metal bumps for flip chip bonding are formed on a substrate in advance, and flip chip bonding is performed on the metal bumps formed on the substrate, thereby simplifying the manufacturing process. And there is an advantage to improve the productivity.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0020941A KR100378092B1 (en) | 1999-06-07 | 1999-06-07 | Flip chip bonding method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1999-0020941A KR100378092B1 (en) | 1999-06-07 | 1999-06-07 | Flip chip bonding method |
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| Publication Number | Publication Date |
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| KR20010001600A KR20010001600A (en) | 2001-01-05 |
| KR100378092B1 true KR100378092B1 (en) | 2003-03-29 |
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| KR10-1999-0020941A Expired - Lifetime KR100378092B1 (en) | 1999-06-07 | 1999-06-07 | Flip chip bonding method |
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| KR (1) | KR100378092B1 (en) |
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| KR20010001600A (en) | 2001-01-05 |
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