KR100376871B1 - Power-up signal generator - Google Patents

Abstract

The purpose of the power-up signal generator according to the present invention is to provide a stable initialization by preventing an error that the initialization signal is generated when the external power supply voltage does not reach a sufficient voltage level. The present invention for this purpose comprises an external initialization signal generator and an internal initialization signal generator. The external initialization signal generator includes a first current mirror controlled by a bias voltage connected to the first node, a first active load, a first inverter circuit, and a second inverter circuit connected in series between an external power supply voltage and ground. The first inverter circuit and the second inverter circuit are supplied with power through the first active load, the voltage of the first node and the output of the second inverter circuit are input to the first inverter circuit, and the second terminal which is an output terminal of the first inverter circuit. The node is connected to the input of the second inverter circuit and the output of the first inverter circuit is configured to be output as a power up signal. The internal initialization signal generator includes a second active load, a third active load, and a second current mirror connected in series between an internal power supply voltage and a ground, a second current mirror controlled by a second bias voltage, and a third active load. The third node to which the second current mirror is connected is made to be connected to the second node.

Description

Power-up signal generator

TECHNICAL FIELD The present invention relates to semiconductor integrated circuits, and more particularly, to a power up signal generator for initialization.

Most semiconductor circuits go through a power on reset after the system is powered on. Therefore, when powered on, a signal for initializing a circuit is required, which is called a power up signal. The power-up signal rises together as the external power supply voltage VDD rises and then drops to a low level when the external power supply voltage VDD reaches a sufficient level.

1 is a circuit diagram illustrating a conventional power up signal generator.

As shown in FIG. 1, the power up signal generator 102 is supplied with a bias voltage from the bias voltage generator 104. The node 132 of the bias voltage generator 104 flows a bias current I _BIAS determined by the turn-on resistances of the PMOS transistor 106 and the NMOS transistor 108.

In the power up signal generator 102, the NMOS transistor 114 forms a current mirror so that the bias current I _BIAS is also supplied to the node 134. The voltage at node 134 is stored in a latch consisting of two inverters 138 and 140, and the output voltage of the latch is driven active by a series of inverter chains 128 and 130 connected in series, resulting in an active low. It is output as a power-up signal (/ PU) of (active low).

In bias voltage generator 104, the voltage at node 132 is determined by the turn on resistance of PMOS transistor 106 and NMOS transistor 108 of bias voltage generator 104. If the PMOS transistor 106 and the NMOS transistor 108 are made larger in size, the voltage at the node 132 is kept very low, and the NMOS transistor 114 of the power-up signal generator 102 generates a very small current path. To form.

When the external power supply voltage VDD is 2Vt or less, the voltage of the node 134 becomes a low level. Therefore, the voltage at the node 136 is at a high level so that the power-up signal / PU is also at a high level (disabled state). When the external power supply voltage VDD is greater than 2Vt, two PMOS transistors 110 and 112 connected in series are turned on so that the voltage of the node 134 increases along with the external power supply voltage VDD. 122 and PMOS transistor 116 are turned on so that the voltage at node 134 rises faster, the voltage at node 136 is further dropped so that the power-up signal / PU is at a low level (active state) ).

However, such a conventional power-up signal generator has the following problems.

First, the voltage of the node 134, which is the input of the latch circuit composed of two inverters 138 and 140, must be at a low level while the external power supply voltage VDD is not sufficiently increased at initial power-on. For this purpose, the NMOS capacitor 124 is connected between the node 134 and the ground VSS, and the PMOS capacitor 126 is connected between the node 136 and the external power supply voltage VDD. However, when the external power supply voltage VDD slowly rises, these two capacitors 124 and 126 have little effect. Therefore, the amount of current supplied to the node 134 through the current path by the two PMOS transistors 110 and 112 connected in series and the current path by the PMOS transistor 116 of the inverter 138 becomes excessively large. Therefore, even when the external power supply voltage VDD is still below the threshold voltage Vt, the voltage of the node 134 becomes higher than or equal to the logic threshold voltage of the inverter 140 to bring the voltage of the node 136 to a low level. Furthermore, even the power-up signal (/ PU) is activated at a low level. At this time, since the external power supply voltage VDD has not yet reached a sufficient level (2Vt or more), an abnormal power-up signal / PU has occurred.

Second, the internal supply voltage (V _PERI) power-up signal (/ PU) after reaching the required level of the internal power supply voltage (V _PERI) in the semiconductor circuit using a must be designed to fall to the low level. However, due to the first problem of the prior art mentioned above, an error may occur in which the power-up signal (/ PU) is activated before the external power supply voltage VDD and the internal power supply voltage V _PERI do not reach a sufficient level. have.

The purpose of the power-up signal generator according to the present invention is to provide a stable initialization by preventing an error that the initialization signal is generated when the external power supply voltage does not reach a sufficient voltage level.

The present invention for this purpose comprises an external initialization signal generator and an internal initialization signal generator.

The external initialization signal generator includes a first current mirror controlled by a bias voltage connected to the first node, a first active load, a first inverter circuit, and a second inverter circuit connected in series between an external power supply voltage and ground. The first inverter circuit and the second inverter circuit are supplied with power through the first active load, the voltage of the first node and the output of the second inverter circuit are input to the first inverter circuit, and the second terminal which is an output terminal of the first inverter circuit. The node is connected to the input of the second inverter circuit and the output of the first inverter circuit is configured to be output as a power up signal.

The internal initialization signal generator includes a second active load, a third active load, and a second current mirror connected in series between an internal power supply voltage and a ground, a second current mirror controlled by a second bias voltage, and a third active load. The third node to which the second current mirror is connected is made to be connected to the second node.

1 is a circuit diagram showing a conventional power-up signal generator.

2 is a circuit diagram illustrating a power up signal generator according to the present invention.

A preferred embodiment of the power up signal generator according to the present invention as described above will be described with reference to FIG. 2 is a circuit diagram illustrating a power up signal generator according to the present invention.

As shown in FIG. 2, the power up signal generator 202 is supplied with a bias voltage from the bias voltage generator 204. The node 236 of the bias voltage generator 204 flows a bias current I _BIAS determined by the turn-on resistances of the PMOS transistor 206 and the NMOS transistor 208.

In power up signal generator 202, NMOS transistor 114 coupled to node 238 is controlled by the bias voltage of node 236. The voltage at node 238 is stored in a latch consisting of two inverters 242 and 244, and the output voltage of the latch is driven active by a series of inverter chains 226 and 228 connected in series, resulting in an active low. It is output as a power-up signal (/ PU) of (active low).

Two inverter circuits 242 and 244, which are composed of CMOS, are supplied with power through a diode-connected PMOS transistor 212. The output of the inverter circuit 244 is connected to the input terminal of the inverter circuit 242, that is, the node 238. The NMOS transistor 210 and the two inverter circuits 242 and 244 generate an initialization signal by the external power supply voltage VDD, and thus may be referred to as an external initialization signal generator.

The NMOS transistor 236 forms a very small current path even when turned on by the bias voltage of the node 236 because the channel is very small. In order to generate a normal initialization signal by the external power supply voltage VDD, the voltage of the node 238 should be maintained at a low level while the external power supply voltage VDD is less than or equal to the threshold voltage Vt. The PMOS transistor 218 of the inverter circuit 242 is turned on to increase the voltage at the node 240. As a result, the NMOS transistor 216 of the inverter circuit 244 is turned on and the voltage at the node 238 is turned on. Is kept at a certain low level. At this time, only the PMOS transistors 212 and 214 increase the voltage of the node 238, and the PMOS transistor 214 is not turned on while the voltage of the node 240 is at a high level. Therefore, the voltage at the node 238 is kept at a low level while the external power supply voltage VDD is below Vt. At this time, the voltage of the node 240 is high level, and the power-up signal / PU is also high level (disabled state).

As the external power supply voltage VDD rises, the internal power supply voltage V _PERI also increases, but since the internal power supply voltage V _PERI has a lower potential than the external power supply voltage VDD, the relationship between VDD> V _PERI is always applied. Is established. In order for the initialization signal to be generated in the internal initialization signal generator 246, the internal power supply voltage V _PERI should be 2Vt or more. In order for the internal power supply voltage V _PERI to be 2Vt or more, the external power supply voltage VDD is 2Vt. Must have a much higher voltage level. Therefore, the node 240 remains at a high level until the external power supply voltage VDD reaches a voltage level high enough to generate an internal power supply voltage V _PERI greater than 2Vt, and the power-up signal (/ PU ) Also remains high (disabled).

When the external power supply voltage VDD keeps rising to generate a power-up signal / PU (external initialization), and the internal power supply voltage V _PERI exceeds 2Vt, the PMOS transistor of the internal initialization circuit 246 ( 230 and 232 are turned on to bring the voltage of node 240 to a high level. For this reason, the power-up signal / PU which was activated at the low level becomes inactive at the high level (end of initialization). That is, it can be seen that initialization (power up signal activation) by the external power supply voltage VDD and initialization (power up signal termination) by the internal power supply voltage V _PERI are normally performed.

The power-up signal generator according to the present invention enables stable initialization by preventing an error that an initialization signal occurs when the external power supply voltage does not reach a sufficient voltage level.

Claims (6)

A first current mirror controlled by a bias voltage is connected to the first node, a first active load and a first inverter circuit and a second inverter circuit are connected in series between an external power supply voltage and ground, and the first inverter circuit The second inverter circuit is supplied with power through the first active load, the voltage of the first node and the output of the second inverter circuit are input to the first inverter circuit, which is an output terminal of the first inverter circuit. An external initialization signal generator configured to connect a second node to an input of the second inverter circuit and to output an output of the first inverter circuit as a power up signal; A second active load and a third active load and a second current mirror are connected in series between an internal power supply voltage and ground, the second current mirror is controlled by the second bias voltage, and the third active load and the third And an internal initialization signal generator configured to connect a third node to which a second current mirror is connected to the second node. The power up signal generator of claim 1, wherein the internal initialization signal generator is configured to operate by receiving an internal power supply voltage. The power up signal generator of claim 1, wherein the external initialization signal generator is configured to operate by receiving an external power supply voltage. The power up signal generator of claim 1, wherein an NMOS capacitor and a PMOS capacitor are connected to the first node and the second node, respectively. The power up signal generator of claim 1 wherein the first and second active loads are diode coupled PMOS transistors. The power up signal generator of claim 1, wherein the first and second current mirrors are NMOS transistors.