KR100374548B1 - Data line pre-sensing circuit for memory cell - Google Patents
Data line pre-sensing circuit for memory cell Download PDFInfo
- Publication number
- KR100374548B1 KR100374548B1 KR1019950070193A KR19950070193A KR100374548B1 KR 100374548 B1 KR100374548 B1 KR 100374548B1 KR 1019950070193 A KR1019950070193 A KR 1019950070193A KR 19950070193 A KR19950070193 A KR 19950070193A KR 100374548 B1 KR100374548 B1 KR 100374548B1
- Authority
- KR
- South Korea
- Prior art keywords
- circuit
- cell
- data
- data line
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
Landscapes
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
본 발명은 메모리셀의 데이타라인 프리센싱회로에 관한 것으로, 종래의 셀 회로에 있어서는 비트라인 풀업회로 및 칩선택회로에 엔모스트랜지스터를 사용하게 되어 있어 비트라인의 신호 레벨이 엔모스의 VT만큼의 전압 드롭이 발생되고, 이에 의해 센싱속도가 떨어지는 문제점이 있었다. 본 발명은 이러한 종래의 문제점을 해결하기 위해 리드/라이트시 상기 셀(12)의 비트라인(BIT),(BITB)측으로 전원단자전압(Vcc)을 공급하는 엔-비피유와, 외부의 각종 제어신호에 따라 데이타를 저장하거나 이미 저장된 데이타를 출력하는 셀과, 데이타라인의 등화 및 풀업기능을 담당하는 데이타라인 등화 및 풀업부로 구성된 셀 회로에 있어서, 전원전압(VCC)과 병렬접속되어 항상 온되어 있는 피모스트랜지스터(PM1PM2)와 데이타라인(DBL),(DL)의 전위에 따라 온되어 풀업되는 피모스트랜지스터(PM3,PM4)로 구성된 프리센싱회로부를 더 포함하여 구성한 메모리셀의 데이타라인 프리센싱회로를 창안한 것으로, 이와같이 데이타라인과 센스앰프사이에 프리센싱회로부를 추가하여 데이타라인의 전압차를 크게 함므로써 센스앰프의 입력레벨을 안정케 할 수 있고, 저전전압단자전압 특성을 개선할 수 있는 효과가 있다.The present invention relates to a data line pre-sensing circuit of a memory cell. In a conventional cell circuit, an NMOS transistor is used for a bit line pull-up circuit and a chip select circuit, so that the signal level of the bit line is as much as V T of the NMOS. There is a problem that the voltage drop is generated, thereby reducing the sensing speed. In order to solve the conventional problems, the present invention provides an N-P-U which supplies a power terminal voltage Vcc to the bit lines BIT and BITB of the cell 12 during read / write, and various external controls. A cell circuit comprising a cell for storing data in accordance with a signal or outputting already stored data, and a data line equalization and pull-up part for equalizing and pulling up data lines. The cell circuit is always connected in parallel with a power supply voltage VCC. Data line pre-sensing of the memory cell further comprising a pre-sensing circuit unit comprising PMO transistors PM1PM2 and PMO transistors PM3 and PM4 turned on and pulled up according to potentials of the data lines DBL and DL. The circuit is designed to stabilize the input level of the sense amplifier by increasing the voltage difference between the data lines by adding a presensing circuit portion between the data line and the sense amplifier. There is an effect capable of improving the voltage terminal voltage characteristic.
Description
본 발명은 메모리셀의 데이타라인 프리센싱회로에 관한 것으로, 특히 데이타라인과 센스앰프 사이에 프리센싱회로를 추가하여 저전전압단자전압 특성을 개선하는데 적당하도록 한 메모리셀의 데이타라인 프리센싱회로에 관한 것이다.The present invention relates to a data line presensing circuit of a memory cell, and more particularly, to a data line presensing circuit of a memory cell suitable for improving a low voltage terminal voltage characteristic by adding a presensing circuit between the data line and the sense amplifier. will be.
제1도는 일반적인 메모리셀의 비트라인 풀업 회로도로서, 이의 작용을 설명하면 다음과 같다.FIG. 1 is a bit line pull-up circuit diagram of a general memory cell. The operation thereof is as follows.
먼저, 라이트 사이클(Write Cycle)에서, 엔-비피유(1)는 항시 턴온되어 있고, 선택된 로우(ROW)의 워드라인(WL)이 인에이블되며, 선택된 컬럼(Columm)의 칩선택신호(C/S)를 인에이블시켜 "하이" 또는 "로우"의 데이타를 셀(2)에 라이트(Write)한다.First, in the write cycle, the N-PUI 1 is always turned on, the word line WL of the selected ROW is enabled, and the chip select signal C of the selected column C. / S) is enabled to write "high" or "low" data to the cell 2.
이후, 등화신호(EQN)로 비트라인과 데이타라인을 등화시켜 레벨이 안정되게 한다. 이후, 라이트인에이블신호가 디스에이블되고, 워드라인(WL)이 인에이블되어 셀(2)의 "하이", "로우" 레벨이 컬럼선택선을 통해 센스앰프 측으로 출력된다.Thereafter, the bit line and the data line are equalized with the equalization signal EQN to stabilize the level. Thereafter, the write enable signal is disabled, the word line WL is enabled, and the " high " and " low " levels of the cell 2 are output to the sense amplifier through the column select line.
그러나, 이와 같은 종래의 셀 회로에 있어서는 비트라인 풀업회로 및 칩선택회로에 엔모스트랜지스터를 사용하게 되어 있어 비트라인의 신호 레벨이 엔모스의 VT만큼의 전압 드롭이 발생되고, 이에 의해 센싱속도가 떨어지는 문제점이 있었다.However, in such a conventional cell circuit, the EnMOS transistor is used in the bit line pull-up circuit and the chip select circuit, so that the voltage drop of the bit line is as much as V T of the NMOS. There was a problem falling.
따라서, 본 발명은 이를 해결하기 위하여 데이타라인과 센스앰프 사이에 프리센싱회로부를 추가하여 데이타라인의 전압차를 크게함으로써 센스앰프의 입력레벨을 안정되게 하여 센싱속도를 향상시킨 메모리셀의 데이타라인 프리센싱회로를 제공하는데 있다.Accordingly, in order to solve this problem, the present invention adds a pre-sensing circuit unit between the data line and the sense amplifier to increase the voltage difference of the data line to stabilize the input level of the sense amplifier, thereby improving the sensing speed. To provide a sensing circuit.
제2도는 상기의 목적을 달성하기 위한 본 발명 메모리셀의 데이타라인 프리센싱회로도로서, 이에 도시한 바와같이 제어신호에 따라 데이타를 저장/출력하는 셀(12)과, 리드/라이트시 상기 셀(12)의 비트라인 (BIT),(BITB)측으로 전원단자전압(Vcc)을 공급하는 엔-비피유(11)와, 데이타라인의 등화 및 풀업기능을 담당하는 테이타라인등화및풀업부(13)와: 데이타라인(DL),(DBL)의 출력신호를 증폭하여 출력하는 센스앰프(14)로 구성된 셀 회로에 있어서, 전원진압(VCC)과 병렬접속되어 항상 온되어 있는 피모스트랜지스터(PM1PM2)와 데이타라인(DBL),(DL)의 전위에 따라 온되어 풀업되는 피모스트랜지스터(PM3,PM4)로 구성된 프리센싱회로부(14)를 더 포함하여 구성한 것으로, 이와 같이 구성한 본 발명의 작용 및 효과를 첨부한 제3도 및 제4도를 참조하여 상세히 설명하면 다음과 같다.FIG. 2 is a data line pre-sensing circuit diagram of a memory cell of the present invention for achieving the above object. As shown in FIG. 2, a cell 12 storing / outputting data in accordance with a control signal, and the cell during read / write, N-BP (11) for supplying the power terminal voltage (Vcc) to the bit lines (BIT) and (BITB) side of 12), and the data line equalization and pull-up section 13 for equalizing and pulling-up functions of the data lines. And a cell circuit composed of a sense amplifier 14 for amplifying and outputting the output signals of the data lines DL and DBL, wherein the PMOS transistor PM1PM2 is always connected in parallel with the power supply voltage suppressor VCC. And a pre-sensing circuit unit 14 including PMOS transistors PM3 and PM4 which are turned on and pulled up according to potentials of the data lines DBL and DL. With reference to Figures 3 and 4 attached to the following Same as
먼저, 라이트 사이클에서, 선택된 로우(LOW)의 워드라인(WL)를 인에이블시키고, 칩선택신호(CS)에 의해 선택된 컬럼이 인에이블되며, 라이트인에이블신호(WE)가 구동되어 데이타(D), (DB)가 셀(12)에 라이트된다.First, in the write cycle, the word line WL of the selected LOW is enabled, the column selected by the chip select signal CS is enabled, and the write enable signal WE is driven to drive the data D. ) And (DB) are written to the cell 12.
라이트시 하이 도는 로우 데이타는 데이타라인의 프리센싱회로부(15)에 의해서 보다 안정된 동작을 하게된다.The high data during writing is more stable by the presensing circuit 15 of the data line.
한편, 리드 사이클에서, 워드라인(WL)을 인에이블시켜 라이트된 데이타를 리드하게되는 패스를 열어준다.On the other hand, in the read cycle, the word line WL is enabled to open a path for reading the written data.
이후, 칩선택신호(CS)는 인에이블 시키면, 데이타라인의 하이 또는 로우 전압차는 상기 프리센싱회로부(15)에 의해 보다 증폭되어 센스앰프(14)에 전달된다.After that, when the chip select signal CS is enabled, the high or low voltage difference of the data line is further amplified by the presensing circuit 15 to be transmitted to the sense amplifier 14.
참고로, 제3도 및 제4도는 종래의 회로와 본 발명에 의한 셀노드전압 및 데이타라인의 전압을 비교한 것이다.For reference, FIGS. 3 and 4 compare conventional cell and cell node voltage and data line voltage according to the present invention.
이상에서 상세히 설명한 바와 같이, 본 발명은 데이타라인과 센스앰프 사이에 프리센싱회로부를 추가하여 데이타라인의 전압차를 크게 함으로써 센스앰프의 입력레벨을 안정케 할 수 있고, 저전전압단자전압 특성을 개선할 수있는 효과가 있다.As described in detail above, the present invention can increase the voltage difference between the data line by adding a presensing circuit portion between the data line and the sense amplifier to stabilize the input level of the sense amplifier and improve the low voltage terminal voltage characteristics. There is an effect that can be done.
제1도는 일반적인 메모리셀의 비트라인 풀업 회로도.1 is a bit line pull-up circuit diagram of a typical memory cell.
제2도는 본 발명 메모리셀의 데이타라인 프리센싱회로도.2 is a data line pre-sensing circuit diagram of a memory cell of the present invention.
제3도는 종래의 회로와 본 발명에 의한 셀노드전압을 비교한 그래프.3 is a graph comparing a cell node voltage according to a conventional circuit with the present invention.
제4도는 종래의 회로와 본 발명에 의한 데이타라인전압을 비교한 그래프.4 is a graph comparing a data line voltage according to a conventional circuit with the present invention.
************ 도면의 주요부분에 대한 부호의 설명 ************************ Explanation of symbols on the main parts of the drawing ************
11 : 엔-비피유 12 : 셀11: n-Bl 12: cell
13 : 데이타라인등화및풀업부 14 : 센스엠프13: data line equalization and pull-up part 14: sense amplifier
15 : 프리센싱회로부15: presensing circuit
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950070193A KR100374548B1 (en) | 1995-12-31 | 1995-12-31 | Data line pre-sensing circuit for memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950070193A KR100374548B1 (en) | 1995-12-31 | 1995-12-31 | Data line pre-sensing circuit for memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR970051289A KR970051289A (en) | 1997-07-29 |
| KR100374548B1 true KR100374548B1 (en) | 2003-05-12 |
Family
ID=37416794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950070193A Expired - Fee Related KR100374548B1 (en) | 1995-12-31 | 1995-12-31 | Data line pre-sensing circuit for memory cell |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100374548B1 (en) |
-
1995
- 1995-12-31 KR KR1019950070193A patent/KR100374548B1/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR970051289A (en) | 1997-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7626877B2 (en) | Low voltage sense amplifier and sensing method | |
| KR910008101B1 (en) | Feedback type data output circuit of semiconductor memory device | |
| EP1614118B1 (en) | Low-voltage sense amplifier and method | |
| US5291447A (en) | Semiconductor memory device having function of controlling sense amplifiers | |
| KR100197757B1 (en) | Dynamic Semiconductor Memory Device | |
| KR100402243B1 (en) | Semiconductor memory device with improved peripheral circuit | |
| KR940004515B1 (en) | Dynamic semiconductor memory device | |
| US5883846A (en) | Latch type sense amplifier having a negative feedback device | |
| KR0184092B1 (en) | Dynamic type memory | |
| KR950014908B1 (en) | Read circuit of semiconductor memory | |
| KR910008100B1 (en) | Semiconductor memory device | |
| KR100281125B1 (en) | Nonvolatile Ferroelectric Memory Device | |
| KR100322541B1 (en) | Input and output line equalizing circuit and memory device having the same | |
| US6909644B2 (en) | Semiconductor memory device | |
| US7821817B2 (en) | Semiconductor storage device | |
| US5886936A (en) | Memory cell data line equalization controlling circuit for semiconductor memory device | |
| KR910004733B1 (en) | Semiconductor memory device having data bus reset circuit | |
| US5247482A (en) | Semiconductor memory device with high speed write operation | |
| KR100374548B1 (en) | Data line pre-sensing circuit for memory cell | |
| KR100301811B1 (en) | Column selecting circuit | |
| KR20080047157A (en) | Sense Amplifier Power Supply Circuit for Semiconductor Memory Devices | |
| KR19990015874A (en) | A column selection line driving method, a column selection line driving signal control circuit used therefor, and a semiconductor memory device having the same | |
| KR100374546B1 (en) | Bpu control circuit of memory cell | |
| KR19990016994A (en) | Semiconductor memory device | |
| KR100209339B1 (en) | Write driver circuit in semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19951231 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 20001025 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19951231 Comment text: Patent Application |
|
| N231 | Notification of change of applicant | ||
| PN2301 | Change of applicant |
Patent event date: 20020225 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20030129 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20030219 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20030220 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20060118 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20061211 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20080102 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20090121 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100126 Start annual number: 8 End annual number: 8 |
|
| FPAY | Annual fee payment |
Payment date: 20110126 Year of fee payment: 9 |
|
| PR1001 | Payment of annual fee |
Payment date: 20110126 Start annual number: 9 End annual number: 9 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20130109 |