KR100372769B1 - Method for manufacturing fine pattern of semiconductor device - Google Patents
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- KR100372769B1 KR100372769B1 KR1019950066088A KR19950066088A KR100372769B1 KR 100372769 B1 KR100372769 B1 KR 100372769B1 KR 1019950066088 A KR1019950066088 A KR 1019950066088A KR 19950066088 A KR19950066088 A KR 19950066088A KR 100372769 B1 KR100372769 B1 KR 100372769B1
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 32
- 229920005989 resin Polymers 0.000 claims abstract description 28
- 239000011347 resin Substances 0.000 claims abstract description 28
- 239000004642 Polyimide Substances 0.000 claims abstract description 4
- 229920001721 polyimide Polymers 0.000 claims abstract description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 8
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 claims description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 125000006239 protecting group Chemical group 0.000 claims description 6
- 238000010511 deprotection reaction Methods 0.000 claims description 5
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 claims description 4
- PPBRXRYQALVLMV-UHFFFAOYSA-N Styrene Chemical compound C=CC1=CC=CC=C1 PPBRXRYQALVLMV-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 4
- 238000007654 immersion Methods 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 238000010539 anionic addition polymerization reaction Methods 0.000 claims description 2
- 238000010538 cationic polymerization reaction Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims description 2
- 238000000576 coating method Methods 0.000 claims description 2
- 239000012454 non-polar solvent Substances 0.000 claims description 2
- 239000002798 polar solvent Substances 0.000 claims description 2
- 238000010526 radical polymerization reaction Methods 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 150000001450 anions Chemical class 0.000 claims 1
- 239000007864 aqueous solution Substances 0.000 claims 1
- 150000001768 cations Chemical class 0.000 claims 1
- 229920000642 polymer Polymers 0.000 claims 1
- 239000000243 solution Substances 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 6
- 239000000805 composite resin Substances 0.000 abstract description 2
- 229920003986 novolac Polymers 0.000 abstract description 2
- 238000005979 thermal decomposition reaction Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 38
- 239000010410 layer Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000003513 alkali Substances 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006884 silylation reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Materials For Photolithography (AREA)
Abstract
본발명은 반도체소자의 미세패턴 제조방법에 관한 것으로서, 화학 증폭형 포지티브 레지스트의 열적 분해 성질을 이용하는 것으로서, 피식각층상에 스페이스가 작은 라인/스페이스 형상의 감광막패턴을 형성하고, 상기 노출되어있는 피식각층상에 열에 강한 노블락(Novolac) 레진이나 폴리이미드 등의 유기 합성물 수지막을 도포한 후, 열을 가하여 상기 감광막패턴을 탈보호시켜 느슨한 구조로 만든 후, 감광막 패턴을 제거하여 상기 감광막패턴과는 반전된 상을 가지는 미세 선폭의 수지막 패턴을 형성하므로, 공정이 간단하고, 분해능 한계치 이하의 미세 패턴을 용이하개 형성하여 소자의 고집적화에 유리하며, 공정 여유도가 증가되어 규정수율 및 소자 동작의 신뢰성을 향상시킬 수 있다.The present invention relates to a method for manufacturing a micropattern of a semiconductor device, which utilizes the thermal decomposition property of a chemically amplified positive resist, and forms a line / space-shaped photoresist pattern having a small space on an etched layer, and exposes the exposed pattern. After applying an organic composite resin film such as Novolac resin or polyimide that is resistant to heat on each layer, heat is applied to deprotect the photoresist pattern to form a loose structure, and then the photoresist pattern is removed to reverse the photoresist pattern. Since the resin film pattern having a fine line width is formed, the process is simple, and the micro pattern below the resolution limit is easily formed, which is advantageous for the high integration of the device, and the process margin is increased, so that the reliability of the specified yield and the operation of the device are increased. Can improve.
Description
본 발명은 원자외선(Deep Ultra Violet; 이하 DUV라 칭함)용 화학증폭형 감광막의 보호기가 가지는 열적 성질을 이용하여, 용이하게 분해능 한계치 이하의 미세 패턴을 형성하여 소자의 고집적화에 유리하고, 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 미세패턴 제조방법에 관한 것이다.The present invention utilizes the thermal properties of the protecting group of a chemically amplified photosensitive film for deep ultra violet (hereinafter referred to as DUV) to easily form a fine pattern below a resolution limit, which is advantageous for high integration of devices, and a process yield. And it relates to a method of manufacturing a fine pattern of a semiconductor device capable of improving the reliability of device operation.
최근 반도체 장치의 고집적화 추세는 미세 패턴 형성기술의 발전에 큰 영향을 받고 있으며, 반도체 장치의 제조 공정 중에서 식각 또는 이온 주입 공정 등의 마스크로 매우 폭 넓게 사용되는 감광막패턴의 미세화가 필수요건이다.Recently, the trend of high integration of semiconductor devices has been greatly influenced by the development of fine pattern formation technology, and the miniaturization of photoresist patterns, which are widely used as masks such as etching or ion implantation processes, are essential in the manufacturing process of semiconductor devices.
종래 기술에 따른 감광막패턴의 제조 공정을 살펴보면 다음과 같다.Looking at the manufacturing process of the photosensitive film pattern according to the prior art as follows.
먼저, 소정의 하부구조가 형성되어 표면이 굴곡진 패턴을 형성하고자 하는 반도체기판상에 감광제 및 수지(resin) 등이 용제인 솔벤트에 일정 비율로 용해되어 있는 감광액을 도포하여 감광막을 형성한 후, 투명 기판상에 상기 감광막에서 패턴으로 예정되어 있는 부분에 대응되는 위치에 광차단막 패턴이 형성되어있는 노광마스크를 사용하여 빛을 선택적으로 조사하여 패턴으로 예정된 부분을 중합시킨다.First, a photoresist is formed by applying a photoresist in which a predetermined substructure is formed to form a curved pattern on the surface of the semiconductor substrate to which a photoresist and a resin are dissolved in a solvent at a predetermined ratio. A light mask is formed on a transparent substrate at a position corresponding to a portion of the photoresist that is intended as a pattern to selectively irradiate light to polymerize the predetermined portion of the pattern using an exposure mask.
그다음 상기 노광 공정을 진행한 웨이퍼를 열처리 장치에서 80∼120℃의 온도로 60~120초간 소프트 베이크 열처리 공정을 실시한 후, TMAH(tetra methyl ammonium hydroxide)를 주원료로 하는 약알칼리성 현상액을 사용하여 상기 감광막의 노광/비노광 영역들을 선택적으로 제거하고, 상기 웨이퍼를 탈이온수로 세척한 후, 건조시켜 감광막 패턴을 형성한다.Then, the wafer subjected to the exposure process was subjected to a soft bake heat treatment process at a temperature of 80 to 120 ° C. for 60 to 120 seconds in a heat treatment apparatus, and then using the weak alkaline developer containing TMAH (tetra methyl ammonium hydroxide) as a main raw material. The exposed / non-exposed areas of are selectively removed, the wafer is washed with deionized water and then dried to form a photoresist pattern.
상기 감광막패턴의 분해능(R)은 축소노광장치의 광원의 파장(λ) 및 공정변수(k)에 비례하고, 노광장치의 렌즈구경(numerical aperture; NA)에 반비례한다.The resolution R of the photoresist pattern is proportional to the wavelength? And the process variable k of the light source of the reduction exposure apparatus, and inversely proportional to the numerical aperture NA of the exposure apparatus.
여기서 상기 축소노광장치의 광분해능을 향상시키기 위하여 광원의 파장을 감소시키게 되며, 예를 들어 파장이 436 및 365nm인 G-라인 및 i-라인 축소노광장치는 공정 분해능이 각각 약 0.7 및 0.5㎛ 정도가 한계이다.Here, the wavelength of the light source is reduced to improve the optical resolution of the reduced exposure apparatus. For example, the G-line and i-line reduced exposure apparatus having wavelengths of 436 and 365 nm have a process resolution of about 0.7 and 0.5 µm, respectively. Is the limit.
따라서 0.5㎛ 이하의 미세 패턴을 형성하기 위해 파장이 작은 원자외선(deep ultra violet), 예를 들어 파장이 248nm인 KrF 레이저나 193nm인 ArF 레이저를 광원으로 사용하는 노광장치를 이용하거나, 이미지 콘트라스트를 향상시킬 수 있는별도의 박막을 웨이퍼 상에 형성하는 씨.이.엘(contrast enhancement layer; CEL) 방법 또는 위상반전 마스크를 사용하기도 한다.Therefore, in order to form a fine pattern of 0.5 μm or less, an exposure apparatus using a deep ultra violet, for example, a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm, may be used as a light source, or image contrast may be used. A CEL method or a phase inversion mask may be used to form a separate thin film on the wafer which can be improved.
그러나 장비의 광원을 미세 파장으로 바꾸는 데에도 한계가 있으며, 상기 CEL 방법은 공정이 복잡하고, 수율이 떨어진다.However, there is a limit in converting the light source of the equipment to the fine wavelength, and the CEL method is complicated and the yield is low.
또한 종래 기술의 다른 실시예로서, 단층 레지스트 방법보다는 두개의 감광막 사이에 중간층을 개재시킨 TLR 방법은 공정변수가 작아 단층 감광막 방법에 비해 약 30% 정도 분해능이 향상되어 0.25㎛ 정도의 미세 패턴 형성이 가능하나, 265M 또는 1G DRAM 이상의 고집적 반도체소자에서 필요한 0.2㎛ 정도의 패턴 형성이 어려워 소자의 고집적화에 한계가 있다.In addition, as another embodiment of the prior art, the TLR method in which an intermediate layer is interposed between two photoresist layers is smaller than a single layer resist method, and thus the resolution of the TLR method is improved by about 30% compared to the single layer photoresist method. Although it is possible, pattern formation of about 0.2 μm that is required in highly integrated semiconductor devices of 265M or 1G DRAM or more is difficult, and thus high integration of devices is limited.
또한 이러한 한계를 극복하기 위하여 감광막의 상측에 선택적으로 실리콘을 주입시키는 실릴레이션 공정을 이용하는 방법 등이 개발되어 분해능 한계치를 낮추고 있으나, 공정이 복잡하고, 재현성이 떨어져 공정수율 및 소자 동작의 신뢰성이 떨어지는 문제점이 있다.In addition, in order to overcome this limitation, a method using a silylation process that selectively injects silicon into the upper side of the photoresist film has been developed to lower the resolution limit, but the process is complicated and the reproducibility is low, resulting in poor process yield and device operation reliability. There is a problem.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로서, 본 발명의 목적은 DUV용 화학증폭형 감광막의 보호기가 가지는 열적 성질을 이용하여, 용이하게 분해능 한계치 이하의 미세 패턴을 형성하여 소자의 고집적화에 유리하고, 공정여유도를 증가시켜 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 반도체소자의 미세패턴 제조방법을 제공함에 있다.The present invention is to solve the above problems, an object of the present invention by using the thermal properties of the protecting group of the chemically amplified photosensitive film for DUV, it is easy to form a fine pattern below the resolution limit, which is advantageous for high integration of the device In addition, the present invention provides a method of manufacturing a fine pattern of a semiconductor device which can improve process yield and reliability of device operation by increasing process margin.
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 미세패턴 제조방법의 특징은,Features of the method for manufacturing a fine pattern of a semiconductor device according to the present invention for achieving the above object,
피식각층 상에 화학증폭형 포지티브 감광막을 형성하는 공정과,Forming a chemically amplified positive photoresist film on the etched layer;
라인이 스페이스보다 큰 듀티 레시오(Duty Ratio)를 갖는 노광마스크를 이용하여, 상기 감광막을 선택 노광하여 라인이 스페이스보다 큰 선폭을 갖는 감광막패턴을 형성하는 공정과,Forming a photoresist pattern having a line width greater than a space by selectively exposing the photoresist by using an exposure mask having a duty ratio with a line larger than a space;
상기 감광막패턴에 의해 노출되어있는 피식각층상에 수지막을 형성하는 공정과,Forming a resin film on the etched layer exposed by the photosensitive film pattern;
상기 구조의 수지막과 감광막패턴을 열처리하여 상기 감광막패턴에 탈보호 현상이 일어나도록 하는 공정과,Heat-treating the resin film and the photoresist pattern of the structure to cause a deprotection phenomenon on the photoresist pattern;
상기 감광막패턴을 제거하여 수지막 패턴을 형성하는 공정과,Removing the photosensitive film pattern to form a resin film pattern;
상기 수지막 패턴을 식각 마스크로 피식각층을 식각하여 피식각층 패턴을 형성하는 공정을 구비함에 있다.And etching the etching layer using the resin film pattern as an etching mask to form an etching layer pattern.
이하, 본 발명에 따른 반도체소자의 미세패턴 제조방법에 관하여 첨부 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a fine pattern of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제 1A 도 내지 제 1D 도는 본 발명에 따른 반도체소자의 미세패턴 제조 공정도이다.1A to 1D are process diagrams for manufacturing a fine pattern of a semiconductor device according to the present invention.
먼저 양이온 중합, 음이온 중합 또는 라디칼 중합 등의 방법으로 합성된 분자량 100~1,000,000의 PHS(polyhydroxy styrene) 과 같은 매트릭스 레진으로 된 화학증폭형 포지티브 감광막(2)을 피식각층 기판(1)상에 스핀 도포 또는 담금 방법으로 0.1∼100㎛ 정도의 두께로 도포한 후, 상기 감광막(2)을 라인/스페이스의 광차단막 패턴(7)이 투명한 석영기판(6)상에 형성되어있는 노광마스크(5)를 사용하여선택적으로 노광한다. 이때 상기 감광막(2)은 t-BOC등 모든 종류의 보호기가 포함되어 있는 DUV나 E-빔 또는 X-선용 감광막(2)이며, 상기 노광마스크(5)는 라인이 스페이스에 비해 큰 듀티 레시오를 갖는다 (제 1A 도 참조).First, spin-coating a chemically amplified positive photoresist film 2 made of a matrix resin such as polyhydroxy styrene (PHS) having a molecular weight of 100 to 1,000,000 synthesized by a method such as cationic polymerization, anionic polymerization or radical polymerization, on the etched layer substrate 1 Alternatively, after the coating is applied to a thickness of about 0.1 to 100 μm, the exposure mask 5 having the photoresist film 2 formed thereon on the transparent quartz substrate 6 with the line / space light blocking film pattern 7 Selective exposure. At this time, the photosensitive film 2 is a DUV, E-beam, or X-ray photosensitive film 2 including all kinds of protecting groups such as t-BOC, and the exposure mask 5 has a duty ratio of which the line is larger than the space. (See also FIG. 1A).
그 다음 상기 감광막(2)의 노광영역을 0.01∼100wt% 농도의 TMAH, NaOH, KOH 또는 LiOH 등의 알카리 용액으로 된 현상액을 사용하여 퍼블(pubble)이나 담금 방법으로 제거하여 라인이 스페이스보다 큰 선폭을 갖는 라인/스페이스 패턴으로된 감광막(2) 패턴을 형성한다 (제 1B 도 참조).Then, the exposure area of the photosensitive film 2 is removed by a pubble or immersion method using a developer solution of an alkali solution such as TMAH, NaOH, KOH, or LiOH at a concentration of 0.01 to 100 wt%, so that the line width is larger than the space. A photosensitive film 2 pattern having a line / space pattern having the same was formed (see also FIG. 1B).
그후, 상기 감광막(2) 패턴에 의해 노출되어있는 피식각층 기판(1) 상에, 즉 감광막(2) 패턴 사이사이에, 열에 강한 재질, 예를 들어 노볼락 계통이나 폴리 이미드 등의 유기 고분자로 된 수지막(3)을 스핀 도포나 담금 방법으로 0.1∼100㎛ 정도의 두께로 형성한다 (제 1C 도 참조).Subsequently, on the etched layer substrate 1 exposed by the photosensitive film 2 pattern, that is, between the photosensitive film 2 patterns, a material resistant to heat, for example, an organic polymer such as a novolac series or polyimide. The resin film 3 is formed to a thickness of about 0.1 to 100 µm by spin coating or dipping (see FIG. 1C).
그 다음 상기 구조의 기판(1)을 10℃~500℃의 정도의 온도에서 열처리하면, DUV용 화학 증폭형 포지티브 감광막(2) 패턴에 포함되어있는 t-BOC기 등의 보호기가 열에 의해 분리되는 탈보호 현상이 발생하므로, 상기 감광막(2)패턴들의 사이에 형성되어있는 수지막(3)은 열에 의해 경화되어 수지막(3)패턴이 되고, 감광막(2) 패턴은 탈보호 현상에 의해 현상액에 쉽게 용해되는 성질로 변환된다. 참고로, 화학증폭형 포지티브 감광막에 포함되어 있는 보호기는 노광에 의해 생성된 프로톤(Proton; H)에 의하여 탈리되어, 노광부와 비노광부의 용해도 차이에 의해 패턴을 형성하게 하는 역할을 하는데, 이러한 탈보호 현상은 노광뿐만 아니라 열에 의해서도 진행된다.Subsequently, when the substrate 1 having the above structure is heat-treated at a temperature of about 10 ° C. to 500 ° C., a protecting group such as a t-BOC group included in the DUV chemically amplified positive photosensitive film 2 pattern is separated by heat. Since the deprotection phenomenon occurs, the resin film 3 formed between the photosensitive film 2 patterns is cured by heat to form the resin film 3 pattern, and the photosensitive film 2 pattern is developed by the deprotection phenomenon. It is converted into a property that is easily dissolved in For reference, the protecting group included in the chemically amplified positive photoresist film is detached by Proton (H) generated by exposure, and serves to form a pattern due to the difference in solubility of the exposed portion and the non-exposed portion. The deprotection phenomenon proceeds not only by exposure but also by heat.
상기 열처리 후, 상기 감광막(2) 패턴을 전술한 알카리성 현상액으로 제거하여 감광막(2) 패턴에 비하여 미세한 선폭을 갖는 수지막(3) 패턴을 형성한다. (제 1D 도 참조).After the heat treatment, the photosensitive film 2 pattern is removed with the above-described alkaline developer to form a resin film 3 pattern having a finer line width than the photosensitive film 2 pattern. (See also FIG. 1D).
그 다음 도시되어있지는 않으나, 상기 수지막(3) 패턴을 식각마스크로 사용하여 상기 피식각층 기판(1)을 제거하여 피식각층 패턴을 형성한다.Next, although not shown, the etched layer substrate 1 is removed by using the resin film 3 pattern as an etch mask to form an etched layer pattern.
여기서 상기 화학 증폭형 포지티브 감광막(2) 또는 수지막(3)을 형성하는데 사용하는 용액에는 모든 종류의 비극성 또는 극성 용매가 사용될 수 있다.Here, any kind of nonpolar or polar solvent may be used for the solution used to form the chemically amplified positive photosensitive film 2 or the resin film 3.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 미세패턴 제조방법은 화학 증폭형 포지티브 레지스트의 열적 분해 성질을 이용하는 것으로서, 피식각층 상에 스페이스가 작은 라인/스페이스 형상의 감광막패턴을 형성하고, 상기 노출되어있는 피식각층 상에 열에 강한 노블락 레진이나 폴리이미드 등의 유기 합성물 수지막을 도포한 후, 열을 가하여 상기 감광막패턴을 탈보호시켜 느슨한 구조로만든 후, 감광막패턴을 제거하여 상기 감광막패턴과는 반전된 상을 가지는 미세 선폭의 수지막 패턴을 형성하므로, 공정이 간단하고, 분해능 한계치 이하의 미세 패턴을 용이하게 형성하여 소자의 고집적화에 유리하며, 공정 여유도가 증가되어 공정수율 및 소자 동작의 신뢰성을 향상시킬 수 있는 이점이 있다.As described above, the method for manufacturing a micropattern of a semiconductor device according to the present invention uses a thermal decomposition property of a chemically amplified positive resist, and forms a line / space-shaped photoresist pattern having a small space on an etched layer. After applying an organic composite resin film, such as noblock resin or polyimide, which is resistant to heat on the exposed layer, the photoresist pattern is deprotected by applying heat to form a loose structure, and then the photoresist pattern is removed to remove the photoresist pattern. Since the resin film pattern of the fine line width having the inverted phase is formed, the process is simple, and the micro pattern below the resolution limit is easily formed, which is advantageous for the high integration of the device, and the process margin is increased to increase the process yield and the operation of the device. There is an advantage to improve the reliability.
제 1A 도 내지 제 1D 도는 본발명에 따른 반도체소자의 미세패턴 제조 공정도.1A to 1D are fine pattern manufacturing process diagrams of a semiconductor device according to the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 피식각층 기판 2 : 화학증폭형 감광막DESCRIPTION OF SYMBOLS 1 Substrate to be etched 2 Chemically amplified photosensitive film
3 : 수지막 5 : 노광마스크3: resin film 5: exposure mask
6 : 석영기판 7 : 광차단막 패턴6: quartz substrate 7: light blocking film pattern
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100806807B1 (en) * | 2001-06-19 | 2008-02-22 | 엘지.필립스 엘시디 주식회사 | Photoresist stripper and manufacturing method of liquid crystal display device using same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558531A (en) * | 1978-10-25 | 1980-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Fine processing |
| JPH0220016A (en) * | 1988-07-08 | 1990-01-23 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH05251335A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Manufacture of semiconductor device |
| JPH06252040A (en) * | 1993-02-23 | 1994-09-09 | Mitsubishi Electric Corp | Method of forming resist pattern and resist surface acid-treatment device |
| JPH06267812A (en) * | 1993-03-12 | 1994-09-22 | Matsushita Electric Ind Co Ltd | Fine pattern forming material and pattern forming method |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5558531A (en) * | 1978-10-25 | 1980-05-01 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Fine processing |
| JPH0220016A (en) * | 1988-07-08 | 1990-01-23 | Seiko Epson Corp | Manufacture of semiconductor device |
| JPH05251335A (en) * | 1992-03-09 | 1993-09-28 | Nec Corp | Manufacture of semiconductor device |
| JPH06252040A (en) * | 1993-02-23 | 1994-09-09 | Mitsubishi Electric Corp | Method of forming resist pattern and resist surface acid-treatment device |
| JPH06267812A (en) * | 1993-03-12 | 1994-09-22 | Matsushita Electric Ind Co Ltd | Fine pattern forming material and pattern forming method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100806807B1 (en) * | 2001-06-19 | 2008-02-22 | 엘지.필립스 엘시디 주식회사 | Photoresist stripper and manufacturing method of liquid crystal display device using same |
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