KR100372646B1 - Method for making a vertical type transistor using a standard semiconductor process - Google Patents

Abstract

The present invention relates to a method of manufacturing a vertical transistor using a standard semiconductor process, and etching a part of the upper silicon layer using a photolithography method, and then performing an ion implantation process to form a source or drain region, Removing the upper silicon layer for isolation between devices using a photolithography method, forming an interlayer insulating film, and planarizing the interlayer insulating film using chemical mechanical polishing, wet or dry etching the planarized interlayer insulating film Etching to form a thickness remaining from the boundary between the upper silicon layer and the buried oxide film using the method, forming the gate oxide film and the gate material successively, and planarizing the gate material by using chemical mechanical polishing, and then wet or dry etching. The gate material of a predetermined thickness is etched using, and then an interlayer insulating film is formed. Etching the formed gate material and the interlayer dielectric using a photolithography method; etching the interlayer dielectric using a photolithography method to form a source or drain region of the device; ion implantation or epitaxial growth Forming doped polycrystalline silicon by a method, and then forming a source or drain region of the device using a photolithography method, and using a vertical transistor device fabricated on a double-layer silicon wafer, The fabrication of the above highly integrated DRAM device and the fabrication of high performance complementary metal oxide semiconductor field effect transistors and integrated circuits are possible.

Description

Method for manufacturing vertical transistor using standard semiconductor process {METHOD FOR MAKING A VERTICAL TYPE TRANSISTOR USING A STANDARD SEMICONDUCTOR PROCESS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a vertical transistor using a standard semiconductor process. In particular, in order to fabricate a device having a gate length of 0.1 μm or less, the vertical length of which the gate length is determined by the thickness of the gate material rather than the photo printing process By fabricating a transistor device on a double-layer silicon wafer, a method of manufacturing a vertical transistor using a standard semiconductor process that can achieve perfect separation between devices and improvement of device reliability, as well as devices having a gate length of 0.1 μm or less. will be.

Increasingly high integration, high speed, and low power characteristics of integrated circuits using semiconductor devices have been continued, and methods for solving many problems in the process of obtaining the above characteristics have been steadily presented.

The method generally pursued for high integration, high speed, and low power has been to reduce the gate length of the transistor device.

As described above, when the gate length of the device is reduced, the gate oxide film, the junction depth, and the doping concentration of the substrate should be simultaneously optimized to ensure stable operation of the device.

In DRAM devices, since the memory capacity must be increased while minimizing the increase in chip size, the gate length of the cell transistor is expected to be 0.1 μm or less in a DRAM device of 4G class or more.

Therefore, in order to reproducibly secure a gate length of 0.1 μm or less, a photo printing apparatus should be preceded. However, even if a commercially available DUV device or an ArF or KrF device is being developed, a gate length of 0.1 μm or less must be secured. It is expected to be hard.

Therefore, in order to develop DRAM devices of 4G class or more in the future, the development of a photo printing apparatus for securing a gate length of 0.1 μm or less, and the minimum gate length of the element is not limited by the limitation of the photo printing apparatus. Development is urgent.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem. In order to fabricate a device having a gate length of 0.1 μm or less, a vertical transistor device having a gate transistor whose thickness is determined by the thickness of a gate material rather than a photo printing process is used. It is an object of the present invention to provide a method of manufacturing a vertical transistor using a standard semiconductor process capable of achieving perfect separation between devices, improvement of device reliability, as well as devices having a gate length of 0.1 μm or less by fabricating on a wafer.

1 is a cross-sectional view of a bilayer silicon wafer.

FIG. 2 is a cross-sectional view after etching a part of the upper silicon layer 3 using a photolithography method and then performing an ion implantation process to form a source or drain region.

3 is a cross-sectional view of the structure formed in FIG. 2 after the upper silicon layer is removed for separation between devices using a photolithography method;

4 is a cross-sectional view after the interlayer insulating film is formed in the structure formed in FIG. 3 and planarized by chemical mechanical polishing;

FIG. 5 is a cross-sectional view of the planarized interlayer insulating film of FIG. 4 after being etched using a wet or dry etching method to leave a predetermined thickness from a boundary between the upper silicon layer and the buried oxide film.

FIG. 6 illustrates that the gate oxide layer and the gate material are successively formed in the structure of FIG. 5, the gate material is planarized by chemical mechanical polishing, and the gate material having a predetermined thickness is etched by wet or dry etching. After that, the cross-sectional view after forming the interlayer insulating film.

FIG. 7 is a cross-sectional view after etching the gate material and the interlayer insulating film formed in FIG. 6 using a photolithography method; FIG.

8 is a cross-sectional view after etching the interlayer insulating film using a photolithography method to form a source or drain region of the device in FIG.

FIG. 9 is a cross-sectional view after forming polycrystalline silicon doped by an ion implantation method or epitaxial growth method in the structure of FIG. 8 and then forming a source or drain region of the device using a photolithography method. FIG.

10 is a three-dimensional view of a vertical transistor device formed through the process of FIGS. 1-9.

11 is a flow chart showing a process sequence of a method of manufacturing a vertical transistor using a standard semiconductor process of the present invention.

<Description of Symbols for Main Parts of Drawings>

1 silicon wafer substrate 2 buried oxide layer

3: upper silicon layer 4: lower source or drain region

5, 8: interlayer insulating film 6: gate oxide film

7: gate material 9: source or drain region on top

In order to achieve the above object, a method of manufacturing a vertical transistor using a standard semiconductor process according to the present invention may include forming a buried layer and an upper silicon layer on a silicon substrate, and then removing a portion of the upper silicon layer using a photolithography method. After etching, performing an ion implantation process for forming a lower source / drain region on the etched upper silicon layer, and etching the upper silicon layer implanted for separation between devices by using a photolithography method to etch the lower source or drain. Forming a first interlayer insulating film on a substrate including a lower source or a drain, and planarizing the first interlayer insulating film using a chemical mechanical polishing method, and partially etching the planarized first interlayer insulating film. Etching away from the boundary between the upper silicon layer and the buried oxide film to leave a predetermined thickness; A gate oxide film and a gate material are successively formed on the substrate, the gate material is planarized by chemical mechanical polishing, and the gate material having a predetermined thickness is etched by wet or dry etching, and then the second interlayer insulating film is removed. Forming, etching the gate material and the second interlayer insulating film using a photolithography method, etching the second interlayer insulating film to expose the remaining upper silicon layer, and etching the portion of the second interlayer insulating film. After forming the polycrystalline silicon doped by any one of the ion implantation method and epitaxial growth method, and forming a top source or drain using a photolithography method.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

11 is a flowchart showing a process procedure of a method of manufacturing a vertical transistor using a standard semiconductor process of the present invention.

As shown in FIG. 11, in the method of manufacturing a vertical transistor using a standard semiconductor process of the present invention, after etching a portion of the upper silicon layer using a photolithography method, an ion implantation process is performed to form a source or drain region. In step (S10), the step of removing the upper silicon layer for separation between devices using a photolithography method (S20), forming an interlayer insulating film, and planarizing the interlayer insulating film using a chemical mechanical polishing method ( S30), etching the planarized interlayer insulating film by using a wet or dry etching method so as to leave a predetermined thickness from the boundary between the upper silicon layer and the buried oxide film (S40), successively forming the gate oxide film and the gate material, and chemical mechanical After the gate material is planarized using magic, the gate material of a certain thickness is etched using wet or dry etching, Forming an interlayer insulating film (S50), etching the formed gate material and the interlayer insulating layer using a photolithography method (S60), and forming an interlayer insulating layer using a photolithography method to form a source or drain region of the device. Etching step (S70), after forming the doped polycrystalline silicon by the ion implantation method or epitaxial growth method, and forming a source or drain region of the device using a photolithography method (S80).

In detail, it is as follows.

The lower source or drain is formed through ion implantation and diffusion, and the thickness of the upper silicon layer of the lower source or drain region is adjusted to 100 nm or more.

In addition, the thickness of the upper silicon layer is controlled by the dry and wet etching methods, and the channel region is formed by the dry etching method.

After the gate material is formed, the gate length of the device is adjusted by an etching method, and dry and wet etching methods are used to etch the gate material, and the gate thickness is formed to be lower than the upper source or drain.

Meanwhile, after the doped epitaxial of about 10 nm is grown by epitaxial growth, doped polycrystalline silicon is formed, and an ion implantation method is used to form a thinly doped drain structure between the upper source or drain region and the channel. .

1 is a cross-sectional view of a bilayer silicon wafer. The thickness of the upper silicon layer 3 depends on the gate length of the device to be manufactured.

FIG. 2 is a cross-sectional view after etching a part of the upper silicon layer 3 using a photolithography method and then performing an ion implantation process to form a source or drain region. In this case, the thickness of the upper silicon layer 3 of the source / drain region remaining after etching may be about 100 nm or more to obtain stable resistance.

FIG. 3 is a cross-sectional view of the structure formed in FIG. 2 after removing the upper silicon layer to separate the devices by using a photolithography method.

FIG. 4 is a cross-sectional view after the interlayer insulating film 5 is formed in the structure formed in FIG. 3 and planarized by chemical mechanical polishing.

FIG. 5 is a cross-sectional view of the planarized interlayer insulating layer of FIG. 4 after etching to form a thickness remaining from a boundary between the upper silicon layer and the buried oxide layer using a wet or dry etching method.

FIG. 6 shows the gate oxide film 6 and the gate material 7 in succession with respect to the structure of FIG. 5, planarizes the gate material by chemical mechanical polishing, and then uses a wet or dry etching method to obtain a predetermined thickness. After etching the gate material, the cross-sectional view after forming an interlayer insulating film.

FIG. 7 is a cross-sectional view after etching the gate material 7 and the interlayer insulating film 8 formed in FIG. 6 using a photolithography method.

FIG. 8 is a cross-sectional view after etching an interlayer insulating film using a photolithography method to form a source or drain region of the device in FIG.

FIG. 9 is a cross-sectional view of an ion implantation method, an epitaxial growth method, and a doped polycrystalline silicon in the structure of FIG. 8, followed by forming a source or drain region of the device using a photolithography method.

FIG. 10 is a three-dimensional view of a vertical transistor device formed through the process of FIGS. 1 to 9.

The vertical transistor fabricated on the double-layer silicon wafer through the above process is 0.1 because the gate length of the device is not determined by the photo printing method as conventionally, but is controlled by dry or wet time performed after the formation of the gate material. It is easy to obtain a gate length of μm or less.

In addition, since the channel region of the fabricated vertical transistor element is completely surrounded by the gate, there is a characteristic that it is completely depleted at the gate voltage of 0V.

These fully depleted devices feature large current driving forces, ideal subcritical swings, and low threshold voltages.

In addition, since the vertical transistor device manufactured by the present invention is implemented in a double-layer silicon wafer, it is possible to completely separate between devices and has advantages such as durability against external high energy particles.

In addition, it is superior in the uniformity of the electrical characteristics of the device compared to the conventional vertical transistor device to form a channel using the epic growth method.

On the other hand, another embodiment of the present invention includes a method of manufacturing a vertical PMOS device.

As described above, the present invention uses a vertical transistor device fabricated on a double-layer silicon wafer, thereby making it possible to fabricate a high-density DRAM device of 4G class or higher, and to manufacture a high performance complementary metal oxide semiconductor field effect transistor and an integrated circuit. There is.

Claims (12)

Sequentially forming a buried layer and an upper silicon layer on the silicon substrate; Etching a portion of the upper silicon layer using a photolithography method, and performing an ion implantation process for forming a lower source / drain region on the etched upper silicon layer; Etching the ion implanted upper silicon layer to form a lower source or drain for separation between devices using a photolithography method; Forming a first interlayer insulating film on the substrate including the lower source or drain, and planarizing the first interlayer insulating film by chemical mechanical polishing; Partially etching the planarized first interlayer insulating layer to etch a predetermined thickness from a boundary between the remaining upper silicon layer and the buried oxide film; A gate oxide film and a gate material are successively formed on the resultant, the gate material is planarized by chemical mechanical polishing, and the gate material having a predetermined thickness is etched by wet or dry etching, and then interlayer between the second layers is formed. Forming an insulating film, Etching the formed gate material and the second interlayer insulating layer using a photolithography method; Etching the second interlayer insulating film to expose the remaining upper silicon layer; Forming a doped polycrystalline silicon on the etched portion of the second interlayer insulating film by any one of ion implantation and epitaxial growth, and then forming an upper source or a drain using a photolithography method. A method of manufacturing a vertical transistor using a standard semiconductor process. delete The vertical transistor of claim 1, wherein in the etching of a portion of the upper silicon layer using a photolithography method, a thickness of the upper silicon layer remaining after the etching is 100 nm or more. Method of preparation. The method of claim 3, wherein the thickness of the upper silicon layer is controlled by a dry etching method. The method of claim 3, wherein the thickness of the upper silicon layer is controlled by a wet etching method. The method of claim 1, wherein the channel region is formed by a dry etching method. The method of claim 1, wherein after the gate material is formed, the gate length of the device is adjusted by an etching method. 8. The method of claim 7 wherein a standard semiconductor process employs a dry etching method to etch the gate material. 8. The method of claim 7 wherein a standard semiconductor process employs a wet etching method to etch the gate material. 8. The method of claim 7, wherein the thickness of the gate is lower than the top source or drain. The method of manufacturing a vertical transistor using a standard semiconductor process according to claim 1, wherein after the doped epitaxial of about 10 nm is grown by epitaxial growth, a doped polycrystalline silicon is formed. delete