KR100363702B1 - Storage node contact plug of semiconductor device and method for forming thereof - Google Patents
Storage node contact plug of semiconductor device and method for forming thereof Download PDFInfo
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- KR100363702B1 KR100363702B1 KR1020000086409A KR20000086409A KR100363702B1 KR 100363702 B1 KR100363702 B1 KR 100363702B1 KR 1020000086409 A KR1020000086409 A KR 1020000086409A KR 20000086409 A KR20000086409 A KR 20000086409A KR 100363702 B1 KR100363702 B1 KR 100363702B1
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- interlayer insulating
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- insulating film
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- 238000003860 storage Methods 0.000 title claims abstract description 62
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000011229 interlayer Substances 0.000 claims abstract description 53
- 239000010410 layer Substances 0.000 claims abstract description 38
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 9
- 229920005591 polysilicon Polymers 0.000 abstract description 9
- 239000003990 capacitor Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
- H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체장치의 스토리지노드 전극용 콘택 플러그 제조 방법에 관한 것으로서, 특히 이 방법은 스토리지노드용 콘택 플러그를 형성하기 위해 식각 선택성이 있는 2층 이상의 층간 절연막에 상부는 좁고 하부는 상대적으로 넓은 측면 단차가 있는 스토리지노드용 콘택홀을 형성한 후에 폴리실리콘을 증착하고 전면 식각공정으로 콘택홀에 매립된 폴리실리콘을 분리하여 스토리지노드 콘택을 형성한 후에, 식각 정지막 및 희생 산화막을 적층하고 이를 패터닝하여 스토리지노드 전극의 영역을 확보하는데, 이때 상부의 제 2층간 절연막까지 식각해서 가운데 부분이 볼록한 凸구조의 콘택 플러그를 형성함으로써 스토리지노드 전극의 콘택 면적을 증가시킨다.The present invention relates to a method of manufacturing a contact plug for a storage node electrode of a semiconductor device, and in particular, the method has a narrow upper side and a relatively wide side on a two-layer interlayer insulating layer having an etch selectivity to form a contact plug for a storage node. After forming the contact hole for the storage node having a step, the polysilicon is deposited and the polysilicon embedded in the contact hole is separated by the front etching process to form the storage node contact, and then the etch stop layer and the sacrificial oxide layer are laminated and patterned. In this case, an area of the storage node electrode is secured. At this time, the contact area of the storage node electrode is increased by forming a contact plug having a concave-shaped concave structure by etching the upper second interlayer insulating film.
Description
본 발명은 반도체 장치의 제조 방법에 관한 것으로서, 특히 고집적 반도체 장치에서 스토리지노드 전극의 콘택 플러그 제조 공정시 콘택면의 접촉 면적을 증가시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a technology capable of increasing a contact area of a contact surface during a process of manufacturing a contact plug of a storage node electrode in a highly integrated semiconductor device.
최근의 반도체 장치는 디바이스가 고집적화됨에 따라 메모리 셀 크기가 점점 감소되면서 워드 라인과 커패시터 콘택, 비트라인과 커패시터 콘택의 마진이 점점 작아지면서 스토리지노드용 커패시터 콘택을 더욱 작게 형성해야만 한다.Recent semiconductor devices have to form smaller capacitor contacts for storage nodes as the margins of word lines and capacitor contacts, bit lines and capacitor contacts become smaller as the memory cell size decreases as the device becomes more integrated.
도 1은 종래 기술에 의해 반도체장치의 스토리지노드 전극 구조를 나타낸 평면도로서, 스토리지노드 전극 콘택(SNC) 마스크의 각격(b)이 매우 좁기 때문에 콘택홀에 폴리실리콘을 매립한 후에 CMP 공정시 브릿지가 발생할 가능성이 매우 크다.1 is a plan view illustrating a storage node electrode structure of a semiconductor device according to the prior art, and since the angle b of the storage node electrode contact (SNC) mask is very narrow, a bridge is formed in a CMP process after embedding polysilicon in a contact hole. It is very likely to occur.
도 2는 도 1의 A-A'선에 따라 자른 스토리지노드 전극 구조를 나타낸 수직 단면도이다.FIG. 2 is a vertical cross-sectional view illustrating a storage node electrode structure taken along the line AA ′ of FIG. 1.
도 2를 참조하면, 종래 기술의 스토리지노드 전극 제조 방법은 다음과 같다.Referring to Figure 2, the prior art storage node electrode manufacturing method is as follows.
우선, 필드 산화막(12)이 형성된 반도체기판(10)의 활성 영역에 소정의 소자 공정(게이트, 소스, 드레인 등)을 실시한 결과물 전체에 절연막(14)을 형성하고 비트라인 및 스토리지노드용 콘택 전극(16)을 먼저 형성한다. 그리고나서 절연막(18)을 형성하고 그 위에 비트라인(20)을 형성한다. 이때, 비트라인(20)은 폴리실리콘막(20a), 금속실리사이드(20b) 및 캐핑막(20c)이 적층된 형태이고 그 측면에 사이드월(20d)이 형성된다. 그리고, 그 위에 스토리지노드용 층간 절연막(22), 식각 정지막(26)을 적층한 후에 그 위에 스토리지노드 전극용 콘택 플러그의 마스크 패턴(미도시함)을 형성한다. 이때, 도면 부호 b은 콘택 플러그 사이의 간격을 나타낸 것이고 30은 스토리지노드 전극용 패턴의 공간을 확보하는 희생 절연막 패턴(28)의 개방 영역을 나타낸 것이다.First, an insulating film 14 is formed on the entire product resulting from performing a predetermined device process (gate, source, drain, etc.) in the active region of the semiconductor substrate 10 on which the field oxide film 12 is formed, and contact electrodes for bit lines and storage nodes. (16) is formed first. Then, an insulating film 18 is formed and a bit line 20 is formed thereon. In this case, the bit line 20 is formed by stacking the polysilicon film 20a, the metal silicide 20b, and the capping film 20c, and sidewalls 20d are formed on the side surfaces thereof. Subsequently, the interlayer insulating layer 22 and the etch stop layer 26 for the storage node are stacked thereon, and then a mask pattern (not shown) of the contact plug for the storage node electrode is formed thereon. In this case, reference numeral b denotes an interval between the contact plugs and 30 denotes an open area of the sacrificial insulating layer pattern 28 to secure a space of the pattern for the storage node electrode.
계속해서 마스크 패턴에 의해 드러나는 식각 정지막(26), 층간 절연막(22), 절연막(18)을 식각해서 하부의 콘택전극(16) 표면이 드러나는 콘택홀을 형성한다. 그리고, 도전체로서 폴리실리콘을 콘택홀에 갭필하고 CMP 등의 평탄화 공정으로 그 표면을 평탄화하여 스토리지노드 콘택 플러그(24)를 형성한다.Subsequently, the etch stop layer 26, the interlayer insulating layer 22, and the insulating layer 18 exposed by the mask pattern are etched to form contact holes that expose the surface of the lower contact electrode 16. As a conductor, polysilicon is gap-filled into the contact hole, and the surface thereof is planarized by a planarization process such as CMP to form the storage node contact plug 24.
그리고나서 스토리지노드 전극의 패턴 공간을 확보하기 위한 희생 절연막 패턴(28)을 형성한다.Then, a sacrificial insulating layer pattern 28 is formed to secure the pattern space of the storage node electrode.
그러나, 상기와 같은 종래 기술에 의한 방법에 있어서, 활성 영역정도로 스토리지노드 콘택 플러그의 폭을 형성하기 때문에 콘택 플러그사이의 공간 마진(b)이 매우 작아 셀 사이에서 브릿지가 발생하게 되는 경우가 발생하였다. 이와 같이 스토리지노드 콘택 플러그를 크게 하는 이유는 콘택 저항(즉 접촉 계면 저항)을 낮추어 반도체장치의 전기적 특성을 향상하기 위함이다.However, in the conventional method as described above, since the width of the storage node contact plug is formed to the extent of the active area, the space margin (b) between the contact plugs is so small that a bridge occurs between cells. . The reason for increasing the storage node contact plug is to lower the contact resistance (ie, contact interface resistance) to improve electrical characteristics of the semiconductor device.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위한 것으로 스토리지노드용 콘택 플러그를 형성하기 위해 식각 선택성이 있는 2층 이상의 층간 절연막에 상부는 좁고 하부는 상대적으로 넓은 측면 단차가 있는 스토리지노드용 콘택홀을 형성하고 이 콘택홀에 폴리실리콘 등의 스토리지노드용 콘택 플러그를 형성한 후에, 식각정지막 및 희생 절연막으로 스토리지노드 전극의 영역을 확보하는데, 이때 상부의 층간 절연막까지 식각해서 가운데 부분이 볼록한 凸구조의 콘택 플러그를 형성함으로써 스토리지노드 전극의 콘택 면적을 증가시키는 반도체장치의 스토리지노드 전극용 콘택 플러그 제조 방법을 제공하는데 있다.An object of the present invention is to solve such a problem of the prior art for forming a storage node contact plug for the storage node having a narrow upper side and a relatively wide side step in the two or more interlayer insulating film having an etch selectivity After forming a contact hole and forming a contact plug for a storage node such as polysilicon in the contact hole, the region of the storage node electrode is secured with an etch stop layer and a sacrificial insulating layer. The present invention provides a method for manufacturing a contact plug for a storage node electrode of a semiconductor device which increases a contact area of a storage node electrode by forming a contact plug having a convex fin structure.
도 1은 종래 기술에 의해 반도체장치의 스토리지노드 전극 구조를 나타낸 평면도,1 is a plan view showing a storage node electrode structure of a semiconductor device according to the prior art;
도 2는 도 1의 A-A'선에 따라 자른 스토리지노드 전극 구조를 나타낸 수직 단면도,FIG. 2 is a vertical cross-sectional view illustrating a storage node electrode structure taken along line AA ′ of FIG. 1;
도 3은 본 발명에 따른 반도체장치의 스토리지노드 전극 구조를 나타낸 평면도,3 is a plan view showing a storage node electrode structure of a semiconductor device according to the present invention;
도 4a 내지 도 4g는 본 발명에 따른 반도체장치의 스토리지노드 전극의 제조 공정을 설명하기 위하여 도 3의 B-B'선에 따라 자른 수직 단면도들.4A to 4G are vertical cross-sectional views taken along line BB ′ of FIG. 3 to illustrate a manufacturing process of a storage node electrode of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 반도체기판 102 : 필드 산화막100 semiconductor substrate 102 field oxide film
104,108 : 절연막 106 : 콘택 전극104,108 insulating film 106: contact electrode
110 : 비트라인110: bit line
112 : 스토리지노드용 제 1층간절연막112: first interlayer insulating film for storage node
114 : 스토리지노드용 제 2층간절연막114: second interlayer insulating film for storage node
116 : 스토리지노드용 콘택 마스크116: contact mask for storage nodes
118 : 콘택홀 118': 측면 단차가 있는 콘택홀118: contact hole 118 ': contact hole with a side step
120 : 콘택 플러그 122 : 식각정지막120: contact plug 122: etch stop film
124 : 희생 절연막 패턴 126 : 스토리지노드용 개구부124: sacrificial insulation pattern 126: opening for the storage node
127 : 상부 표면에서 가운데 부분이 볼록한 콘택 플러그127: contact plug with a convex center portion at the upper surface
이러한 목적을 달성하기 위하여 본 발명에 의한 반도체장치의 스토리지노드 전극의 콘택 플러그는 반도체장치의 스토리지노드 전극의 콘택 플러그에 있어서, 상기 스토리지노드 전극의 콘택 플러그의 상부 가운데에 콘택 사이즈보다 좁은 돌출부가 형성된 것을 특징으로 한다.In order to achieve the above object, a contact plug of a storage node electrode of a semiconductor device according to the present invention is a contact plug of a storage node electrode of a semiconductor device, wherein a protrusion narrower than a contact size is formed in an upper center of the contact plug of the storage node electrode. It is characterized by.
또한, 반도체장치의 스토리지노드 전극의 콘택 플러그 제조 방법에 있어서, 반도체 기판의 하부 구조물에 제 1층간절연막을 형성하는 단계와, 제 1층간절연막에 대해 식각선택비를 갖는 제 2층간절연막을 형성하는 단계와, 제 2층간 절연막에 디자인 룰에 의해 정해진 콘택 플러그의 마스크보다 소정 폭이 작은 마스크 패턴을 형성하는 단계와, 마스크 패턴을 이용한 식각 공정을 진행하여 제 2층간절연막 및 제 1층간절연막을 식각하여 콘택홀을 형성하는 단계와, 제 2층간 절연막을 제외한 제 1층간절연막만 선택 식각하여 콘택홀 내측벽에 단차를 형성하는 단계와, 측벽 단차를 갖는 콘택홀에 도전체를 매립하고 제 2층간 절연막 표면의 도전체가 제거되도록 평탄화하는 단계와, 평탄화된 결과물에 식각 정지막을 형성하고, 그 위에 스토리지노드 영역을 정의하는 희생 절연막 패턴을 형성하는 단계와, 희생 절연막 패턴에 맞추어 식각 정지막을 식각하는 단계와, 식각된 식각 정지막에 의해 드러난 제 2층간 절연막의 모서리를 식각해서 상부 표면의 가운데가 볼록한 콘택플러그를 형성한다.Further, in the method for manufacturing a contact plug of a storage node electrode of a semiconductor device, forming a first interlayer insulating film in a lower structure of a semiconductor substrate, and forming a second interlayer insulating film having an etch selectivity with respect to the first interlayer insulating film. Etching the second interlayer insulating film and the first interlayer insulating film by forming a mask pattern having a predetermined width smaller than the mask of the contact plug determined by the design rule in the second interlayer insulating film, and by performing an etching process using the mask pattern. Forming a contact hole, forming a step in the inner wall of the contact hole by selectively etching only the first interlayer insulating film excluding the second interlayer insulating film, and filling a conductor in the contact hole having the sidewall step Planarizing the conductive material on the surface of the insulating film, and forming an etch stop layer on the flattened product, and forming a storage node region thereon. Forming a sacrificial insulating film pattern to be defined; etching the etch stop film according to the sacrificial insulating film pattern; and etching a corner of the second interlayer insulating film exposed by the etch stop film to form a contact plug having a centered convex contact surface. Form.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명에 따른 반도체장치의 스토리지노드 전극 구조를 나타낸 평면도로서, 본 발명의 스토리지노드용 콘택 플러그의 마스크 패턴 사이의 간격(b')이 디자인 룰에서 정해진 것보다 작기 때문에 콘택 플러그 사이의 공간 마아진이 크다.3 is a plan view showing a storage node electrode structure of a semiconductor device according to the present invention. Since the spacing b 'between the mask patterns of the storage node contact plug of the present invention is smaller than that defined in the design rule, Space margin is large.
도 4a 내지 도 4g는 본 발명에 따른 반도체장치의 스토리지노드 전극의 제조 공정을 설명하기 위하여 도 3의 B-B'선에 따라 자른 수직 단면도들이다.4A to 4G are vertical cross-sectional views taken along the line BB ′ of FIG. 3 to explain a manufacturing process of the storage node electrode of the semiconductor device according to the present invention.
도 4a에 도시된 바와 같이, 반도체 기판에 소정의 소자 공정, 예컨대 필드 산화막(미도시함)과 게이트전극, 스페이서 및 소스/드레인 영역을 갖는 트랜지스터(미도시)를 형성하고, 콘택 전극(106) 및 비트라인(110) 제조 공정을 실시한다. 여기서, 미설명된 도면 부호 104 및 108은 절연막이고, 본 실시예에서의 비트라인(110)은 폴리실리콘막(110a), 금속실리사이드(110b) 및 캐핑막(110c)이 적층된 형태이고 그 측면에 사이드월(110d)이 형성된다.As shown in FIG. 4A, a predetermined device process, for example, a field oxide film (not shown) and a transistor (not shown) having a gate electrode, a spacer, and a source / drain region are formed on a semiconductor substrate, and the contact electrode 106 is formed. And a bit line 110 manufacturing process. Here, non-described reference numerals 104 and 108 are insulating films, and the bit line 110 in this embodiment has a form in which a polysilicon film 110a, a metal silicide 110b, and a capping film 110c are stacked and side surfaces thereof. The sidewall 110d is formed in this.
그 다음부터 본 발명에 의한 스토리지전극용 콘택 플러그 제조 공정에 대한 것이다.Then, the present invention relates to a process for manufacturing a contact plug for a storage electrode according to the present invention.
상기와 같은 반도체 기판의 하부 구조물에 제 1층간절연막(112)을 두껍게 형성하고, 그 위에 제 1층간절연막(112)에 대해 식각선택비를 갖는 제 2층간절연막(114)을 얇게 형성하는데 후속 스토리지노드용 콘택 플러그의 식각 마아진을 고려하여 그 두께를 결정한다. 이때, 제 1층간절연막(112)은 제 2층간절연막(114)보다 세정 공정에 대해 식각이 잘되는 산화물질을 사용하도록 한다. 예를 들면, 제 1층간절연막(112)은 바람직하게 BPSG이고 제 2층간절연막(114)은 HDP(High Density Plasma) 산화막이다.The first interlayer dielectric film 112 is formed thick in the lower structure of the semiconductor substrate as described above, and the second interlayer dielectric film 114 having an etch selectivity with respect to the first interlayer dielectric film 112 is formed thereon. The thickness is determined by considering the etch margin of the contact plug for the node. In this case, the first interlayer insulating film 112 may be formed of an oxide material having better etching for the cleaning process than the second interlayer insulating film 114. For example, the first interlayer insulating film 112 is preferably BPSG and the second interlayer insulating film 114 is a high density plasma (HDP) oxide film.
그리고 도 4b에 도시된 바와 같이 제 2층간 절연막(114)에 디자인 룰에 의해 정해진 콘택 플러그의 마스크보다 소정 폭이 작은 마스크 패턴(116)을 형성한다. 즉, 본 발명의 콘택 플러그용 마스크 패턴(116)은 종래보다 X축 및 Y축 모두 작게형성하는데, 그 이유는 이후 스토리지노드 콘택홀에 매립된 막을 평탄화할 때 스토리지노드 콘택 사이의 브릿지를 방지하기 위함이다.As shown in FIG. 4B, a mask pattern 116 having a predetermined width smaller than that of the contact plug mask determined by the design rule is formed in the second interlayer insulating film 114. That is, the mask pattern 116 for the contact plug of the present invention is formed smaller in both the X-axis and the Y-axis than the conventional one, because it prevents the bridge between the storage node contacts when planarizing the film embedded in the storage node contact hole. For sake.
도 4c에 도시된 바와 같이 마스크 패턴(116)을 이용한 식각 공정을 진행하여 제 2층간절연막(114) 및 제 1층간절연막(112)을 식각하여 하부에 있는 콘택 전극(106)가 드러나는 콘택홀(118)을 형성한 후에 마스크 패턴(116)을 제거한다.As shown in FIG. 4C, the etching process using the mask pattern 116 is performed to etch the second interlayer insulating layer 114 and the first interlayer insulating layer 112 to expose the contact electrode 106 below. After forming 118, the mask pattern 116 is removed.
그 다음 도 4d에 도시된 바와 같이, 제 2층간 절연막(114)을 제외한 제 1층간절연막(112')만 선택 식각하여 콘택홀 내측벽에 단차(118')를 형성한다. 이때, 선택 식각 공정은 제 1층간 절연막(112)을 식각할 수 있는 세정 공정을 이용한다. 예를 들면, BOE 또는 HF 딥 공정을 실시할 경우 제 1 및 제 2층간 절연막(112,114)의 물성 차이로 인해 아래에 있는 제 1층간 절연막(112')은 많이 식각되는 반면에, 위에 있는 제 2층간 절연막(114)은 거의 식각되지 않는다.Next, as shown in FIG. 4D, only the first interlayer insulating layer 112 ′ except for the second interlayer insulating layer 114 is selectively etched to form a step 118 ′ on the inner wall of the contact hole. In this case, the selective etching process uses a cleaning process capable of etching the first interlayer insulating layer 112. For example, when the BOE or HF dip process is performed, the lower first interlayer insulating layer 112 ′ is etched a lot due to the difference in physical properties of the first and second interlayer insulating layers 112 and 114, whereas the second upper layer is etched. The interlayer insulating film 114 is hardly etched.
이와 같이 본 발명은 제 1 및 제 2층간 절연막의 선택 식각에 의해 스토리지노드 전극 용 콘택홀 사이의 공간 마진이 종래보다 크기 때문에 이후 스토리지노드 전극 사이의 브릿지를 막을 수 있다.As described above, the present invention can prevent the bridge between the storage node electrodes since the space margin between the contact holes for the storage node electrodes is larger than the conventional one by the selective etching of the first and second interlayer insulating films.
도 4e에 도시된 바와 같이, 측벽 단차를 갖는 콘택홀(118')에 도전체로서 폴리실리콘을 매립하고 제 2층간 절연막(114) 표면의 폴리실리콘이 제거되도록 CMP 등의 평탄화 공정을 진행하여 스토리지노드용 콘택 플러그(120)를 형성한다. 이때, 콘택 플러그(120)의 공간 마아진이 종래 기술의 것보다 크게 된다.As shown in FIG. 4E, the polysilicon is embedded as a conductor in the contact hole 118 ′ having the sidewall step and the planarization process such as CMP is performed to remove the polysilicon on the surface of the second interlayer insulating layer 114. The node contact plug 120 is formed. At this time, the space margin of the contact plug 120 is larger than that of the prior art.
계속 해서 도 4f에 도시된 바와 같이, 평탄화된 결과물에 식각 정지막(122)으로서 실리콘질화막을 형성하고, 그 위에 스토리지노드 영역을 정의하는 희생 절연막 패턴(124)을 형성한다. 이때, 희생 절연막 패턴(124) 또한 종래 기술의 것보다 폭이 넓어지게 된다.Subsequently, as shown in FIG. 4F, a silicon nitride film is formed as an etch stop film 122 on the flattened resultant, and a sacrificial insulating film pattern 124 defining a storage node region is formed thereon. At this time, the sacrificial insulating layer pattern 124 also becomes wider than that of the prior art.
이어서 도 4g에 도시된 바와 같이, 희생 절연막 패턴(124)에 맞추어 식각 정지막(122)을 식각하고, 식각된 식각 정지막(122')에 의해 드러난 제 2층간 절연막(114)의 모서리를 식각해서 상부 표면의 가운데가 볼록(127)한 콘택 플러그(127)를 형성한다. 이러한 식각 공정에 의해 스토리지노드 콘택 플러그(120)의 표면뿐만 아니라 측벽 부위도 개방된다. 즉, 본 발명의 콘택 플러그(127)는 상부면이 凸 구조의 단차를 갖고 있기 때문에 표면적이 증가하게 되어 이후 형성될 스토리지노드 전극과의 접촉 면적이 증가하고 이로 인해 콘택의 계면 저항이 크게 줄어들게 된다.Subsequently, as illustrated in FIG. 4G, the etch stop layer 122 is etched in accordance with the sacrificial insulation pattern 124, and the edges of the second interlayer insulating layer 114 exposed by the etch stop layer 122 ′ are etched. As a result, a contact plug 127 is formed in which the center of the upper surface is convex 127. The etching process opens not only the surface of the storage node contact plug 120 but also the sidewall portion. That is, since the contact plug 127 of the present invention has a stepped structure of the top surface, the surface area is increased, thereby increasing the contact area with the storage node electrode to be formed, thereby greatly reducing the interface resistance of the contact. .
한편, 도면 부호 126은 희생 절연막 패턴(124) 사이의 개방 영역에 도전체를 증착하여 본 발명에 따른 콘택 플러그(120)에 연결될 스토리지노드 전극의 예정 영역을 나타낸 것이다.Meanwhile, reference numeral 126 denotes a predetermined region of the storage node electrode to be connected to the contact plug 120 according to the present invention by depositing a conductor in an open region between the sacrificial insulating layer patterns 124.
상술한 바와 같이, 본 발명은 스토리지노드용 콘택 플러그 제조 공정시 식각 선택성이 있는 층간 절연막을 2층이상 증착하고 산화 세정 공정을 실시하여 층간 절연막에 단차가 있는 콘택홀을 형성하고 스토리지노드 식각 패턴을 종래보다 작게 함으로써 스토리지노드 사이의 공간 마아진을 넓힌다.As described above, the present invention is to deposit at least two layers of an interlayer insulating film having an etch selectivity during the manufacturing process of the contact plug for the storage node and to perform an oxide cleaning process to form a stepped contact hole in the interlayer insulating film and to form the storage node etching pattern. By making it smaller than before, the space margin between storage nodes is expanded.
또한, 본 발명은 후속 스토리지노드 전극의 영역을 확보하기 위한 희생 절연막 식각 공정시 층간 절연막의 상부 모서리도 함께 식각함으로써 콘택 플러그의 상부면에 단차를 두어 스토리지노드 전극과의 콘택 면적을 넓힌다. 이에 따라, 스토리지노드 전극에 의한 콘택 저항을 줄여 고집적 반도체장치의 전기적 특성을 향상시킨다.In addition, according to the present invention, the upper edge of the interlayer insulating film is also etched during the sacrificial insulating film etching process to secure the region of the storage node electrode, thereby increasing the contact area with the storage node electrode by providing a step on the top surface of the contact plug. Accordingly, the electrical resistance of the highly integrated semiconductor device is improved by reducing the contact resistance caused by the storage node electrode.
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| CN112951769A (en) * | 2021-03-19 | 2021-06-11 | 长鑫存储技术有限公司 | Semiconductor memory and forming method thereof |
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