KR100357041B1 - Low Voltage Current Sensing Amplifier - Google Patents

Abstract

The present invention relates to a semiconductor memory, and more particularly to a bit line sense amplifier of a semiconductor memory device. SUMMARY OF THE INVENTION An object of the present invention is to provide a bit line sense amplifier of a semiconductor memory device capable of performing fast sensing by minimizing time delay even during low voltage operation. According to an aspect of the present invention, in a bit line sense amplifier of a semiconductor memory device, the bit line sense amplifier includes first and second current mirrors to receive potentials of the positive bit line and the sub bit line as current sources, and to the sense amplification enable signal. A current sensing means for sensing the current levels of the positive bit line and the sub bit line in response and outputting the result to the positive output terminal and the sub output terminal, and a signal sensed by the current sensing means in response to the sense amplification enable signal. There is provided a bit line sense amplifier of a semiconductor memory device having a feedback means for amplifying a voltage difference of the feedback terminal and feeding it back to the positive output terminal and the negative output terminal.

Description

Bitline Sense Amplifiers in Semiconductor Memory Devices

The present invention relates to a semiconductor memory, and more particularly to a bit line sense amplifier of a semiconductor memory device.

A bit line sense amplifier is a high-gain, wideband amplifier that senses the potential of a corresponding bit line pair and amplifies it to a logic level. Most of the bit line sense amplifiers sense and amplify voltage levels.

Recently, as the low voltage of personal portable equipment and memory devices becomes more common, a method of sensing and amplifying a voltage level has a relatively low current driving capability, and thus, it takes a long time to form a certain level of voltage for voltage sensing. That is, when ΔV = Δt (I / C), the current I decreases, and when the capacitor capacitance C increases, the time Δt required to obtain a constant ΔV increases, thereby increasing the data sensing amplification time.

1 is a circuit diagram of a conventional voltage sense amplifier.

As shown in the figure, the conventional voltage sense amplifier detects the voltage level of the positive bit line (BIT) and the sub bit line (BITB) in response to the sense amplification enable signal SAE1 and performs a first-order amplification. (current mirror type) the first amplification stage 100 and the output signal of the first amplification stage 100 in the second response in response to the sense amplification enable signal (SAE2) by the secondary output terminal (OUT) and the sub-output terminal (OUTB) The second amplifier stage 110 of the cross-coupled type and a sense amplifier enable signal SAE2 are output in response to the sense amplification enable signal SAE2. It is composed of a precharge and equalization unit 120 to precharge and equalize. Here, the current mirror type first amplification stage 100 and the cross coupled second amplification stage 110 have a structure of a general sense amplifier.

When the conventional voltage sense amplifier configured as described above operates at a low voltage level, the voltage sense amplifier of the voltage sense amplifier is formed until the voltage level of the bit line BIT and the bit line BITB is formed at a constant level for voltage sensing. Since the sensing amplification operation does not occur and the sensing amplification operation is performed through the first amplifying stage 100 and the second amplifying stage 110 only after the voltage reaches a predetermined level, the time required for the entire data sensing amplification is increased. there was.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a bit line sense amplifier of a semiconductor memory device capable of performing fast sensing by minimizing time delay even in a low voltage operation.

1 is a circuit diagram of a conventional bit line sense amplifier.

2 is a circuit diagram of a bitline sense amplifier in accordance with an embodiment of the present invention.

3 is a waveform diagram of a simulation of the bit line sense amplifier of FIG. 2 with respect to an arbitrary voltage difference between a positive bit line and a bit line.

FIG. 4 is a waveform diagram of a simulation of the bit line sense amplifier of FIG. 1 with respect to an arbitrary voltage difference between a positive bit line (BIT) and a sub bit line (BITB). FIG.

5 is a simulation result waveform diagram of a bit line sense amplifier of the present invention according to a change in supply voltage.

Figure 6 is a waveform diagram of a comparison simulation of the bit line sense amplifier according to the present invention and the conventional bit line sense amplifier.

7 is a waveform diagram simulating comparison of current consumption when enabling a bit line sense amplifier and a conventional bit line sense amplifier according to the present invention.

* Explanation of symbols for the main parts of the drawings

200: current sensing unit

210: feedback unit

220: precharge and equalization unit

According to an aspect of the present invention for achieving the above technical problem, a bit line sense amplifier of a semiconductor memory device, comprising a first and second current mirror to receive the potential of the positive bit line and the sub bit line as a current source And current sensing means for sensing current levels of the positive bit line and the sub bit line in response to a sense amplification enable signal, and outputting the results to the positive output terminal and the sub output terminal, and in response to the sense amplification enable signal. A bit line sense amplifier of a semiconductor memory device having a feedback means for amplifying a voltage difference of a signal sensed by the current sensing means and feeding back to the positive output terminal and the sub output terminal is provided.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2 is a circuit diagram of a bit line sense amplifier according to an embodiment of the present invention.

Referring to FIG. 2, the bit line sense amplifier according to the present embodiment includes a plurality of current mirrors, and receives a positive bit line and a sub bit line (BIT, BITB) as a power source of each current mirror, and detects the current. In response to the amplification enable signal SAE, a sensing operation is performed on current levels of the bit line BIT and the bit line BITB, and the result is output to the positive output terminal OUT and the negative output terminal OUTB. Amplifies the voltage difference with respect to the signal sensed by the current sensing unit 200 in response to the current sensing unit 200 and the sensing amplification enable signal SAE, and feeds it back to the positive output terminal OUT and the negative output terminal OUTB. Precharge and equalize the pre-charge and equalize the output terminal OUT and the output terminal OUTB when the sense amplifier is disabled in response to the output feedback unit 210 and the sense amplification enable signal SAE. It is made of a part 220.

In more detail, the current sensing unit 200 includes a PMOS transistor P1 and P2 having a drain terminal connected to each of the positive bit line BIT and the sub bit line BITB and connected to each other in a current mirror type. NMOS transistors N1 and N2 connected to the source terminals of the PMOS transistors P1 and P2 and receiving the sense amplification enable signal SAE through their respective gates, and the drain terminals include a positive bit line and a bit bit. PMOS transistors P3 and P4, which are connected to the line BITB and are connected to each other in a current mirror type, are connected to source terminals of the PMOS transistors P3 and P4, respectively, and sense amplification enable signals SAE are connected to respective gates. And NMOS transistors N3 and N4 that receive. The constant output terminal OUT is a common connection terminal of the PMOS transistor P1 and the NMOS transistor N1, and the sub output terminal OUTB is a common connection terminal of the PMOS transistor P4 and the NMOS transistor N4. The source terminal of the NMOS transistor N1 and the source terminal of the NMOS transistor N3 are commonly connected, and the source terminal of the NMOS transistor N2 and the source terminal of the NMOS transistor N4 are commonly connected.

Next, the feedback unit 210 includes an inverter having an input terminal connected to a common connection terminal of the PMOS transistor P1 and the NMOS transistor N1, and an output terminal connected to a common source terminal B of the NMOS transistors N2 and N4. 211, an inverter 212 having an input terminal connected to a common connection terminal of the PMOS transistor P4 and an NMOS transistor N4, and an output terminal connected to a common source terminal A of the NMOS transistors N1 and N3, and a ground; And an NMOS transistor N7 coupled to the power supply terminal and serving as a current source of inverters 211 and 212 in response to the sense amplification enable signal SAE. The inverter 211 is connected in series between the power supply voltage terminal and the drain terminal of the NMOS transistor N7, and the PMOS transistor P6 having its gate connected to the common connection terminal of the PMOS transistor P1 and the NMOS transistor N1, and NMOS transistor (N6), the inverter 212 is connected in series between the power supply voltage terminal and the drain terminal of the NMOS transistor (N7), each gate is a common connection terminal of the PMOS transistor P4 and NMOS transistor (N4) PMOS transistor P5 and NMOS transistor N5 connected to each other.

Next, the precharge and equalization unit 220 receives a sense amplification enable signal SAE through a gate, and the common source terminal A of the NMOS transistors N1 and N3 and the NMOS transistors N2 and N4. A PMOS transistor P7 and a sense amplification enable signal connected between the common source stage B to equalize the common source stages A and B to ensure stable sense amplification operation when the sense amplifier is disabled. In response to SAE, the PMOS transistors P8 and P10 for precharging the positive output terminal OUT and the negative output terminal OUTB to the power supply voltage level, respectively, and the positive output signal in response to the sense amplification enable signal SAE. OUT) and a PMOS transistor P9 for equalizing the negative output signal OUTB.

Hereinafter, the operation of the bit line sense amplifier configured as described above will be described.

For convenience of description, it is assumed that high level data is loaded on the bit line BIT and low level data is transferred to the sub bit line BITB.

As soon as the sense amplification enable signal SAE transitions from "low" to "high", the current sense amplifier according to the present embodiment starts a sensing operation. That is, unlike the conventional voltage sense amplifier, the sense amplification enable signal SAE is enabled "high" and starts the sensing operation regardless of the voltage difference between the positive bit line BIT and the sub bit line BITB. do. PMOS transistors P1 and NMOS transistors N1 according to the current levels applied to the respective drains of the PMOS transistors P1, P2, P3, and P4 by the PMOS transistors P1, P2, P3, and P4 configured in the current mirror form. The amount of charges at the common connection terminal and the common connection terminal of the PMOS transistor P4 and the NMOS transistor N4 is determined.

When high level data is transferred to the positive bit line BIT, the amount of charge accumulated at the common connection terminal of the PMOS transistor P1 and the NMOS transistor N1 is accumulated at the common connection terminal of the PMOS transistor P4 and the NMOS transistor N4. The NMOS transistor N6 of the inverter 211 whose input terminal is connected to the common connection terminal of the PMOS transistor P1 and the NMOS transistor N1 is turned on because it is larger than the amount of charge. Therefore, the level of the common source terminal B of the NMOS transistors N2 and N4 changes rapidly to 0V, so that the common connection terminal of the PMOS transistor P4 and the NMOS transistor N4 also changes to 0V at a high speed. At this time, the PMOS transistor P5 of the inverter 212 whose input terminal is connected to the common connection terminal of the PMOS transistor P4 and the NMOS transistor N4 is turned on so that the PMOS transistor P1 and the NMOS transistor N1 are common. The connection stage changes rapidly to a high level. As a result, a high level output signal is output from the common connection terminal of the PMOS transistor P1 and the NMOS transistor N1 through the current sense amplifier according to the present invention, and the common of the PMOS transistor P4 and the NMOS transistor N4. An output signal of 0V is output from the connection terminal.

Contrary to the operation description, when the low level data is loaded on the bit line BIT and the high level data is loaded on the sub bit line BITB, the sensing amplification is performed in the same manner as the above operation.

FIG. 3 is a waveform diagram of a simulation of the bit line sense amplifier of FIG. 2 when the voltage difference between the bit line BIT and the bit line BITB is 10, 30, 50, 70, 90, or 110 mV. FIG. 4 is a waveform diagram of the bit line sense amplifier of FIG. 1 when the voltage difference between the positive bit line BIT and the sub bit line BITB is 10, 30, 50, 70, 90, and 110 mV.

3 and 4, the current sense amplifier according to the present invention performs a stable sensing operation compared to the conventional voltage sense amplifier of the same size, and also, the positive bit line (BIT) and the sub bit line (BITB) It can be seen that a fast sense amplification operation is performed regardless of the voltage difference.

5 is a simulation waveform diagram of the bit line sense amplifier of the present invention according to the change of the supply voltage, it can be seen that the bit line sense amplifier according to the present invention performs a stable sense amplification operation at a supply voltage of 1.5V ~ 4V. .

FIG. 6 compares and simulates the sensing operation of a bitline sense amplifier (see FIG. 2) and a conventional bitline sense amplifier (see FIG. 1) according to the present invention implemented in the same size at a supply voltage of 3V and a voltage difference of 100mV. As a waveform diagram, it can be seen that the bitline sense amplifier of the present invention performs a faster sensing operation than a conventional sense amplifier.

FIG. 7 is a waveform diagram comparing and comparing current consumption when enabling a bit line sense amplifier and a conventional bit line sense amplifier according to the present invention. FIG. You can see that the current consumption is reduced.

Summarizing the simulation results of FIGS. 3 to 7, it can be seen that the current sense amplifier according to the present invention is an amplifier suitable for low voltage and high speed sensing.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above, by detecting and amplifying the current difference instead of the voltage level has the effect of performing a fast and stable sense amplification operation at a low voltage by eliminating the delay time required for a predetermined voltage level during the sense amplification. In addition, the fast sense amplification operation has an effect of faster access to the data stored in the memory cell, and can be applied to personal portable equipment and advanced memory devices requiring low power operation may contribute to the improvement of the performance of the equipment and devices.

Claims (6)

In a bit line sense amplifier of a semiconductor memory device, First and second current mirrors receiving potentials of the positive bit line and the sub bit line as current sources, and detecting current levels of the positive bit line and the sub bit line in response to a sense amplification enable signal. Current sensing means for outputting the output to the positive output terminal and the negative output terminal, Feedback means for amplifying a voltage difference of the signal sensed by the current sensing means in response to the sense amplification enable signal and feeding back to the positive output terminal and the sub output terminal; And a bit line sense amplifier of the semiconductor memory device. The method of claim 1, And precharging and equalizing means for precharging and equalizing the positive output terminal and the sub-output terminal in response to the sense amplification enable signal. The method of claim 2, The current sensing means, First and second PMOS transistors having drain terminals connected to the positive bit line and the sub bit line, respectively, and connected to each other in a current mirror type; First and second NMOS transistors connected to source terminals of the first and second PMOS transistors, respectively, and receiving the sense amplification enable signal through respective gates; Third and fourth PMOS transistors having drain terminals connected to the first and second input signals, respectively, and connected to each other in a current mirror type; Third and fourth NMOS transistors connected to source terminals of the third and fourth PMOS transistors, respectively, and receiving the sense amplification enable signal through respective gates; A common connection terminal of the first PMOS transistor and the first NMOS transistor is connected to the constant output terminal, And a common connection terminal of the fourth PMOS transistor and the fourth NMOS transistor is connected to the sub-output terminal. The method of claim 3, The feedback means, First inverting means having an input terminal connected to a common connection terminal of the first PMOS transistor and the first NMOS transistor and an output terminal connected to a common source terminal of the second and fourth NMOS transistors; Second inverting means having an input terminal connected to a common connection terminal of the fourth PMOS transistor and the fourth NMOS transistor and an output terminal connected to a common source terminal of the first and third NMOS transistors; And And a fifth NMOS transistor connected to a ground power supply terminal and serving as a current source of the first and second inverting means in response to the sense amplification enable signal. The method of claim 4, wherein The first inverting means, A fifth PMOS transistor and a sixth NMOS transistor connected in series between a power supply voltage terminal and a drain terminal of the fifth NMOS transistor, each gate of which is connected to a common connection terminal of the first PMOS transistor and the first NMOS transistor; and, The second inverting means, A sixth PMOS transistor and a seventh NMOS transistor connected in series between a power supply voltage terminal and a drain terminal of the fifth NMOS transistor, each gate of which is connected to a common connection terminal of the fourth PMOS transistor and the fourth NMOS transistor; And a bit line sense amplifier of a semiconductor memory device. The method of claim 3, The precharge and equalization means, The sensing amplification enable signal is applied to a gate, and is connected between a common source terminal of the first and third NMOS transistors and a common source terminal of the second and fourth NMOS transistors to equalize the common source terminals to stabilize each other. A fifth PMOS transistor to ensure sense amplification operation; Sixth and seventh PMOS transistors for precharging the positive output terminal and the sub output terminal to a power supply voltage level in response to the sense amplification enable signal; And And an eighth PMOS transistor for equalizing the positive output signal and the sub output signal in response to the sense amplification enable signal.