KR100355875B1 - 반도체 소자 분리 방법 - Google Patents
반도체 소자 분리 방법 Download PDFInfo
- Publication number
- KR100355875B1 KR100355875B1 KR1019990068478A KR19990068478A KR100355875B1 KR 100355875 B1 KR100355875 B1 KR 100355875B1 KR 1019990068478 A KR1019990068478 A KR 1019990068478A KR 19990068478 A KR19990068478 A KR 19990068478A KR 100355875 B1 KR100355875 B1 KR 100355875B1
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- South Korea
- Prior art keywords
- trench
- film
- nitride film
- etching
- oxide film
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
Claims (3)
- (정정) 반도체 기판에 트렌치를 형성하여 반도체 소자를 분리하는 반도체 소자 분리 방법에 있어서,상기의 반도체 기판 상에 완충 산화막 및 질화막을 연속하여 적층하는 단계;상기의 질화막 상부에 감광막을 도포하고, 마스크를 사용하여 상기의 트렌치를 형성하기 위해 감광막을 노광 및 현상하여 감광막 패턴을 형성하고, 감광막 패턴을 마스크로 하여 상기의 질화막, 완충 산화막 및 반도체 기판을 식각하여 트렌치를 형성하는 트렌치 형성단계;상기의 감광막 패턴을 제거하고, 상기의 질화막을 식각용액에 의해 습식 식각하여 상기의 완충 산화막과 접해 있는 상기의 질화막의 양모서리를 둥굴게 형성하는 질화막 식각 단계;상기의 트렌치 내부에 라이너 산화막을 형성하는 단계;상기의 트렌치가 형성된 반도체 기판 및 습식 식각하여 양모서리가 둥굴게 형성된 질화막 상부에 절연막을 증착하고, 상기의 절연막을 식각하여 상기의 트렌치 내부를 상기의 절연막으로 채우는 트렌치 절연막 패턴을 형성하는 단계;상기의 습식 식각하여 양모서리가 둥굴게 형성된 질화막이 노출될 때까지 상기의 트렌치 절연막 패턴을 연마하는 단계; 및상기의 질화막을 식각하여 제거하는 단계를 구비한 것을 특징으로 하는 반도체 소자 분리 방법.
- 제1항에 있어서, 상기의 질화막 식각 단계에서 식각용액은 인산 용액인 것을 특징으로 하는 반도체 소자 분리 방법.
- 제1항 또는 제2항에 있어서, 상기의 식각용액의 온도는 120℃ 내지 180℃의 범위인 것을 특징으로 하는 반도체 소자 분리 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990068478A KR100355875B1 (ko) | 1999-12-31 | 1999-12-31 | 반도체 소자 분리 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019990068478A KR100355875B1 (ko) | 1999-12-31 | 1999-12-31 | 반도체 소자 분리 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010087468A KR20010087468A (ko) | 2001-09-21 |
KR100355875B1 true KR100355875B1 (ko) | 2002-10-12 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1019990068478A KR100355875B1 (ko) | 1999-12-31 | 1999-12-31 | 반도체 소자 분리 방법 |
Country Status (1)
Country | Link |
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KR (1) | KR100355875B1 (ko) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223747A (ja) * | 1997-02-06 | 1998-08-21 | Nec Corp | 半導体装置の製造方法 |
KR19980084107A (ko) * | 1997-05-21 | 1998-12-05 | 문정환 | 반도체장치의 소자격리방법 |
JPH11186378A (ja) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | 半導体集積回路および半導体集積回路の製造方法並びに半導体装置および半導体装置の製造方法 |
US5930620A (en) * | 1997-09-12 | 1999-07-27 | Advanced Micro Devices | Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures |
KR19990066178A (ko) * | 1998-01-22 | 1999-08-16 | 구본준 | 반도체장치의 소자격리방법 |
JPH11284064A (ja) * | 1998-01-13 | 1999-10-15 | Texas Instr Inc <Ti> | トランジスタの浅いトレンチ分離体を化学的機械的研磨を用いないで作成する方法 |
US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
-
1999
- 1999-12-31 KR KR1019990068478A patent/KR100355875B1/ko not_active IP Right Cessation
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223747A (ja) * | 1997-02-06 | 1998-08-21 | Nec Corp | 半導体装置の製造方法 |
KR19980084107A (ko) * | 1997-05-21 | 1998-12-05 | 문정환 | 반도체장치의 소자격리방법 |
US5930620A (en) * | 1997-09-12 | 1999-07-27 | Advanced Micro Devices | Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures |
US6001706A (en) * | 1997-12-08 | 1999-12-14 | Chartered Semiconductor Manufacturing, Ltd. | Method for making improved shallow trench isolation for semiconductor integrated circuits |
JPH11186378A (ja) * | 1997-12-24 | 1999-07-09 | Mitsubishi Electric Corp | 半導体集積回路および半導体集積回路の製造方法並びに半導体装置および半導体装置の製造方法 |
JPH11284064A (ja) * | 1998-01-13 | 1999-10-15 | Texas Instr Inc <Ti> | トランジスタの浅いトレンチ分離体を化学的機械的研磨を用いないで作成する方法 |
KR19990066178A (ko) * | 1998-01-22 | 1999-08-16 | 구본준 | 반도체장치의 소자격리방법 |
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KR20010087468A (ko) | 2001-09-21 |
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